Hi all,
This seris:
- Move target_signal.h generic defintions to generic/signal.h,
- target_syscall.h remove TARGET_MINSIGSTKSZ,
- Remove unused definitions TARGET_SIGSTKSZ.
V3:
- Rebase
Song Gao (3):
linux-user: Move target_signal.h generic definitions to
generic/signal.h
linux-use
Hi all,
This seris:
- Move target_signal.h generic defintions to generic/signal.h,
- target_syscall.h remove TARGET_MINSIGSTKSZ,
- Remove unused definitions TARGET_SIGSTKSZ.
V3:
- Rebase
Song Gao (3):
linux-user: Move target_signal.h generic definitions to
generic/signal.h
linux-use
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
used as a bus name.
Most common QEMU buses and PCI controllers are named based on their bus
type (e.g. pSer
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
A similar situation as described previously with pnv_phb3_root_port
devices also happens with pnv_phb4_root_ports.
The solution is the same: assign an unique chassis/slot combo for them.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédr
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
pnv_phb4_rc_config_read() and pnv_phb4_rc_config_write() are asserting
the existence of the root port. The root port is now optional, and there
will be cases where a pnv-phb4 device won't have a root port attached.
Instead of asserting, check if th
TARGET_MINSIGSTKSZ has been defined in generic/signal.h
or target_signal.h, We don't need to define it again.
Signed-off-by: Song Gao
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
linux-user/aarch64/target_syscall.h| 1 -
linux-user/alp
No code change
Suggested-by: Richard Henderson
Signed-off-by: Song Gao
Reviewed-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
linux-user/aarch64/target_signal.h| 18 --
linux-user/arm/target_signal.h| 18 --
linux-user/cris/target_signal.h
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
We want to create only the absolutely minimal amount of devices when
running with -nodefaults. The root port is something that the machine
can boot up without. But, to do that, we need to provide a way for the
user to add them by hand.
This patch m
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
When creating a pnv_phb3_root_port using the command line, the first
root port is created successfully, but the second fails with the
following error:
qemu-system-ppc64: -device pnv-phb3-root-port,bus=phb3-root.0,id=pcie.3:
Can't add chassis slot,
On Tue, Dec 14, 2021 at 3:01 AM Frédéric Pétrot
wrote:
>
> The csrs are accessed through function pointers: we add 128-bit read
> operations in the table for three csrs (writes fallback to the
> 64-bit version as the upper 64-bit information is handled elsewhere):
> - misa, as mxl is needed for pr
From: David Hildenbrand
Let's avoid having to manually copy all elements. Copy only the ones
necessary to close the hole and perform the operation in-place without
a second array.
Signed-off-by: David Hildenbrand
Signed-off-by: Raphael Norwitz
Reviewed-by: Stefan Hajnoczi
---
subprojects/lib
Today if QEMU (or any other VMM) has sent multiple copies of the same
region to a libvhost-user based backend and then attempts to remove the
region, only one instance of the region will be removed, leaving stale
copies of the region in dev->regions[].
This change resolves this by having vu_rem_me
Hey Stefan, Marc-Andre, MST, David -
As promised here is a series cleaning up error handling in the
libvhost-user memory mapping path. Most of these cleanups are
straightforward and have been discussed on the mailing list in threads
[1] and [2].
[1]
https://lore.kernel.org/qemu-devel/20211018143
When VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS support was added to
libvhost-user, no guardrails were added to protect against QEMU
attempting to hot-add too many RAM slots to a VM with a libvhost-user
based backed attached.
This change adds the missing error handling by introducing a check on
the
Signed-off-by: Raphael Norwitz
---
subprojects/libvhost-user/libvhost-user.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/subprojects/libvhost-user/libvhost-user.c
b/subprojects/libvhost-user/libvhost-user.c
index a6dadeb637..d61285e991 100644
--- a/subprojects/libvhost-user/libvhos
Signed-off-by: Raphael Norwitz
---
subprojects/libvhost-user/libvhost-user.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/subprojects/libvhost-user/libvhost-user.c
b/subprojects/libvhost-user/libvhost-user.c
index 787f4d2d4f..a6dadeb637 100644
--- a/subprojects/libvhost-user/libvhos
On Wed, Jan 05, 2022 at 05:40:29PM -0300, Fabiano Rosas wrote:
> Next patches will split powerpc_excp in multiple family specific
> handlers. This patch adds a wrapper to make the transition clearer.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c |
On Wed, Jan 05, 2022 at 05:40:24PM -0300, Fabiano Rosas wrote:
> Remove the compile time definition and make the logging be controlled
> by the `-d mmu` option in the cmdline.
>
> Signed-off-by: Fabiano Rosas
> Reviewed-by: Cédric Le Goater
Reviewed-by: David Gibson
I'm guessing from the text
On Wed, Jan 05, 2022 at 11:18:52AM +, Stefan Hajnoczi wrote:
> On Wed, Dec 15, 2021 at 10:29:55PM +, Raphael Norwitz wrote:
> > diff --git a/subprojects/libvhost-user/libvhost-user.c
> > b/subprojects/libvhost-user/libvhost-user.c
> > index 74a9980194..2f465a4f0e 100644
> > --- a/subprojec
On Wed, Jan 05, 2022 at 05:40:28PM -0300, Fabiano Rosas wrote:
> The ppc_interrupts_little_endian function is now suitable for
> determining the endianness of interrupts for all CPUs.
>
> Signed-off-by: Fabiano Rosas
Nice!
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 29 +
On Wed, Jan 05, 2022 at 05:40:27PM -0300, Fabiano Rosas wrote:
> Some CPUs set ILE via an MSR bit. We can make
> ppc_interrupts_little_endian handle that case as well. Now we have a
> centralized way of determining the endianness of interrupts.
>
> This change has no functional impact.
>
> Signed
On Wed, Jan 05, 2022 at 05:40:25PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
> Reviewed-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 77 +---
> 1 file changed, 8 insertions(+), 69 deletions(-)
>
> diff
On Wed, Jan 05, 2022 at 05:40:26PM -0300, Fabiano Rosas wrote:
> The ppc_interrupts_little_endian function could be used for interrupts
> delivered in Hypervisor mode, so add support for powernv8 and powernv9
> to it.
>
> Also drop the comment because it is inaccurate, all CPUs that can run
> litt
On Wed, Jan 05, 2022 at 11:00:35AM +, Stefan Hajnoczi wrote:
> On Wed, Dec 15, 2021 at 10:29:48PM +, Raphael Norwitz wrote:
> > Signed-off-by: Raphael Norwitz
> > ---
> > subprojects/libvhost-user/libvhost-user.c | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/subpro
On Wed, Jan 05, 2022 at 05:40:23PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 63 +++-
> 1 file changed, 36 insertions(+), 27 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c
在 2021/12/11 下午6:44, Vladislav Yaroshchuk 写道:
macOS provides networking API for VMs called 'vmnet.framework':
https://developer.apple.com/documentation/vmnet
We can provide its support as the new QEMU network backends which
represent three different vmnet.framework interface usage modes:
*
On 1/5/22 11:08 AM, Thomas Huth wrote:
The "gtk" variable is re-declared as "dependencies: [gtk, gtkx11]",
so there is just a "YES" in the summary info if gtk has been found.
Let's use the info from the library detection instead so that the
library version is printed in the summary instead.
Sign
On Tue, Dec 21, 2021 at 5:30 PM Bin Meng wrote:
>
> On Mon, Dec 20, 2021 at 2:49 PM Alistair Francis
> wrote:
> >
> > From: Alistair Francis
> >
> > In preperation for adding support for the illegal instruction address
>
> typo: preparation
Fixed
>
> > let's fixup the Hypervisor extension sett
在 2022/1/6 上午12:45, Patrick Venture 写道:
From: Peter Foley
Match the other error handling in this function.
Fixes: e7b347d0bf6 ("net: detect errors from probing vnet hdr flag for TAP
devices")
Reviewed-by: Patrick Venture
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Foley
---
On 1/5/22 9:44 AM, WANG Xuerui wrote:
+static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg,
+ unsigned a_bits)
+{
+TCGLabelQemuLdst *l = new_ldst_label(s);
+
+l->is_ld = is_ld;
+l->addrlo_reg = addr_reg;
+
+tcg_debug_asse
> -Original Message-
> From: Stefano Garzarella [mailto:sgarz...@redhat.com]
> Sent: Wednesday, January 5, 2022 7:16 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: stefa...@redhat.com; m...@redhat.com; jasow...@redhat.com;
> coh...@redhat.com; pbonz...@redh
> -Original Message-
> From: Stefan Hajnoczi [mailto:stefa...@redhat.com]
> Sent: Wednesday, January 5, 2022 6:18 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: m...@redhat.com; jasow...@redhat.com; sgarz...@redhat.com;
> coh...@redhat.com; pbonz...@redhat.
On 1/5/22 9:09 AM, Stevie Lavern wrote:
Hello,
I'm currently testing various binaries under qemu linux user and went into a
strange bug.
Here is the TLDR: is there a reason to allow VEX.L to be 1 when not supporting AVX
instructions?
There are some integer instructions that use vex encoding,
> -Original Message-
> From: Stefano Garzarella [mailto:sgarz...@redhat.com]
> Sent: Wednesday, January 5, 2022 7:29 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: stefa...@redhat.com; m...@redhat.com; jasow...@redhat.com;
> coh...@redhat.com; pbonz...@redh
> -Original Message-
> From: Stefan Hajnoczi [mailto:stefa...@redhat.com]
> Sent: Wednesday, January 5, 2022 6:01 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: m...@redhat.com; jasow...@redhat.com; sgarz...@redhat.com;
> coh...@redhat.com; pbonz...@redhat.
On Wed, Jan 5, 2022 at 8:26 PM Michael S. Tsirkin wrote:
>
> On Wed, Jan 05, 2022 at 05:09:07PM +0800, Jason Wang wrote:
> > On Wed, Jan 5, 2022 at 4:37 PM Longpeng (Mike, Cloud Infrastructure
> > Service Product Dept.) wrote:
> > >
> > >
> > >
> > > > -Original Message-
> > > > From: Jas
On Tue, Dec 14, 2021 at 2:48 AM Frédéric Pétrot
wrote:
>
> As opposed to the gen_arith and gen_shift generation helpers, the csr insns
> do not have a common prototype, so the choice to generate 32/64 or 128-bit
> helper calls is done in the trans_csrxx functions.
>
> Signed-off-by: Frédéric Pétro
> -Original Message-
> From: Cornelia Huck [mailto:coh...@redhat.com]
> Sent: Wednesday, January 5, 2022 6:46 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
> ; stefa...@redhat.com; m...@redhat.com;
> jasow...@redhat.com; sgarz...@redhat.com
> Cc: pbonz...@redhat.co
On Tue, Dec 14, 2021 at 2:46 AM Frédéric Pétrot
wrote:
>
> Given the side effects they have, the csr instructions are realized as
> helpers. We extend this existing infrastructure for 128-bit sized csr.
> We return 128-bit values using the same approach as for div/rem.
> Theses helpers all call a
On Tue, Dec 14, 2021 at 2:55 AM Frédéric Pétrot
wrote:
>
> Mult are generated inline (using a cool trick pointed out by Richard), but
> for div and rem, given the complexity of the implementation of these
> instructions, we call helpers to produce their behavior. From an
> implementation standpoin
> -Original Message-
> From: Stefan Hajnoczi [mailto:stefa...@redhat.com]
> Sent: Wednesday, January 5, 2022 5:49 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: m...@redhat.com; jasow...@redhat.com; sgarz...@redhat.com;
> coh...@redhat.com; pbonz...@redhat.
On Tue, Dec 14, 2021 at 2:44 AM Frédéric Pétrot
wrote:
>
> Addition of 128-bit adds and subs in their various sizes,
> "set if less than"s and branches.
> Refactored the code to have a comparison function used for both stls and
> branches.
>
> Signed-off-by: Frédéric Pétrot
> Co-authored-by: Fabi
Cc'ing Mark for macio which seems to have the same issue.
On 5/1/22 12:13, Hanna Reitz wrote:
When we still have an AIOCB registered for DMA operations, we try to
settle the respective operation by draining the BlockBackend associated
with the IDE device.
However, this assumes that every DMA op
When building on macOS 12 we get:
../block/file-posix.c:3335:18: warning: 'IOMasterPort' is deprecated: first
deprecated in macOS 12.0 [-Wdeprecated-declarations]
kernResult = IOMasterPort( MACH_PORT_NULL, &masterPort );
^~~~
IOMainPort
Use I
On 1/5/2022 6:09 PM, Michael S. Tsirkin wrote:
> On Wed, Jan 05, 2022 at 04:40:43PM -0500, Steven Sistare wrote:
>> On 1/5/2022 4:14 PM, Michael S. Tsirkin wrote:
>>> On Wed, Jan 05, 2022 at 12:24:21PM -0500, Steven Sistare wrote:
On 12/22/2021 6:15 PM, Michael S. Tsirkin wrote:
> On Wed,
On Wed, Jan 05, 2022 at 04:40:43PM -0500, Steven Sistare wrote:
> On 1/5/2022 4:14 PM, Michael S. Tsirkin wrote:
> > On Wed, Jan 05, 2022 at 12:24:21PM -0500, Steven Sistare wrote:
> >> On 12/22/2021 6:15 PM, Michael S. Tsirkin wrote:
> >>> On Wed, Dec 22, 2021 at 11:05:24AM -0800, Steve Sistare wr
On Wed, Jan 05, 2022 at 07:31:33PM +0100, Greg Kroah-Hartman wrote:
> There are currently 2 ways to create a set of sysfs files for a
> kobj_type, through the default_attrs field, and the default_groups
> field. Move the firmware qemu_fw_cfg sysfs code to use default_groups
> field which has been
On Wed, Jan 05, 2022 at 03:12:26PM -0700, Alex Williamson wrote:
> On Wed, 5 Jan 2022 16:05:45 -0500
> "Michael S. Tsirkin" wrote:
>
> > On Wed, Jan 05, 2022 at 12:56:42PM -0700, Alex Williamson wrote:
> > > The VFIO_DEVICE_RESET ioctl might be backed by several different reset
> > > methods, inc
On Wed, Jan 5, 2022 at 12:23 PM wrote:
>
> From: Frank Chang
>
> For vector widening and narrowing floating-point instructions, we should
> use require_scale_rvf() instead of require_rvf() to check whether the
> correspond RVF/RVD is enabled if either source or destination
> floating-point operan
On Thu, Jan 6, 2022 at 7:55 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> This is a few patches to cleanup some RISC-V hardware and mark the
> Hyperisor extension as non experimental.
>
> v4:
> - Resend
> v3:
> - Drop some patches
> - Few small fixes from reviews
> v2:
> - Add som
On Wed, Jan 5, 2022 at 11:58 AM Bin Meng wrote:
>
> Upgrade OpenSBI from v0.9 to v1.0 and the pre-built bios images.
>
> The v1.0 release includes the following commits:
>
> ec5274b platform: implement K210 system reset
> 5487cf0 include: sbi: Simplify HSM state define names
> 8df1f9a lib: sbi: Us
On Tue, Dec 21, 2021 at 2:44 AM Yifei Jiang via wrote:
>
> Add virtual time context description to vmstate_kvmtimer. After cpu being
> loaded, virtual time context is updated to KVM.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Anup Patel
Reviewed-by: Alistair Fra
From: Alistair Francis
When realising the SoC use error_fatal instead of error_abort as the
process can fail and report useful information to the user.
Currently a user can see this:
$ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display
none -drive if=pflash
QEMU 6.1.
On Wed, 5 Jan 2022 16:05:45 -0500
"Michael S. Tsirkin" wrote:
> On Wed, Jan 05, 2022 at 12:56:42PM -0700, Alex Williamson wrote:
> > The VFIO_DEVICE_RESET ioctl might be backed by several different reset
> > methods, including a device specific reset (ie. custom reset code in
> > kernel), an ACPI
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/intc/sifive_plic.c | 76 +++
1 file changed, 27 insertions(+), 49 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index a9f7a1bfb0..698492ce77 10
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/intc/sifive_plic.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 877e76877c..a9f7a1bfb0 100644
From: Alistair Francis
Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
let's set that as the maximum for the virt board.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
Signed-off-by: Alistair Francis
Reviewed-by: Anup Patel
Reviewed-by: Philippe Mathieu-Daudé
From: Alistair Francis
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/intc/sifive_plic.c | 55 +--
1 file changed, 11 insertions(+), 44 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 698492ce77..44d24b3c59 10
On Tue, Dec 21, 2021 at 3:41 AM Yifei Jiang via wrote:
>
> Use char-fe to handle console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Anup Patel
> ---
> target/riscv/kv
On Tue, Dec 21, 2021 at 3:45 AM Yifei Jiang via wrote:
>
> We hope that virtual time adjusts with vm state changing. When a vm
> is stopped, guest virtual time should stop counting and kvm_timer
> should be stopped. When the vm is resumed, guest virtual time should
> continue to count and kvm_time
From: Alistair Francis
The Hypervisor spec is now frozen, so remove the experimental tag.
Signed-off-by: Alistair Francis
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv
Hello Sir/Ma'am,
I am Aakarshit Agarwal, final year student pursuing B.Tech in computer
science with a specialization in DevOps from UPES Dehradun. I love the
topic and technologies you used for GSoC'21. I would love to contribute to
your organization for GSoC'22 and know more about it.
Can you p
Hi Thomas,
I intentionally sent the email via my gmx address. But I want my commit under
the infinite-omicron email address.
I had a few warnings on my end, but it builds fine with Sphinx v3.4.3 on Debian
Bullseye. I can clean up the warnings in the new patch.
Yeah, it renders fine.
Let me su
From: Alistair Francis
This is a few patches to cleanup some RISC-V hardware and mark the
Hyperisor extension as non experimental.
v4:
- Resend
v3:
- Drop some patches
- Few small fixes from reviews
v2:
- Add some more fixes
- Address review comments
Alistair Francis (8):
hw/intc: sifive
From: Alistair Francis
We can remove the original sifive_plic_irqs_pending() function and
instead just use the sifive_plic_claim() function (renamed to
sifive_plic_claimed()) to determine if any interrupts are pending.
This requires move the side effects outside of sifive_plic_claimed(),
but as
On Thu, Nov 4, 2021 at 4:47 AM Bin Meng wrote:
>
> On Tue, Oct 26, 2021 at 4:41 AM Atish Patra wrote:
> >
> > The RISC-V privilege specification provides flexibility to implement
> > any number of counters from 29 programmable counters. However, the QEMU
> > implements all the counters.
> >
> > M
On Thu, Nov 4, 2021 at 4:11 AM Bin Meng wrote:
>
> On Tue, Oct 26, 2021 at 4:02 AM Atish Patra wrote:
> >
> > The PMU counters are supported via cpu config "Counters" which doesn't
> > indicate the correct purpose of those counters.
> >
> > Rename the config property to pmu to indicate that these
On Thu, Dec 30, 2021 at 11:06 PM Anup Patel wrote:
>
> From: Anup Patel
>
> To facilitate software development of RISC-V systems with large number
> of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
>
> We also add a detailed source level comments about limit defines which
>
On Wed, Jan 5, 2022 at 12:24 PM wrote:
>
> From: Frank Chang
>
> vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
> floating-point. Therefore, should use require_rvf() to check whether
> RVF/RVD is enabled.
>
> vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-p
On Wed, Jan 5, 2022 at 12:25 PM wrote:
>
> From: Frank Chang
>
> vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
> convert single-width floating-point to double-width integer.
> Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
>
> vfwcvt.f.xu.v, vfwcvt.
On Wed, Jan 5, 2022 at 12:24 PM wrote:
>
> From: Frank Chang
>
> Vector widening floating-point instructions should use
> require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
> enabled.
>
> Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Alistair
> ---
> target/ris
On Thu, Nov 4, 2021 at 4:08 AM Bin Meng wrote:
>
> On Tue, Oct 26, 2021 at 3:56 AM Atish Patra wrote:
> >
>
> The commit title is incomplete
>
Oops. Fixed it.
>
> > Currently, the predicate function for PMU related CSRs only works if
> > virtualization is enabled. It also does not check mcounte
On Wed, Jan 5, 2022 at 11:58 AM Bin Meng wrote:
>
> Upgrade OpenSBI from v0.9 to v1.0 and the pre-built bios images.
>
> The v1.0 release includes the following commits:
>
> ec5274b platform: implement K210 system reset
> 5487cf0 include: sbi: Simplify HSM state define names
> 8df1f9a lib: sbi: Us
On 1/5/2022 4:14 PM, Michael S. Tsirkin wrote:
> On Wed, Jan 05, 2022 at 12:24:21PM -0500, Steven Sistare wrote:
>> On 12/22/2021 6:15 PM, Michael S. Tsirkin wrote:
>>> On Wed, Dec 22, 2021 at 11:05:24AM -0800, Steve Sistare wrote:
Enable vfio-pci devices to be saved and restored across an exe
The XSCOM address space of the stack must be populated after the
initialization of its associated PHB4 is completed. At this moment this
is always true because stk_realize() will always succeeds the realize of
stack->phb, but that will not be the case with user creatable pnv-phb4
devices.
Create a
On 1/3/22 10:05 AM, Marc Zyngier wrote:
-/*
- * KVM does not support modifications to this feature.
- * We have not registered the cpu properties when KVM
- * is in use, so the user will not be able to set them.
- */
-if (!kvm_enabled()) {
-
At this moment, stack->phb is the plain PnvPHB4 device itself instead
of a pointer to the device. This will present a problem when adding user
creatable devices because we can't deal with this struct and the
realize() callback from the user creatable device.
We can't get rid of this attribute, sim
The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
used as a bus name.
Most common QEMU buses and PCI controllers are named based on their bus
type (e.g. pSeries spapr-pci-host-bridge is called 'pci'). The mo
Relying on stack->phb to write the xscom DT of the PEC is something that
we won't be able to do with user creatable pnv-phb4 devices.
Hopefully, this can be done by using pnv_phb4_pec_get_phb_id(), which is
already used by pnv_pec_realize() to set the phb-id of the stack. Use
the same idea in pnv_
From: Cédric Le Goater
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3 device is parented to i
We want to be able to support user creatable pnv-phb4 objects to allow
users to instantiate a powernv9 machine similar to what it is done with
powernv8.
The main difference is that pnv-phb3 devs are attached directly to the
system bus and can be created in the command line. PCI devices such as
roo
From: Cédric Le Goater
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a lookup on 'chip-id' is r
From: Cédric Le Goater
It is not used elsewhere so that's where it belongs.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 7 +++
include/hw/ppc/pnv.h | 4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8dc6382357..fe7e67e7
pnv_phb4_rc_config_read() and pnv_phb4_rc_config_write() are asserting
the existence of the root port. The root port is now optional, and there
will be cases where a pnv-phb4 device won't have a root port attached.
Instead of asserting, check if the root port exists before read/writing
into it.
S
From: Cédric Le Goater
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 9 +
hw/ppc/pnv.c | 2 ++
2 files changed, 11 insertions(+)
diff --git a/hw/pc
Similar to what was happening with pnv-phb3 buses,
TYPE_PNV_PHB4_ROOT_BUS set to "pnv-phb4-root-bus" is a bit too long for
a default root bus name. The usual default name for theses buses in QEMU
are 'pcie', but we want to make a distinction between pnv-phb4 buses and
other PCIE buses, at least as
We want to create only the absolutely minimal amount of devices when
running with -nodefaults. The root port is something that the machine
can boot up without. But, to do that, we need to provide a way for the
user to add them by hand.
This patch makes pnv-phb4-root-port user creatable and then us
This patch introduces pnv-phb4 user creatable devices that are created
in a similar manner as pnv-phb3 devices, allowing the user to interact
with the PHBs directly instead of creating PCI Express Controllers that
will create a certain amount of PHBs per controller index.
First thing we need is to
The next step before enabling user creatable pnv-phb4 devices is to
decople the init of the stack->phb object from
pnv_pec_stk_instance_init().
First, use 'defaults_enabled()' inside pnv_pec_realize() to create the
stack->phb object, while removing the equivalent object_initiate_child()
call from
From: Cédric Le Goater
This cleanups the PHB3 model a bit more since the root port is an
independent device and it will ease our task when adding user created
PHB3s.
pnv_phb_attach_root_port() is made public in pnv.c so it can be reused
with the pnv_phb4 root port later.
Signed-off-by: Cédric L
The logic inside pnv_pec_phb_offset() will be useful in the next patch
to determine the stack that should contain a PHB4 device.
Move the function to pnv_phb4.c and make it public since there's no
pnv_phb4_pec.h header. While we're at it, add 'stack_index' as a
parameter and make the function retu
A similar situation as described previously with pnv_phb3_root_port
devices also happens with pnv_phb4_root_ports.
The solution is the same: assign an unique chassis/slot combo for them.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 15 +++
1 file changed, 15 i
When creating a pnv_phb3_root_port using the command line, the first
root port is created successfully, but the second fails with the
following error:
qemu-system-ppc64: -device pnv-phb3-root-port,bus=phb3-root.0,id=pcie.3:
Can't add chassis slot, error -16
This error comes from the realize() fun
Hi,
This second version was rebased with upstream and includes fixed/amended
versions of relevant patches that were sent to the mailing list and aren't
upstream yet. In this process 4 patches from v1 were discarded, becoming
either irrelevant or squashed into others.
The patches are organized as
On Wed, Jan 05, 2022 at 12:24:21PM -0500, Steven Sistare wrote:
> On 12/22/2021 6:15 PM, Michael S. Tsirkin wrote:
> > On Wed, Dec 22, 2021 at 11:05:24AM -0800, Steve Sistare wrote:
> >> Enable vfio-pci devices to be saved and restored across an exec restart
> >> of qemu.
> >>
> >> At vfio creation
Philippe Mathieu-Daudé writes:
> Hi Alex,
>
> On 5/1/22 19:03, Alex Bennée wrote:
>> Hi,
>> I'm having a hell of a time trying to create a new SoC+Board model
>> from
>> scratch. The problem comes down to trying to expose some properties to
>> the underlying CPU from my board model. So I have:
On Wed, Jan 05, 2022 at 12:56:42PM -0700, Alex Williamson wrote:
> The VFIO_DEVICE_RESET ioctl might be backed by several different reset
> methods, including a device specific reset (ie. custom reset code in
> kernel), an ACPI reset (ie. custom reset code in firmware), FLR, PM,
> and bus resets.
From: Lucas Ramage
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/527
Signed-off-by: Lucas Ramage
---
docs/{can.txt => system/can.rst} | 92 ++--
docs/system/index.rst| 1 +
2 files changed, 42 insertions(+), 51 deletions(-)
rename docs/{can.txt
On Wed, Jan 05, 2022, Yan Zhao wrote:
> Sorry, maybe I didn't express it clearly.
>
> As in the kvm_faultin_pfn_private(),
> static bool kvm_faultin_pfn_private(struct kvm_vcpu *vcpu,
> struct kvm_page_fault *fault,
> bool *is_pr
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