On Fri, Dec 10, 2021 at 10:35 PM Jean-Philippe Brucker
wrote:
>
> Add ACPI support for virtio-iommu on the virt machine, by instantiating
> a VIOT table. Also add the tests for the ACPI table.
>
> Since last posting [1], I rebased onto v6.2.0-rc4. Note that v6 of this
> series [2] only contained t
The ITS has several tables which all share a similar format,
described by the TableDesc struct: the guest may configure them
to be a single-level table or a two-level table. Currently we
open-code the process of finding the table entry in all the
functions which read or write the device table or th
When an ITS detects an error in a command, it has an
implementation-defined (CONSTRAINED UNPREDICTABLE) choice of whether
to ignore the command, proceeding to the next one in the queue, or to
stall the ITS command queue, processing nothing further. The
behaviour required when the read of the comma
In process_cmdq(), we read 64 bits of the command packet, which
contain the command identifier, which we then switch() on to dispatch
to an appropriate sub-function. However, if address_space_ldq_le()
reports a memory transaction failure, we still read the command
identifier out of the data and sw
Fix process_mapti() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
dif
The MAPI command takes arguments DeviceID, EventID, ICID, and is
defined to be equivalent to MAPTI DeviceID, EventID, EventID, ICID.
(That is, where MAPTI takes an explicit pINTID, MAPI uses the EventID
as the pINTID.)
We didn't quite get this right. In particular the error checks for
MAPI includ
The ITS code has to check whether various parameters passed in
commands are in-bounds, where the limit is defined in terms of the
number of bits that are available for the parameter. (For example,
the GITS_TYPER.Devbits ID register field specifies the number of
DeviceID bits minus 1, and device ID
Fix process_mapc() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gi
Fix process_its_cmd() to consistently return CMD_STALL for
memory errors and CMD_CONTINUE for parameter errors, as
we claim in the comments that we do.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --
Refactor process_its_cmd() so that it consistently uses
the structure
do thing;
if (error condition) {
return early;
}
do next thing;
rather than doing some of the work nested inside if (not error)
code blocks.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 103 +++
Fix process_mapd() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm
process_its_cmd() returns a bool, like all the other process_ functions.
However we were putting its return value into 'res', not 'result',
which meant we would ignore it when deciding whether to continue
or stall the command queue. Fix the typo.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv
In several places we have a local variable max_l2_entries which is
the number of entries which will fit in a level 2 table. The
calculations done on this value are correct; rename it to
num_l2_entries to fit the convention we're using in this code.
Signed-off-by: Peter Maydell
---
hw/intc/arm_g
Use FIELD macros to handle CTEs, rather than ad-hoc mask-and-shift.
Signed-off-by: Peter Maydell
---
hw/intc/gicv3_internal.h | 3 ++-
hw/intc/arm_gicv3_its.c | 7 ---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 14
The comment says that in our CTE format the RDBase field is 36 bits;
in fact for us it is only 16 bits, because we use the RDBase format
where it specifies a 16-bit CPU number. The code already uses
RDBASE_PROCNUM_LENGTH (16) as the field width, so fix the comment
to match it.
Signed-off-by: Peter
We set the TableDesc entry_sz field from the appropriate
GITS_BASER.ENTRYSIZE field. That ID register field specifies the
number of bytes per table entry minus one. However when we use
td->entry_sz we assume it to be the number of bytes per table entry
(for instance we calculate the number of ent
In process_its_cmd() and process_mapti() we must check the
event ID against a limit defined by the size field in the DTE,
which specifies the number of ID bits minus one. Convert
this code to our num_foo convention, fixing the off-by-one error.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_
The bounds check on the number of interrupt IDs is correct, but
doesn't match our convention; change the variable name, initialize it
to the 2^n value rather than (2^n)-1, and use >= instead of > in the
comparison.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 6 +++---
1 file chang
Currently the ITS code that reads and writes DTEs uses open-coded
shift-and-mask to assemble the various fields into the 64-bit DTE
word. The names of the macros used for mask and shift values are
also somewhat inconsistent, and don't follow our usual convention
that a MASK macro should specify th
The GITS_TYPE_PHYSICAL define is the value we set the
GITS_TYPER.Physical field to -- this is 1 to indicate that we support
physical LPIs. (Support for virtual LPIs is the GITS_TYPER.Virtual
field.) We also use this define as the *value* that we write into an
interrupt translation table entry's IN
The DTE.SIZE field is 5 bits, which means that DTE.SIZE + 1
might in theory be 32. When calculating 1 << (DTE.SIZE + 1)
use 1ULL to ensure that we don't do this arithmetic at 32 bits
and shift the 1 off the end in this case.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 4 ++--
1 fi
The extract_table_params() decodes the fields in the GITS_BASER
registers into TableDesc structs. Since the fields are the same for
all the GITS_BASER registers, there is currently a lot of code
duplication within the switch (type) statement. Refactor so that the
cases include only what is genuin
The TableDesc struct defines properties of the in-guest-memory tables
which the guest tells us about by writing to the GITS_BASER
registers. This struct currently has a union 'maxids', but all the
fields of the union have the same type (uint32_t) and do the same
thing (record one-greater-than the
In extract_table_params() we process each GITS_BASER register. If
the register's Valid bit is not set, this means there is no
in-guest-memory table and so we should not try to interpret the other
fields in the register. This was incorrectly coded as a 'return'
rather than a 'break', so instead of
The checks in the ITS on the rdbase values in guest commands are
off-by-one: they permit the guest to pass us a value equal to
s->gicv3->num_cpu, but the valid values are 0...num_cpu-1. This
meant the guest could cause us to index off the end of the
s->gicv3->cpu[] array when calling gicv3_redist_
We currently define a bitmask for the GITS_CTLR ENABLED bit in
two ways: as ITS_CTLR_ENABLED, and via the FIELD() macro as
R_GITS_CTLR_ENABLED_MASK. Consistently use the FIELD macro version
everywhere and remove the redundant ITS_CTLR_ENABLED define.
Signed-off-by: Peter Maydell
---
hw/intc/gicv
From: Alex Bennée
While trying to debug a GIC ITS failure I saw some guest errors that
had poor formatting as well as leaving me confused as to what failed.
As most of the checks aren't possible without a valid dte split that
check apart and then check the other conditions in steps. This avoids
u
I've been working on the ITS to add support for the GICv4 functionality.
In the course of that I found a handful of bugs in it and also some
places where the code benefited from refactoring to make it a better
base to put in the GICv4 parts. This patchset is just the bugfixes
and cleanups, because
On 12/10/21 6:13 AM, Victor Colombo wrote:
Signed-off-by: Victor Colombo
---
target/ppc/insn32.decode| 17 +---
target/ppc/translate/vsx-impl.c.inc | 30 +
target/ppc/translate/vsx-ops.c.inc | 4
3 files changed, 40 insertions(+), 11
On 12/10/21 8:19 AM, Matheus K. Ferst wrote:
On 10/12/2021 11:13, Victor Colombo wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 10 +++---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 4
ta
On 12/10/21 6:13 AM, Victor Colombo wrote:
From: Matheus Ferst
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Signed-off-by: Matheus Ferst
---
target/ppc/translate/vsx-impl.c.inc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
On 12/10/21 6:13 AM, Victor Colombo wrote:
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them ve
On 12/9/21 9:33 AM, Fabiano Rosas wrote:
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TC
From: Longpeng
This patchset moves the call to kvm_irqchip_commit_routes() out of
kvm_irqchip_add_msi_route(). An optimization of vfio migration [1]
depends on this changes.
[1] https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg00968.html
Longpeng (Mike) (2):
kvm-irqchip: introduce new
From: Longpeng
As suggested by Paolo [1], add the new API to support route changes.
We should invoke kvm_irqchip_begin_route_changes() before changing the
routes, increase the KVMRouteChange.changes if the routes are changed,
and commit the changes at last.
[1] https://lists.gnu.org/archive/html
From: Longpeng
We invoke commit operation for each addition to msi route table, this
is not efficient if we are adding lots of routes in some cases (e.g.
the resume phase of vfio migration [1]).
This patch moves the call to kvm_irqchip_commit_routes() to the callers,
so the callers can decide ho
Create separate netdevs for each vmnet operating mode:
- vmnet-host
- vmnet-shared
- vmnet-bridged
Signed-off-by: Vladislav Yaroshchuk
---
net/clients.h | 11
net/meson.build | 7 +++
net/net.c | 10
net/vmnet-bridged.m | 25 +
net/vmnet-common.m | 20
macOS provides networking API for VMs called 'vmnet.framework':
https://developer.apple.com/documentation/vmnet
We can provide its support as the new QEMU network backends which
represent three different vmnet.framework interface usage modes:
* `vmnet-shared`:
allows the guest to communicat
Signed-off-by: Vladislav Yaroshchuk
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..5c696e38da 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2631,6 +2631,11 @@ W: http://info.iet.unipi.it/~luigi/netmap/
S: Maintained
F: net/n
Signed-off-by: Vladislav Yaroshchuk
---
qemu-options.hx | 25 +
1 file changed, 25 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index ae2c6dbbfc..1ffa5eedd5 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -2677,6 +2677,25 @@ DEF("netdev", HAS_ARG, QE
Signed-off-by: Vladislav Yaroshchuk
---
net/vmnet-host.c | 93
1 file changed, 87 insertions(+), 6 deletions(-)
diff --git a/net/vmnet-host.c b/net/vmnet-host.c
index 4a5ef99dc7..9c2e760ed1 100644
--- a/net/vmnet-host.c
+++ b/net/vmnet-host.c
@@ -
Interaction with vmnet.framework in different modes
differs only on configuration stage, so we can create
common `send`, `receive`, etc. procedures and reuse them.
vmnet.framework supports iov, but writing more than
one iov into vmnet interface fails with
'VMNET_INVALID_ARGUMENT'. Collecting provi
Signed-off-by: Vladislav Yaroshchuk
---
meson.build | 4
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 3 +++
3 files changed, 9 insertions(+)
diff --git a/meson.build b/meson.build
index 96de1a6ef9..ce8acf6ada 100644
--- a/meson.build
+++ b/meson.b
Signed-off-by: Vladislav Yaroshchuk
---
net/vmnet-bridged.m | 98 ++---
1 file changed, 92 insertions(+), 6 deletions(-)
diff --git a/net/vmnet-bridged.m b/net/vmnet-bridged.m
index 4e42a90391..3c9da9dc8b 100644
--- a/net/vmnet-bridged.m
+++ b/net/vmnet-br
There seems to be difference in syscall and libc definition of these
methods and therefore musl does not implement them (1e21e78bf7). Call
syscall directly to ensure the behavior of the libc of user application,
not the libc that was used to build QEMU.
Signed-off-by: Tonis Tiigi
---
linux-user/
Signed-off-by: Tonis Tiigi
---
linux-user/syscall.c | 55 +++
linux-user/syscall_defs.h | 15 +++
2 files changed, 70 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index f1cfcc8104..670b61b2ef 100644
--- a/linux-user/sysca
This patchset improves support for sched_* syscalls under user emulation. The
first commit adds support for sched_g/setattr that was previously not
implemented. There is no equivalent for these syscalls in libc, so I needed to
redefine the struct from kernel. It can't be included directly becaus
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