[PATCH v11 02/77] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..70f58981

[PATCH v11 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 16 target/riscv/cpu.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target

Re: [PATCH 3/4] Move CONFIG_XFS handling to meson.build

On 02/11/2021 12.34, Paolo Bonzini wrote: On 28/10/21 20:59, Thomas Huth wrote: Checking for xfsctl() can be done more easily in meson.build. Also, this is not a "real" feature like the other features that we provide with the "--enable-xxx" and "--disable-xxx" switches for the configure script,

[PATCH v6 8/8] target/riscv: zfh: add Zfhmin cpu property

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0f808a5bee..9835829588 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -630,6 +630,7 @

[PATCH v6 4/8] target/riscv: zfh: half-precision floating-point compare

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/fpu_helper.c | 21 + target/riscv/helper.h | 3 ++ target/riscv/i

[PATCH v6 6/8] target/riscv: zfh: add Zfh cpu property

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..0f808a5bee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -629,6 +629,7 @

[PATCH v6 7/8] target/riscv: zfh: implement zfhmin extension

From: Frank Chang Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h,

[PATCH v6 1/8] target/riscv: zfh: half-precision load and store

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h| 1 + target/riscv/insn32.decode| 4 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 65 ++

[PATCH v6 2/8] target/riscv: zfh: half-precision computational

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/fpu_helper.c | 86 +++ target/riscv/helper.h | 13 +++ target/ri

[PATCH v6 5/8] target/riscv: zfh: half-precision floating-point classify

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/fpu_helper.c | 6 ++ target/riscv/helper.h | 1 + target/riscv/insn32.de

[PATCH v6 3/8] target/riscv: zfh: half-precision convert and move

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/fpu_helper.c | 67 + target/riscv/helper.h | 12 + target/riscv/insn32.deco

[PATCH v6 0/8] target/riscv: support Zfh, Zfhmin extension v0.1

From: Frank Chang Zfh - Half width floating point Zfhmin - Subset of half width floating point Zfh, Zfhmin v0.1 is now in public review period and is required by RVV extension: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/63gDCinXTwE/m/871Wm9XIBQAJ Zfh, Zfhmin can be enabled with -c

Re: [PATCH v10 00/77] support vector extension v1.0

On Wed, Dec 8, 2021 at 2:40 PM Alistair Francis wrote: > On Mon, Nov 29, 2021 at 1:04 PM wrote: > > > > From: Frank Chang > > > > This patchset implements the vector extension v1.0 for RISC-V on QEMU. > > > > RVV v1.0 spec is now fronzen for public review: > > https://github.com/riscv/riscv-v-s

Re: [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation

Alistair Francis writes: > From: Alistair Francis > > When realising the SoC use error_fatal instead of error_abort as the > process can fail and report useful information to the user. > > Currently a user can see this: > >$ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -disp

[PATCH 2/2] target/riscv: Implement the stval/mtval illegal instruction

From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h|

[PATCH 1/2] target/riscv: Set the opcode in DisasContext

From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..24251bc8cc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -586

[PATCH 0/2] RISC-V: Populate mtval and stval

From: Alistair Francis Populate mtval and stval when taking an illegal instruction exception. The RISC-V spec states that "The stval register can optionally also be used to return the faulting instruction bits on an illegal instruction exception...". In this case we are always writing the value

Re: [PATCH v7 2/7] net/vmnet: add vmnet backends to qapi/net

Vladislav Yaroshchuk writes: > Create separate netdevs for each vmnet operating mode: > - vmnet-host > - vmnet-shared > - vmnet-bridged > > Signed-off-by: Vladislav Yaroshchuk > --- [...] > diff --git a/qapi/net.json b/qapi/net.json > index 7fab2e7cd8..8ed7bf0c04 100644 > --- a/qapi/net.json >

[PATCH] COLO: Move some trace code behind qemu_mutex_unlock_iothread()

Signed-off-by: Lei Rao --- migration/colo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/migration/colo.c b/migration/colo.c index 2415325262..3ccacb29c8 100644 --- a/migration/colo.c +++ b/migration/colo.c @@ -683,8 +683,8 @@ static void colo_incoming_process_checkp

Re: [PATCH 1/7] hw/intc: sifive_plic: Add a reset function

On Wed, Dec 8, 2021 at 10:00 PM Philippe Mathieu-Daudé wrote: > > Hi Alistair, > > On 12/8/21 07:42, Alistair Francis wrote: > > From: Alistair Francis > > > > Signed-off-by: Alistair Francis > > --- > > hw/intc/sifive_plic.c | 12 > > 1 file changed, 12 insertions(+) > > > > diff

Re: [PATCH v6 09/18] target/riscv: accessors to registers upper part and 128-bit load/store

On Mon, Nov 29, 2021 at 12:03 AM Frédéric Pétrot wrote: > > Get function to retrieve the 64 top bits of a register, stored in the gprh > field of the cpu state. Set function that writes the 128-bit value at once. > The access to the gprh field can not be protected at compile time to make > sure it

[PATCH v2 2/4] intel_iommu: Support IR-only mode without DMA translation

From: David Woodhouse By setting none of the SAGAW bits we can indicate to a guest that DMA translation isn't supported. Tested by booting Windows 10, as well as Linux guests with the fix at https://git.kernel.org/torvalds/c/c40c10 Signed-off-by: David Woodhouse Acked-by: Claudio Fontana -

[PATCH v2 1/4] target/i386: Fix sanity check on max APIC ID / X2APIC enablement

The check on x86ms->apic_id_limit in pc_machine_done() had two problems. Firstly, we need KVM to support the X2APIC API in order to allow IRQ delivery to APICs >= 255. So we need to call/check kvm_enable_x2apic(), which was done elsewhere in *some* cases but not all. Secondly, microvm needs the s

[PATCH v2 4/4] intel_iommu: Fix irqchip / X2APIC configuration checks

We don't need to check kvm_enable_x2apic(). It's perfectly OK to support interrupt remapping even if we can't address CPUs above 254. Kind of pointless, but still functional. The check on kvm_enable_x2apic() needs to happen *anyway* in order to allow CPUs above 254 even without an IOMMU, so allow

[PATCH v2 3/4] intel_iommu: Only allow interrupt remapping to be enabled if it's supported

From: David Woodhouse We should probably check if we were meant to be exposing IR, before letting the guest turn the IRE bit on. Signed-off-by: David Woodhouse Reviewed-by: Peter Xu Acked-by: Jason Wang --- hw/i386/intel_iommu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff

Re: Redesign of QEMU startup & initial configuration

On Thu, Dec 09, 2021 at 09:01:24PM +0100, Mark Burton wrote: > I’ll take the liberty to cut one part (I agree with much of what you say > elsewhere) > > > On 9 Dec 2021, at 20:11, Daniel P. Berrangé wrote: > > > > As illustrated earlier, I'd really like us to consider being a bit > > more adven

Re: [PATCH 1/1] uas: add stream number sanity checks.

On Wed, Aug 18, 2021 at 02:05:05PM +0200, Gerd Hoffmann wrote: > The device uses the guest-supplied stream number unchecked, which can > lead to guest-triggered out-of-band access to the UASDevice->data3 and > UASDevice->status3 fields. Add the missing checks. > > Fixes: CVE-2021-3713 > Signed-of

Re: Redesign of QEMU startup & initial configuration

I’ll take the liberty to cut one part (I agree with much of what you say elsewhere) > On 9 Dec 2021, at 20:11, Daniel P. Berrangé wrote: > > As illustrated earlier, I'd really like us to consider being a bit > more adventurous on the CLI side. I'm convinced that a CLI for > directly configurabl

Re: [PATCH v2] target/i386: Use assert() to sanity-check b1 in SSE decode

Gave up pinging for i386 maintainers; will take this via target-arm.next. thanks -- PMM On Mon, 15 Nov 2021 at 14:38, Peter Maydell wrote: > > Ping^4. Who is collecting target/i386 patches these days ? > > -- PMM > > On Mon, 1 Nov 2021 at 16:18, Peter Maydell wrote: > > > > Ping^3, now 2 month

Re: [PATCH v2 for-7.0] scripts: Explain the difference between linux-headers and standard-headers

On 09/12/2021 20.45, Peter Maydell wrote: If you don't know it, it's hard to figure out the difference between the linux-headers folder and the include/standard-headers folder. So let's add a short explanation to clarify the difference. Suggested-by: Thomas Huth Signed-off-by: Peter Maydell --

[PATCH v2 for-7.0] scripts: Explain the difference between linux-headers and standard-headers

If you don't know it, it's hard to figure out the difference between the linux-headers folder and the include/standard-headers folder. So let's add a short explanation to clarify the difference. Suggested-by: Thomas Huth Signed-off-by: Peter Maydell --- v1 of this was from Thomas; I suggested so

Re: [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG

Fabiano Rosas writes: > Cédric Le Goater writes: > >> Richard, >> >> On 12/9/21 16:05, Fabiano Rosas wrote: >>> Cédric Le Goater writes: >>> On 12/9/21 00:06, Fabiano Rosas wrote: > We cannot have TCG code in powerpc_excp because the function is called > from kvm-only code via ppc

Re: Redesign of QEMU startup & initial configuration

On Thu, Dec 02, 2021 at 07:57:38AM +0100, Markus Armbruster wrote: > = Motivation = > > QEMU startup and initial configuration were designed many years ago for > a much, much simpler QEMU. They have since changed beyond recognition > to adapt to new needs. There was no real redesign. Adaption t

Re: [PATCH] audio: Add sndio backend

Hi Brad, I tested the sndio backend on my Linux system and I found a bug in the sndio backend. The problem is that the function audio_run() can call the function sndio_enable_out() to disable audio playback. In the sndio_poll_event() function, audio_run() is called, which removes the poll ha

Re: [PATCH] scripts: Explain the difference between linux-headers and standard-headers

On 09/12/2021 18.44, Peter Maydell wrote: On Thu, 9 Dec 2021 at 17:34, Thomas Huth wrote: If you don't know it, it's hard to figure out the difference between the linux-headers folder and the include/standard-headers folder. So let's add a short explanation to clarify the difference. Signed-o

[PATCH v10 07/10] ACPI ERST: create ACPI ERST table for pc/x86 machines

This change exposes ACPI ERST support for x86 guests. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha --- hw/i386/acpi-build.c | 15 +++ hw/i386/acpi-microvm.c | 15 +++ include/hw/acpi/erst.h | 5 + 3 files changed, 35 insertions(+) diff --git a/hw/i386/acpi

[PATCH v10 10/10] ACPI ERST: step 6 of bios-tables-test.c

Following the guidelines in tests/qtest/bios-tables-test.c, this is step 6. Below is the disassembly of tests/data/acpi/pc/ERST.acpierst. /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180508 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * D

[PATCH v10 06/10] ACPI ERST: build the ACPI ERST table

This builds the ACPI ERST table to inform OSPM how to communicate with the acpi-erst device. Signed-off-by: Eric DeVolder --- hw/acpi/erst.c | 241 + 1 file changed, 241 insertions(+) diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c index 81f5

[PATCH v10 02/10] ACPI ERST: specification for ERST support

Information on the implementation of the ACPI ERST support. Signed-off-by: Eric DeVolder Acked-by: Ani Sinha --- docs/specs/acpi_erst.rst | 200 +++ 1 file changed, 200 insertions(+) create mode 100644 docs/specs/acpi_erst.rst diff --git a/docs/spec

[PATCH v10 09/10] ACPI ERST: bios-tables-test testcase

This change implements the test suite checks for the ERST table. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha --- tests/qtest/bios-tables-test.c | 56 ++ 1 file changed, 56 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bi

[PATCH v10 04/10] ACPI ERST: header file for ERST

This change introduces the public defintions for ACPI ERST. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha --- include/hw/acpi/erst.h | 19 +++ 1 file changed, 19 insertions(+) create mode 100644 include/hw/acpi/erst.h diff --git a/include/hw/acpi/erst.h b/include/hw/acpi

[PATCH v10 08/10] ACPI ERST: qtest for ERST

This change provides a qtest that locates and then does a simple interrogation of the ERST feature within the guest. Signed-off-by: Eric DeVolder --- tests/qtest/erst-test.c | 167 tests/qtest/meson.build | 2 + 2 files changed, 169 insertions(+

[PATCH v10 03/10] ACPI ERST: PCI device_id for ERST

This change reserves the PCI device_id for the new ACPI ERST device. Signed-off-by: Eric DeVolder Acked-by: Igor Mammedov Acked-by: Ani Sinha --- include/hw/pci/pci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e7cdf2d..d3734b9 100644 -

[PATCH v10 05/10] ACPI ERST: support for ACPI ERST feature

This implements a PCI device for ACPI ERST. This implements the non-NVRAM "mode" of operation for ERST as it is supported by Linux and Windows. Signed-off-by: Eric DeVolder --- hw/acpi/Kconfig | 6 + hw/acpi/erst.c | 846 +++ hw/acpi/m

[PATCH v10 01/10] ACPI ERST: bios-tables-test.c steps 1 and 2

Following the guidelines in tests/qtest/bios-tables-test.c, this change adds empty placeholder files per step 1 for the new ERST table, and excludes resulting changed files in bios-tables-test-allowed-diff.h per step 2. Signed-off-by: Eric DeVolder Acked-by: Igor Mammedov --- tests/data/acpi/mi

[PATCH v10 00/10] acpi: Error Record Serialization Table, ERST, support for QEMU

This patchset introduces support for the ACPI Error Record Serialization Table, ERST. For background and implementation information, please see docs/specs/acpi_erst.rst, which is patch 2/10. Suggested-by: Konrad Wilk Signed-off-by: Eric DeVolder --- v10: 9dec2021 - Addressed additional feedba

Re: [PATCH v9 05/10] ACPI ERST: support for ACPI ERST feature

On 12/9/21 00:31, Ani Sinha wrote: On Wed, Dec 8, 2021 at 10:08 PM Eric DeVolder wrote: On 12/6/21 02:14, Ani Sinha wrote: On Fri, Dec 3, 2021 at 12:39 AM Eric DeVolder wrote: This implements a PCI device for ACPI ERST. This implements the non-NVRAM "mode" of operation for ERST as it i

Re: [PATCH v9 10/10] ACPI ERST: step 6 of bios-tables-test.c

Ani, thanks! eric On 12/9/21 03:29, Ani Sinha wrote: On Fri, Dec 3, 2021 at 12:39 AM Eric DeVolder wrote: Following the guidelines in tests/qtest/bios-tables-test.c, this is step 6. Below is the disassembly of tests/data/acpi/pc/ERST.acpierst. [...] Note that the contents of tests/data/q3

Re: [RFC PATCH v2 0/5] virtio: early detect 'modern' virtio

On Thu, Dec 09, 2021 at 02:29:25PM +0100, Halil Pasic wrote: > On Wed, 8 Dec 2021 13:56:19 -0500 > "Michael S. Tsirkin" wrote: > > > On Fri, Nov 12, 2021 at 03:57:44PM +0100, Halil Pasic wrote: > > > This is an early RFC for a transport specific early detecton of > > > modern virtio, which is mos

Re: [PATCH v9 05/10] ACPI ERST: support for ACPI ERST feature

Ani, inline responses below. eric On 12/9/21 00:29, Ani Sinha wrote: On Fri, Dec 3, 2021 at 12:39 AM Eric DeVolder wrote: This implements a PCI device for ACPI ERST. This implements the non-NVRAM "mode" of operation for ERST as it is supported by Linux and Windows. Few more comments on this

Re: [PATCH] scripts: Explain the difference between linux-headers and standard-headers

On Thu, 9 Dec 2021 at 17:34, Thomas Huth wrote: > > If you don't know it, it's hard to figure out the difference between > the linux-headers folder and the include/standard-headers folder. > So let's add a short explanation to clarify the difference. > > Signed-off-by: Thomas Huth > --- > script

[PATCH v2] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp"

This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2. It breaks the --disable-tcg build: ../target/ppc/excp_helper.c:463:29: error: implicit declaration of function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration] We should not have TCG code in powerpc_excp because some kvm-only

[PATCH] scripts: Explain the difference between linux-headers and standard-headers

If you don't know it, it's hard to figure out the difference between the linux-headers folder and the include/standard-headers folder. So let's add a short explanation to clarify the difference. Signed-off-by: Thomas Huth --- scripts/update-linux-headers.sh | 7 +++ 1 file changed, 7 inserti

Re: [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG

Cédric Le Goater writes: > Richard, > > On 12/9/21 16:05, Fabiano Rosas wrote: >> Cédric Le Goater writes: >> >>> On 12/9/21 00:06, Fabiano Rosas wrote: We cannot have TCG code in powerpc_excp because the function is called from kvm-only code via ppc_cpu_do_interrupt: ../

Re: [PULL 0/1] Block patches

On 12/9/21 8:34 AM, Stefan Hajnoczi wrote: I'm not running the release cycle this time around, but: it's already rc4, pull requests by this point need a clear justification in the cover letter for why they're really release critical. It's late, this isn't a show-stopper (block/nvme.c is not wid

Re: [RFC] block-backend: prevent dangling BDS pointer in blk_drain()

09.12.2021 19:32, Stefan Hajnoczi wrote: On Thu, Dec 09, 2021 at 04:45:13PM +0100, Hanna Reitz wrote: On 09.12.21 15:23, Stefan Hajnoczi wrote: The BlockBackend root child can change during bdrv_drained_begin() when aio_poll() is invoked. In fact the BlockDriverState can reach refcnt 0 and blk_

Re: [PULL 0/1] Block patches

On Thu, Dec 09, 2021 at 03:46:29PM +, Peter Maydell wrote: > On Thu, 9 Dec 2021 at 15:21, Stefan Hajnoczi wrote: > > > > The following changes since commit a3607def89f9cd68c1b994e1030527df33aa91d0: > > > > Update version for v6.2.0-rc4 release (2021-12-07 17:51:38 -0800) > > > > are availabl

Re: [PATCH] mirror: Avoid assertion failed in mirror_run

08.12.2021 12:52, wang.y...@zte.com.cn wrote: [CC-ing qemu-block, Vladimir, Kevin, and John – when sending patches, please look into the MAINTAINERS file or use the scripts/get_maintainer.pl script to find out who to CC on them. It’s very to overlook patches on qemu-devel :/] On 07.12.21 11:56,

Re: [RFC] block-backend: prevent dangling BDS pointer in blk_drain()

On Thu, Dec 09, 2021 at 04:45:13PM +0100, Hanna Reitz wrote: > On 09.12.21 15:23, Stefan Hajnoczi wrote: > > The BlockBackend root child can change during bdrv_drained_begin() when > > aio_poll() is invoked. In fact the BlockDriverState can reach refcnt 0 > > and blk_drain() is left with a dangling

Re: QEMU 6.2.0 and rhbz#1999878

Thanks all, I saw the patch has been merged and is part of rc4. I'm removing it from the fedora package. On Fri, Dec 3, 2021 at 9:09 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 12/3/21 2:00 PM, Richard Henderson wrote: > >> Oh I see, it was indeed replaced by Richard Henderso

Re: [RFC] block-backend: prevent dangling BDS pointer in blk_drain()

09.12.2021 18:45, Hanna Reitz wrote: On 09.12.21 15:23, Stefan Hajnoczi wrote: The BlockBackend root child can change during bdrv_drained_begin() when aio_poll() is invoked. In fact the BlockDriverState can reach refcnt 0 and blk_drain() is left with a dangling BDS pointer. One example is scsi_

Re: [PULL 04/13] target/rx: TCG helpers

On Tue, 17 Mar 2020 at 16:43, Philippe Mathieu-Daudé wrote: > > From: Yoshinori Sato > > Reviewed-by: Richard Henderson > Tested-by: Philippe Mathieu-Daudé > Signed-off-by: Yoshinori Sato > Signed-off-by: Richard Henderson > [PMD: Removed tlb_fill, extracted from patch of Yoshinori Sato > 'C

Re: [RFC] vhost-vdpa-net: add vhost-vdpa-net host device support

On Thu, Dec 09, 2021 at 09:16:58AM +, Stefan Hajnoczi wrote: On Wed, Dec 08, 2021 at 01:20:10PM +0800, Longpeng(Mike) wrote: From: Longpeng Hi guys, This patch introduces vhost-vdpa-net device, which is inspired by vhost-user-blk and the proposal of vhost-vdpa-blk device [1]. I've tested

Re: RFC: x86 memory map, where to put CXL ranges?

On Thu, 09 Dec 2021 14:19:59 + Alex Bennée wrote: > Jonathan Cameron writes: > > > Hi All, > > > > For CXL emulation we require a couple of types of memory range that > > are then provided to the OS via the CEDT ACPI table. > > > > 1) CXL Host Bridge Structures point to CXL Host Bridge Comp

Re: [PULL 0/1] Block patches

On Thu, 9 Dec 2021 at 15:21, Stefan Hajnoczi wrote: > > The following changes since commit a3607def89f9cd68c1b994e1030527df33aa91d0: > > Update version for v6.2.0-rc4 release (2021-12-07 17:51:38 -0800) > > are available in the Git repository at: > > https://gitlab.com/stefanha/qemu.git tags/b

Re: [RFC] block-backend: prevent dangling BDS pointer in blk_drain()

On 09.12.21 15:23, Stefan Hajnoczi wrote: The BlockBackend root child can change during bdrv_drained_begin() when aio_poll() is invoked. In fact the BlockDriverState can reach refcnt 0 and blk_drain() is left with a dangling BDS pointer. One example is scsi_device_purge_requests(), which calls b

Re: [PATCH v2] Move the libssh setup from configure to meson.build

On Thu, Dec 09, 2021 at 04:08:24PM +0100, Thomas Huth wrote: > On 09/12/2021 15.55, Richard W.M. Jones wrote: > >On Thu, Dec 09, 2021 at 03:48:01PM +0100, Thomas Huth wrote: > >>It's easier to do this in meson.build now. > >> > >>Signed-off-by: Thomas Huth > >>--- > >> v2: Added the missing "conf

[PATCH] vvfat: Fix vvfat_write() for writes before the root directory

The calculation in sector2cluster() is done relative to the offset of the root directory. Any writes to blocks before the start of the root directory (in particular, writes to the FAT) result in negative values, which are not handled correctly in vvfat_write(). This changes sector2cluster() to ret

Re: [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG

Philippe Mathieu-Daudé writes: > On 12/9/21 00:06, Fabiano Rosas wrote: >> We cannot have TCG code in powerpc_excp because the function is called >> from kvm-only code via ppc_cpu_do_interrupt: >> >> ../target/ppc/excp_helper.c:463:29: error: implicit declaration of >> function ‘cpu_ldl_code’

[PATCH] vvfat: Fix size of temporary qcow file

The size of the qcow size was calculated so that only the FAT partition would fit on it, but not the whole disk. However, offsets relative to the whole disk are used to access it, so increase its size to be large enough for that. Signed-off-by: Kevin Wolf --- block/vvfat.c | 7 +++ 1 file ch

[PULL 0/1] Block patches

The following changes since commit a3607def89f9cd68c1b994e1030527df33aa91d0: Update version for v6.2.0-rc4 release (2021-12-07 17:51:38 -0800) are available in the Git repository at: https://gitlab.com/stefanha/qemu.git tags/block-pull-request for you to fetch changes up to cf4fbc3030c974ff

[PULL 1/1] block/nvme: fix infinite loop in nvme_free_req_queue_cb()

When the request free list is exhausted the coroutine waits on q->free_req_queue for the next free request. Whenever a request is completed a BH is scheduled to invoke nvme_free_req_queue_cb() and wake up waiting coroutines. 1. nvme_get_free_req() waits for a free request: while (q->free_req_

Re: [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG

Richard, On 12/9/21 16:05, Fabiano Rosas wrote: Cédric Le Goater writes: On 12/9/21 00:06, Fabiano Rosas wrote: We cannot have TCG code in powerpc_excp because the function is called from kvm-only code via ppc_cpu_do_interrupt: ../target/ppc/excp_helper.c:463:29: error: implicit declarat

Re: [PATCH v2] Move the libssh setup from configure to meson.build

On 09/12/2021 15.55, Richard W.M. Jones wrote: On Thu, Dec 09, 2021 at 03:48:01PM +0100, Thomas Huth wrote: It's easier to do this in meson.build now. Signed-off-by: Thomas Huth --- v2: Added the missing "config_host_data.set('CONFIG_LIBSSH', libssh.found())" configure

Re: [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG

Cédric Le Goater writes: > On 12/9/21 00:06, Fabiano Rosas wrote: >> We cannot have TCG code in powerpc_excp because the function is called >> from kvm-only code via ppc_cpu_do_interrupt: >> >> ../target/ppc/excp_helper.c:463:29: error: implicit declaration of >> function ‘cpu_ldl_code’ [-We

Re: [PATCH v4 0/5] s390x: CPU Topology

Hi, This series is updated by a v5 series with documentation and numa extensions. Some changes have been made in some of the patches contained in this series too. Regards, Pierre On 11/17/21 17:48, Pierre Morel wrote: Hi, This series is a first part of the implementation of CPU topology fo

[PATCH 3/8] vhost-user-video: boiler plate code for vhost-user-video device

Signed-off-by: Peter Griffin --- hw/display/Kconfig | 5 + hw/display/meson.build | 3 + hw/display/vhost-user-video.c| 386 +++ include/hw/virtio/vhost-user-video.h | 41 +++ 4 files changed, 435 insertions(+) create mode 1006

[PATCH 6/8] virtio_video: Add Fast Walsh-Hadamard Transform format

Linux vicodec (Virtual Codec) test driver in Linux implements FWHT. FWHT was designed to be fast and simple and to have characteristics of other video codecs and therefore face similar issues [1]. https://en.wikipedia.org/wiki/Fast_Walsh%E2%80%93Hadamard_transform Signed-off-by: Peter Griffin --

[PATCH 8/8] tools/vhost-user-video: Add initial vhost-user-video vmm

This vmm translates from virtio-video v3 protocol and writes to a v4l2 mem2mem stateful decoder/encoder device [1]. v3 was chosen as that is what the virtio-video Linux frontend driver implements. This allows for testing with the v4l2 vicodec test codec [2] module in the Linux kernel, and is inten

[PATCH 7/8] hw/display: add vhost-user-video-pci

Add boiler plate code for vhost-user-video-pci. Example -device vhost-user-video-pci,chardev=video,id=video -chardev socket,path=video.sock,id=video Signed-off-by: Peter Griffin --- hw/display/vhost-user-video-pci.c | 82 +++ 1 file changed, 82 insertions(+) create

[PATCH 4/8] vhost-user-video: add meson subdir build logic

Signed-off-by: Peter Griffin --- tools/meson.build | 9 + 1 file changed, 9 insertions(+) diff --git a/tools/meson.build b/tools/meson.build index 3e5a0abfa2..3314b5efc5 100644 --- a/tools/meson.build +++ b/tools/meson.build @@ -24,3 +24,12 @@ endif if have_virtiofsd subdir('virtiofs

[PATCH 5/8] standard-headers: Add virtio_video.h

Signed-off-by: Peter Griffin --- include/standard-headers/linux/virtio_video.h | 483 ++ 1 file changed, 483 insertions(+) create mode 100644 include/standard-headers/linux/virtio_video.h diff --git a/include/standard-headers/linux/virtio_video.h b/include/standard-headers/linu

[PATCH 0/8] virtio: Add vhost-user based Video decode

This series adds support for virtio-video decoder devices in Qemu and also provides a vhost-user-video vmm implementation. The vhost-user-video vmm currently parses virtio-vido v3 protocol (as that is what the Linux frontend driver implements). It then converts that to a v4l2 mem2mem stateful deco

[PATCH 1/8] vhost-user-video: Add a README.md with cheat sheet of commands

Signed-off-by: Peter Griffin --- tools/vhost-user-video/README.md | 98 1 file changed, 98 insertions(+) create mode 100644 tools/vhost-user-video/README.md diff --git a/tools/vhost-user-video/README.md b/tools/vhost-user-video/README.md new file mode 100644 ind

[PATCH 2/8] MAINTAINERS: Add virtio-video section

Add myself as maintainer of the virtio-video files added in this series. Signed-off-by: Peter Griffin --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7543eb4d59..43c53aded8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2012,6 +2012,14

Re: [PATCH v2] Move the libssh setup from configure to meson.build

On Thu, Dec 09, 2021 at 03:48:01PM +0100, Thomas Huth wrote: > It's easier to do this in meson.build now. > > Signed-off-by: Thomas Huth > --- > v2: Added the missing "config_host_data.set('CONFIG_LIBSSH', libssh.found())" > > configure | 27 --- > m

[PATCH v2] Move the libssh setup from configure to meson.build

It's easier to do this in meson.build now. Signed-off-by: Thomas Huth --- v2: Added the missing "config_host_data.set('CONFIG_LIBSSH', libssh.found())" configure | 27 --- meson.build | 13 + meson_options.txt

Re: LTP test perf_event_open02.c: possible rounding issue on aarch64 KVM

On 09/12/2021 12:20, Petr Vorel wrote: > Hi, > > I have problem with LTP test perf_event_open02.c [1] on QEMU using KVM on > openSUSE aarch64 kernel 5.15.5-1-default (not much different from stable > kernel > from kernel.org): > > # /opt/ltp/testcases/bin/perf_event_open02 > ... > perf_event_o

Re: [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG

On 12/9/21 00:06, Fabiano Rosas wrote: We cannot have TCG code in powerpc_excp because the function is called from kvm-only code via ppc_cpu_do_interrupt: ../target/ppc/excp_helper.c:463:29: error: implicit declaration of function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration] Fortu

Re: [PATCH 0/3] iotests: multiprocessing!!

On 03.12.21 13:22, Vladimir Sementsov-Ogievskiy wrote: Hi all! Finally, I can not stand it any longer. So, I'm happy to present multiprocessing support for iotests test runner. Thanks, looks great! Applied to my block-next branch: https://gitlab.com/hreitz/qemu/-/commits/block-next Hanna

Re: [RFC PATCH v2 32/44] tdx: add kvm_tdx_enabled() accessor for later use

On 7/23/2021 1:53 AM, Connor Kuehl wrote: On 7/7/21 7:55 PM, isaku.yamah...@gmail.com wrote: From: Isaku Yamahata Signed-off-by: Isaku Yamahata ---   include/sysemu/tdx.h  | 1 +   target/i386/kvm/kvm.c | 5 +   2 files changed, 6 insertions(+) diff --git a/include/sysemu/tdx.h b/include/s

Re: RFC: x86 memory map, where to put CXL ranges?

Jonathan Cameron writes: > Hi All, > > For CXL emulation we require a couple of types of memory range that > are then provided to the OS via the CEDT ACPI table. > > 1) CXL Host Bridge Structures point to CXL Host Bridge Component Registers. > Small regions for each CXL Host bridge that are map

[RFC] block-backend: prevent dangling BDS pointer in blk_drain()

The BlockBackend root child can change during bdrv_drained_begin() when aio_poll() is invoked. In fact the BlockDriverState can reach refcnt 0 and blk_drain() is left with a dangling BDS pointer. One example is scsi_device_purge_requests(), which calls blk_drain() to wait for in-flight requests to

[PATCH v5 11/12] s390x: topology: implementing numa for the s390x topology

S390x CPU Topology allows a non uniform repartition of the CPU inside the topology containers, sockets, books and drawers. We use numa to place the CPU inside the right topology container and report the non uniform topology to the guest. Note that s390x needs CPU0 to belong to the topology and co

Re: [PATCH] virtio-blk: Fix clean up of host notifiers for single MR transaction.

On Thu, Dec 2, 2021 at 10:34 PM Mark Mielke wrote: > > Sorry... I missed copy maintainers and qemu-stable. This should be > considered a regression. > > -- Forwarded message - > From: Mark Mielke > Date: Thu, Dec 2, 2021 at 11:26 AM > Subject: [PATCH] virtio-blk: Fix clean up of h

[PATCH v5 12/12] s390: Topology: documentation

The use of the S390x CPU topology is explain in a new documentation file. Signed-off-by: Pierre Morel --- docs/system/s390x/numa-cpu-topology.rst | 273 1 file changed, 273 insertions(+) create mode 100644 docs/system/s390x/numa-cpu-topology.rst diff --git a/docs/syste

[PATCH v5 09/12] s390: topology: Adding drawers to CPU topology

S390 CPU topology may have up to 5 topology containers. The first container above the cores is level 2, the sockets, and the level 3, containing sockets are the books. We introduce here the drawers, drawers is the level containing books. Let's add drawers, level4, containers to the CPU topology.

[PATCH v5 06/12] s390x: kvm: topology: interception of PTF instruction

When the host supports the CPU topology facility, the PTF instruction with function code 2 is interpreted by the SIE, provided that the userland hypervizor activates the interpretation by using the KVM_CAP_S390_CPU_TOPOLOGY KVM extension. The PTF instructions with function code 0 and 1 are interce

[PATCH v5 07/12] s390: topology: Adding books to CPU topology

S390 CPU topology may have up to 5 topology containers. The first container above the cores is level 2, the sockets. We introduce here the books, book is the level containing sockets. Let's add books, level3, containers to the CPU topology. Signed-off-by: Pierre Morel --- hw/core/machine-smp.c

[PATCH v5 10/12] s390: topology: Adding drawers to STSI

Let's add STSI support for the container level 4, drawers, and provide the information back to the guest. Signed-off-by: Pierre Morel --- hw/s390x/cpu-topology.c | 137 +--- include/hw/s390x/cpu-topology.h | 19 - include/hw/s390x/sclp.h | 2 +-

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