RE: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror and filter-redirector

> -Original Message- > From: Jason Wang > Sent: Wednesday, October 27, 2021 2:45 PM > To: Zhang, Chen > Cc: qemu-dev ; Markus Armbruster > ; Li Zhijian > Subject: Re: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror > and filter-redirector > > On Wed, Oct 27, 2021 at 2:40

Re: [PATCH v4 3/3] multifd: Implement zerocopy write in multifd migration (multifd-zerocopy)

On Wed, Oct 13, 2021 at 3:26 AM Peter Xu wrote: > > On Sat, Oct 09, 2021 at 04:56:13AM -0300, Leonardo Bras wrote: > > @@ -105,7 +105,13 @@ static int nocomp_send_prepare(MultiFDSendParams *p, > > uint32_t used, > > */ > > static int nocomp_send_write(MultiFDSendParams *p, uint32_t used, Error

Re: [PATCH v4 3/3] multifd: Implement zerocopy write in multifd migration (multifd-zerocopy)

On Wed, Oct 13, 2021 at 3:24 AM Peter Xu wrote: > > On Sat, Oct 09, 2021 at 04:56:13AM -0300, Leonardo Bras wrote: > > diff --git a/qapi/migration.json b/qapi/migration.json > > index 88f07baedd..c4890cbb54 100644 > > --- a/qapi/migration.json > > +++ b/qapi/migration.json > > @@ -724,6 +724,11 @@

Re: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror and filter-redirector

On Wed, Oct 27, 2021 at 2:40 PM Zhang, Chen wrote: > > > > > -Original Message- > > From: Jason Wang > > Sent: Wednesday, October 27, 2021 2:24 PM > > To: Zhang, Chen > > Cc: qemu-dev ; Markus Armbruster > > ; Li Zhijian > > Subject: Re: [PATCH V4 1/3] net/filter: Remove vnet_hdr from f

RE: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror and filter-redirector

> -Original Message- > From: Jason Wang > Sent: Wednesday, October 27, 2021 2:24 PM > To: Zhang, Chen > Cc: qemu-dev ; Markus Armbruster > ; Li Zhijian > Subject: Re: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror > and filter-redirector > > > 在 2021/10/27 下午2:19, Zha

Re: [PATCH v4 1/3] QIOChannel: Add io_writev_zerocopy & io_flush_zerocopy callbacks

On Wed, Oct 27, 2021 at 3:15 AM Peter Xu wrote: > > On Wed, Oct 27, 2021 at 03:07:13AM -0300, Leonardo Bras Soares Passos wrote: > > > > > > > >if (flags & ZEROCOPY) { > > > >assert(fds == NULL && nfds == 0); > > > > Quick question: Why is this assert needed? > > Not re

Re: [PATCH v4 2/3] QIOChannelSocket: Implement io_writev_zerocopy & io_flush_zerocopy for CONFIG_LINUX

On Wed, Oct 13, 2021 at 3:18 AM Peter Xu wrote: > > On Sat, Oct 09, 2021 at 04:56:12AM -0300, Leonardo Bras wrote: > > @@ -154,6 +161,17 @@ int qio_channel_socket_connect_sync(QIOChannelSocket > > *ioc, > > return -1; > > } > > > > +#ifdef CONFIG_LINUX > > +ret = qemu_setsockopt

Re: [PATCH v12 0/6] support dirtyrate at the granualrity of vcpu

Hi. I have no objection for the implement code itself. But we should know or let the user know the performance penalty and conflicted with migration compared to the hash method, especially for the performance of vm with hugepages. On 2021/10/15 10:07, Hyman Huang wrote: > > > 在 2021/10/15 9:32

Re: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror and filter-redirector

在 2021/10/27 下午2:19, Zhang, Chen 写道: mirror,id=id,netdev=netdevid,outdev=chardevid,queue=all|rx|tx[,vnet_hdr _support][,position=head|tail|id=][,insert=behind|before]`` +``-object + filter-mirror,id=id,netdev=netdevid,outdev=chardevid,queue=all|rx|tx + [,position=head|tail|id=][,insert=beh

RE: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror and filter-redirector

> -Original Message- > From: Jason Wang > Sent: Wednesday, October 27, 2021 12:46 PM > To: Zhang, Chen > Cc: qemu-dev ; Markus Armbruster > ; Li Zhijian > Subject: Re: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror > and filter-redirector > > > 在 2021/10/27 上午2:17, Zh

Re: [PATCH V6 00/27] Live Update

Hi, Steve. Any updates for this series? On 2021/9/1 5:15, Steven Sistare wrote: > On 8/24/2021 5:36 AM, Zheng Chuan wrote: >> Hi, Steve. >> >> I think I have found the problem, it is because the rom_reset() during the >> cpr_exec will write dtb into the mach-virt.ram which cause the memory >> co

Re: [PATCH v4 1/3] QIOChannel: Add io_writev_zerocopy & io_flush_zerocopy callbacks

On Wed, Oct 27, 2021 at 03:07:13AM -0300, Leonardo Bras Soares Passos wrote: > > > > > >if (flags & ZEROCOPY) { > > >assert(fds == NULL && nfds == 0); > > Quick question: Why is this assert needed? Not required I think; just want to make sure no one passes in the fds w

Re: [PATCH v4 1/3] QIOChannel: Add io_writev_zerocopy & io_flush_zerocopy callbacks

Hello Peter, sorry for the delay. On Wed, Oct 13, 2021 at 3:33 AM Peter Xu wrote: > > On Wed, Oct 13, 2021 at 02:07:13PM +0800, Peter Xu wrote: > > On Sat, Oct 09, 2021 at 04:56:11AM -0300, Leonardo Bras wrote: > > > -int qio_channel_writev_full_all(QIOChannel *ioc, > > > -

Re: [PATCH 1/1] gitlab-ci: Only push docker images to registry from /master branch

On 26/10/2021 16.55, Philippe Mathieu-Daudé wrote: Users expect images pulled from registry.gitlab.com/qemu-project/qemu/ to be stable. QEMU repository workflow pushes merge candidates to the /staging branch, and on success the same commit is pushed as /master. If /staging fails, we do not want t

Re: [PATCH] qapi: Improve input_type_enum()'s error message

John Snow writes: > This likely fixes https://gitlab.com/qemu-project/qemu/-/issues/608 and you > could include that in your commit message if it isn't too late. It's not. Have you verified it fixes the bug, or is it just an educated guess?

Re: [PATCH 9/9] qapi: Extend -compat to set policy for unstable interfaces

"Dr. David Alan Gilbert" writes: > * Markus Armbruster (arm...@redhat.com) wrote: >> New option parameters unstable-input and unstable-output set policy >> for unstable interfaces just like deprecated-input and >> deprecated-output set policy for deprecated interfaces (see commit >> 6dd75472d5 "q

Re: [PATCH 5/9] qapi: Generalize struct member policy checking

Philippe Mathieu-Daudé writes: > On 10/25/21 07:25, Markus Armbruster wrote: >> The generated visitor functions call visit_deprecated_accept() and >> visit_deprecated() when visiting a struct member with special feature >> flag 'deprecated'. This makes the feature flag visible to the actual >> v

Re: [PATCH 2/9] qapi: Mark unstable QMP parts with feature 'unstable'

John Snow writes: > On Tue, Oct 26, 2021 at 3:56 AM Markus Armbruster wrote: > >> John Snow writes: >> >> > On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster >> wrote: >> > >> >> Add special feature 'unstable' everywhere the name starts with 'x-', >> >> except for InputBarrierProperties member

Re: [PATCH 1/9] qapi: New special feature flag "unstable"

Daniel P. Berrangé writes: > On Tue, Oct 26, 2021 at 05:15:10PM +0200, Markus Armbruster wrote: >> Daniel P. Berrangé writes: >> >> > On Tue, Oct 26, 2021 at 11:37:19AM +0200, Markus Armbruster wrote: [...] >> >> Management applications are better off with a feature flag than with a >> >> nam

[PATCH v2] hw/arm/virt: Expose empty NUMA nodes through ACPI

The empty NUMA nodes, where no memory resides, aren't exposed through ACPI SRAT table. It's not user preferred behaviour because the corresponding memory node devices are missed from the guest kernel as the following example shows. It means the guest kernel doesn't have the node information as user

[PATCH-for-6.0.1 1/2] gitlab: only let pages be published from default branch

From: Daniel P. Berrangé GitLab will happily publish pages generated by the latest CI pipeline from any branch: https://docs.gitlab.com/ee/user/project/pages/introduction.html "Remember that GitLab Pages are by default branch/tag agnostic and their deployment relies solely on what you spec

[PATCH-for-6.0.1 0/2] gitlab-ci: Only push docker images to mainstream registry from /master

Hi Michael, 2 more patches to avoid gitlab-ci mayhem when you push the stable tags. See this cover for more info: https://www.mail-archive.com/qemu-devel@nongnu.org/msg846861.html Based-on: <20211019140944.152419-1-michael.r...@amd.com> "Patch Round-up for stable 6.0.1, freeze on 2021-10-26" Dan

[PATCH-for-6.0.1 2/2] gitlab-ci: Only push docker images to registry from /master branch

Users expect images pulled from registry.gitlab.com/qemu-project/qemu/ to be stable. QEMU repository workflow pushes merge candidates to the /staging branch, and on success the same commit is pushed as /master. If /staging fails, we do not want to push the built images to the registry. Therefore li

Re: [PATCH v4 5/5] block: Deprecate transaction type drive-backup

John Snow writes: > On Mon, Oct 25, 2021 at 12:24 AM Markus Armbruster > wrote: > >> Several moons ago, Vladimir posted >> >> Subject: [PATCH v2 3/3] qapi: deprecate drive-backup >> Date: Wed, 5 May 2021 16:58:03 +0300 >> Message-Id: <20210505135803.67896-4-vsement...@virtuozzo.com>

Re: [PATCH] hw/arm/virt: Expose empty NUMA nodes through ACPI

On 10/26/21 8:47 PM, Igor Mammedov wrote: On Tue, 26 Oct 2021 07:41:01 +0800 Gavin Shan wrote: The empty NUMA nodes, where no memory resides, aren't exposed through ACPI SRAT table. It's not user preferred behaviour because the corresponding memory node devices are missed from the guest kernel

Re: [PATCH] hw/arm/virt: Expose empty NUMA nodes through ACPI

On 10/26/21 5:25 PM, Andrew Jones wrote: On Tue, Oct 26, 2021 at 07:41:01AM +0800, Gavin Shan wrote: The empty NUMA nodes, where no memory resides, aren't exposed through ACPI SRAT table. It's not user preferred behaviour because the corresponding memory node devices are missed from the guest ke

Re: [PATCH 0/3] hw/input/lasips2: QOM'ify the Lasi PS/2

Cc'ing qemu-trivial@ (fully reviewed). On 9/20/21 08:40, Philippe Mathieu-Daudé wrote: > Slowly nuking non-QOM devices: Lasi PS/2's turn. > > Philippe Mathieu-Daudé (3): > hw/input/lasips2: Fix typos in function names > hw/input/lasips2: Move LASIPS2State declaration to > 'hw/input/lasips

[PATCH v2] hw: Add a 'Sensor devices' qdev category

Sensors models are listed in the 'Misc devices' category. Move them to their own category. Reviewed-by: Cédric Le Goater Reviewed-by: Hao Wu Signed-off-by: Philippe Mathieu-Daudé --- v2: Only include hw/sensor/, removed AER915 device from hw/arm/z2.c --- include/hw/qdev-core.h | 1 + hw/sensor

[PATCH v2 4/4] target/arm: Use tcg_constant_i64() in do_sat_addsub_64()

The immediate value used for comparison is constant and read-only. Move it to the constant pool. This frees a TCG temporary for unsigned saturation opcodes. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/translate-sve.c | 17 - 1 file changed

[PATCH v2 3/4] target/arm: Use the constant variant of store_cpu_field() when possible

When using a constant variable, we can replace the store_cpu_field() call by store_cpu_field_constant() which avoid using TCG temporaries. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/translate.c | 21 ++--- 1 file changed, 6 insertions(+),

[PATCH v2 1/4] target/arm: Use tcg_constant_i32() in op_smlad()

Avoid using a TCG temporary for a read-only constant. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d6af5b1b039..083a6d6e

[PATCH v2 2/4] target/arm: Introduce store_cpu_field_constant() helper

Similarly to the store_cpu_field() helper which takes a TCG temporary, store its value to the CPUState, introduce the store_cpu_field_constant() helper which store a constant to CPUState (without using any TCG temporary). Update the single store_cpu_offset() user in do_coproc_insn(). Signed-off-b

[PATCH v2 0/4] target/arm: Use tcg_constant_*

Missing review: patch #2 Introduce store_cpu_field_constant() helper to avoid using temporary when the value is constant (and read-only). Since v1: - Really use tcg_constant() in patch 2 (Richard) Philippe Mathieu-Daudé (4): target/arm: Use tcg_constant_i32() in op_smlad() target/arm: Introd

Re: [PATCH V4 1/3] net/filter: Remove vnet_hdr from filter-mirror and filter-redirector

在 2021/10/27 上午2:17, Zhang Chen 写道: Make the vnet header a necessary part of filter transfer protocol. So remove the module's vnet_hdr_support switch here. It make other modules(like another filter-redirector,colo-compare...) know how to parse net packet correctly. If local device is not the vi

Re: [PATCH] target/avr: Optimize various functions using extract opcode

Hi Richard, On 10/3/21 17:24, Richard Henderson wrote: > On 10/3/21 10:21 AM, Philippe Mathieu-Daudé wrote: >> When running the scripts/coccinelle/tcg_gen_extract.cocci >> Coccinelle semantic patch on target/avr/, we get: >> >>    [DBG] candidate at target/avr/translate.c:228 >>    [DBG] candidate

Re: [PATCH] e1000: fix tx re-entrancy problem

在 2021/10/22 上午12:10, Jon Maloy 写道: The fact that the MMIO handler is not re-entrant causes an infinite loop under certain conditions: Guest write to TDT -> Loopback -> RX (DMA to TDT) -> TX We now eliminate the effect of this problem locally in e1000, by adding a boolean in struct E1000Stat

[PATCH v2] .mailmap: Fix more contributor entries

These authors have some incorrect author email field. Acked-by: Pan Nengyuan Reviewed-by: Alex Chen Reviewed-by: Hyman Huang Reviewed-by: Haibin Zhang Signed-off-by: Philippe Mathieu-Daudé --- Patch fully reviewed/acked. --- .mailmap | 4 1 file changed, 4 insertions(+) diff --git a/.m

Re: [PATCH v2 1/3] file-posix: add `aio-max-batch` option

Stefano Garzarella writes: > Commit d7ddd0a161 ("linux-aio: limit the batch size using > `aio-max-batch` parameter") added a way to limit the batch size > of Linux AIO backend for the entire AIO context. > > The same AIO context can be shared by multiple devices, so > latency-sensitive devices ma

Re: [PATCH] MAINTAINERS: Split HPPA TCG vs HPPA machines/hardware

Cc'ing qemu-trivial@ (patch reviewed) On 10/4/21 10:38, Philippe Mathieu-Daudé wrote: > Hardware emulated models don't belong to the TCG MAINTAINERS > section. Move them to the 'HP-PARISC Machines' section. > > Signed-off-by: Philippe Mathieu-Daudé > --- > MAINTAINERS | 5 ++--- > 1 file change

[PATCH v2 4/4] MAINTAINERS: Agree to maintain nanoMIPS TCG frontend

As of this commit, the nanoMIPS toolchains haven't been merged in mainstream projects. However MediaTek provides a toolchain: https://github.com/MediaTek-Labs/nanomips-gnu-toolchain/releases/tag/nanoMIPS-2021.02-01 QEMU deprecation policy schedules code for removal. If we don't need / want to remo

[PATCH v2 1/4] MAINTAINERS: Add MIPS general architecture support entry

The architecture is covered in TCG (frontend and backend) and hardware models. Add a generic section matching the 'mips' word in patch subjects. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211004092515.3819836-2-f4...@amsat.org> --- MAINTAINERS | 7 ++- 1 f

[PATCH v2 3/4] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware

Hardware emulated models don't belong to the TCG MAINTAINERS section. Move them to a new 'Overall MIPS Machines' section in the 'MIPS Machines' group. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211004092515.3819836-4-f4...@amsat.org> --- MAINTAINERS | 10 +

[PATCH v2 2/4] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware

MIPS CPS and GIC models are unrelated to the TCG frontend. Move them as new sections under the 'Devices' group. Cc: Paul Burton Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git

[PATCH v2 0/4] MAINTAINERS: Sanitize 'MIPS TCG CPUs' section

Move various files unrelated to MIPS TCG frontend into new sections. Since v1: - Do not add Paul without his consent - un-deprecate nanoMIPS Philippe Mathieu-Daudé (4): MAINTAINERS: Add MIPS general architecture support entry MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware MAINTAI

Re: [PATCH 0/6] More SH4 clean ups

On 10/27/21 03:32, BALATON Zoltan wrote: > Based-on: > ^ (hw/sh4: Codeing style fixes) > > Continuing the clean up stared in previous series this now removes > printfs and QOM-ify sh_serial. > > Is there somebody who will merge these? I don't think there's anybody > sending pull request for SH4

Re: Deprecate the ppc405 boards in QEMU? (was: [PATCH v3 4/7] MAINTAINERS: Orphan obscure ppc platforms)

On 10/5/21 18:20, Daniel P. Berrangé wrote: > On Tue, Oct 05, 2021 at 06:15:35PM +0200, Philippe Mathieu-Daudé wrote: >> On 10/5/21 10:49, Daniel P. Berrangé wrote: >>> On Tue, Oct 05, 2021 at 06:44:23AM +0200, Christophe Leroy wrote: >> I will look at it, please allow me a few weeks though. >

Re: [PATCH] hw/net: store timers for e1000 in vmstate

On Tue, Oct 26, 2021 at 6:36 PM Pavel Dovgalyuk wrote: > > Setting timers randomly when vmstate is loaded breaks > execution determinism. > Therefore this patch allows saving mit and autoneg timers > for e1000. It makes execution deterministic and allows > snapshotting and reverse debugging in ico

Re: [PATCH v2 0/3] memory: memory_region_is_mapped() cleanups

On Tue, Oct 26, 2021 at 06:06:46PM +0200, David Hildenbrand wrote: > This is the follow-up of [1]. > > Playing with memory_region_is_mapped(), I realized that memory regions > mapped via an alias behave a little bit "differently", as they don't have > their ->container set. The patches look ok to

Re: [PATCH 4/4] MAINTAINERS: Agree to maintain nanoMIPS TCG frontend

On 10/4/21 22:08, Jiaxun Yang wrote: > 在 2021/10/4 10:25, Philippe Mathieu-Daudé 写道: >> As of this commit, the nanoMIPS toolchains haven't been merged >> in mainstream projects. However MediaTek provides a toolchain: >> https://github.com/MediaTek-Labs/nanomips-gnu-toolchain/releases/tag/nanoMIPS-2

Re: [PATCH 2/4] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware

On 10/12/21 00:21, Philippe Mathieu-Daudé wrote: > Hi Paul, > > You are the maintainer of the Boston machine which is the > only one using these peripherals; would you agree to be > (co-)maintainer of these files? I am going to respin this patch removing Paul name. > On 10/4/21 11:25, Philippe M

Re: [PATCH v2 2/2] target/riscv: remove force HS exception

On Wed, Oct 27, 2021 at 12:54 AM Jose Martins wrote: > > There is no need to "force an hs exception" as the current privilege > level, the state of the global ie and of the delegation registers should > be enough to route the interrupt to the appropriate privilege level in > riscv_cpu_do_interrupt

Re: [PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS

On Wed, Oct 27, 2021 at 12:53 AM Jose Martins wrote: > > VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when > not delegated in hideleg (which was not being taken into account). This > was mainly because hs level sie was not always considered enabled when > it should. The spec st

Re: [PATCH v2 0/2] mconfigptr support

On Mon, Oct 25, 2021 at 10:51 PM Rahul Pathak wrote: > > Patches add the mconfigptr csr support. > mconfigptr is newly incorporated in risc-v privileged architecture > specification 1.12 version. > priv spec 1.12.0 version check is also added. > > > qemu-system-riscv64 -nographic -machine virt -cp

Re: [PATCH v2 2/2] target/riscv: csr: Implement mconfigptr CSR

On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak wrote: > > Signed-off-by: Rahul Pathak > --- > target/riscv/cpu_bits.h | 1 + > target/riscv/csr.c | 19 +++ > 2 files changed, 16 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

Re: [PATCH v2 1/2] target/riscv: Add priv spec 1.12.0 version check

On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak wrote: > > Signed-off-by: Rahul Pathak > --- > target/riscv/cpu.c | 4 +++- > target/riscv/cpu.h | 1 + > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 788fa0b11c..83c3814a5a 100644 >

Re: [PATCH 4/6] hw/sh4/r2d: Use error_report instead of fprintf to stderr

On 10/26/21 6:32 PM, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan --- hw/sh4/r2d.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 3/6] hw/sh4: Change debug printfs to traces

On 10/26/21 6:32 PM, BALATON Zoltan wrote: +trace_sh_serial("write", size, offs, val); switch (offs) { case 0x00: /* SMR */ s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); @@ -302,10 +298,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,

Re: [PATCH 2/6] hw//sh4: Use qemu_log instead of fprintf to stderr

On 10/26/21 6:32 PM, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 7 --- hw/sh4/sh7750.c | 13 ++--- 2 files changed, 10 insertions(+), 10 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 1/6] hw/sh4: Fix a typo in a comment

On 10/26/21 6:32 PM, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan --- hw/timer/sh_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

[PATCH 3/6] hw/sh4: Change debug printfs to traces

Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 13 ++- hw/char/trace-events | 3 ++ hw/intc/sh_intc.c | 79 +++ hw/intc/trace-events | 8 + hw/sh4/sh7750.c | 8 ++--- hw/sh4/trace-events | 3 ++ hw/sh4/trace.h|

[PATCH 5/6] hw/char/sh_serial: QOM-ify

Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 127 ++-- hw/sh4/sh7750.c | 62 +++-- include/hw/sh4/sh.h | 9 +--- 3 files changed, 123 insertions(+), 75 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c in

[PATCH 1/6] hw/sh4: Fix a typo in a comment

Signed-off-by: BALATON Zoltan --- hw/timer/sh_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 02eb865908..0a18ac8276 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -107,7 +107,7 @@ static void sh_timer_writ

[PATCH 4/6] hw/sh4/r2d: Use error_report instead of fprintf to stderr

Signed-off-by: BALATON Zoltan --- hw/sh4/r2d.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 57ccae7249..72759413f3 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #inclu

[PATCH 0/6] More SH4 clean ups

Based-on: ^ (hw/sh4: Codeing style fixes) Continuing the clean up stared in previous series this now removes printfs and QOM-ify sh_serial. Is there somebody who will merge these? I don't think there's anybody sending pull request for SH4 so maybe Peret/Richard might need to take it. Regards,

[PATCH 6/6] hw/char/sh_serial: Add device id to trace output

Normally there are at least two sh_serial instances. Add device id to trace messages to make it clear which instance they belong to otherwise its not possible to tell which serial device is accessed. Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 6 -- hw/char/trace-events | 2 +-

[PATCH 2/6] hw//sh4: Use qemu_log instead of fprintf to stderr

Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 7 --- hw/sh4/sh7750.c | 13 ++--- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 1b1e6a6a04..c4231975c7 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_ser

Re: [PATCH v3] migration/rdma: Fix out of order wrid

ping again On 18/10/2021 18:18, Li, Zhijian/李 智坚 wrote: > ping > > > On 27/09/2021 15:07, Li Zhijian wrote: >> destination: >> ../qemu/build/qemu-system-x86_64 -enable-kvm -netdev >> tap,id=hn0,script=/etc/qemu-ifup,downscript=/etc/qemu-ifdown -device >> e1000,netdev=hn0,mac=50:52:54:00:11:22 -

[PATCH v4 51/51] tcg/optimize: Propagate sign info for shifting

For constant shifts, we can simply shift the s_mask. For variable shifts, we know that sar does not reduce the s_mask, which helps for sequences like ext32s_i64 t, in sar_i64 t, t, v ext32s_i64 out, t allowing the final extend to be eliminated. Reviewed-by: Alex Bennée Signed

[PATCH v4 47/51] tcg/optimize: Optimize sign extensions

Certain targets, like riscv, produce signed 32-bit results. This can lead to lots of redundant extensions as values are manipulated. Begin by tracking only the obvious sign-extensions, and converting them to simple copies when possible. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson

[PATCH v4 45/51] tcg/optimize: Use fold_xi_to_x for div

Recognize the identity function for division. Suggested-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index fe2b1eb18e..92684d4b1d 100644 --- a/tcg/optimize.c +++ b/tcg/

[PATCH v4 46/51] tcg/optimize: Use fold_xx_to_i for rem

Recognize the constant function for remainder. Suggested-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 92684d4b1d..6c6c523a85 100644 --- a/tcg/optimize.c +++ b/tcg

[PATCH v4 44/51] tcg/optimize: Use fold_xi_to_x for mul

Recognize the identity function for low-part multiply. Suggested-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index bea82305db..fe2b1eb18e 100644 --- a/tcg/optimize.c +++

[PATCH v4 50/51] tcg/optimize: Propagate sign info for bit counting

The results are generally 6 bit unsigned values, though the count leading and trailing bits may produce any value for a zero input. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/optimize.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b

[PATCH v4 33/51] tcg/optimize: Add type to OptContext

Compute the type of the operation early. There are at least 4 places that used a def->flags ladder to determine the type of the operation being optimized. There were two places that assumed !TCG_OPF_64BIT means TCG_TYPE_I32, and so could potentially compute incorrect results for vector operations

[PATCH v4 49/51] tcg/optimize: Propagate sign info for setcond

The result is either 0 or 1, which means that we have a 2 bit signed result, and thus 62 bits of sign. For clarity, use the smask_from_zmask function. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcg/optimize.

[PATCH v4 42/51] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values

This "garbage" setting pre-dates the addition of the type changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64, and INDEX_op_extr{l,h}_i64_i32. So now we have a definitive points at which to adjust z_mask to eliminate such bits from the 32-bit operands. Reviewed-by: Alex Bennée Signed-of

[PATCH v4 39/51] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies

Rename to fold_multiply2, and handle muls2_i32, mulu2_i64, and muls2_i64. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 44 +++- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/tcg/optimize.c b/tc

[PATCH v4 48/51] tcg/optimize: Propagate sign info for logical operations

Sign repetitions are perforce all identical, whether they are 1 or 0. Bitwise operations preserve the relative quantity of the repetitions. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 29 + 1 fil

[PATCH v4 32/51] tcg/optimize: Split out fold_xi_to_i

Pull the "op r, a, 0 => movi r, 0" optimization into a function, and use it in the outer opcode fold functions. Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 38 -- 1 file changed, 20 insert

[PATCH v4 41/51] tcg/optimize: Sink commutative operand swapping into fold functions

Most of these are handled by creating a fold_const2_commutative to handle all of the binary operators. The rest were already handled on a case-by-case basis in the switch, and have their own fold function in which to place the call. We now have only one major switch on TCGOpcode. Introduce NO_DE

[PATCH v4 43/51] tcg/optimize: Use fold_xx_to_i for orc

Recognize the constant function for or-compliment. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/optimize.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 3207817b68..bea82305db 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1

[PATCH v4 40/51] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops

Rename to fold_addsub2. Use Int128 to implement the wider operation. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 65 ++ 1 file changed, 44 insertions(+), 21 deletions(-) diff

[PATCH v4 34/51] tcg/optimize: Split out fold_to_not

Split out the conditional conversion from a more complex logical operation to a simple NOT. Create a couple more helpers to make this easy for the outer-most logical operations. Signed-off-by: Richard Henderson --- tcg/optimize.c | 158 +++-- 1 file c

[PATCH v4 29/51] tcg/optimize: Split out fold_mov

This is the final entry in the main switch that was in a different form. After this, we have the option to convert the switch into a function dispatch table. Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 ++

[PATCH v4 31/51] tcg/optimize: Split out fold_xx_to_x

Pull the "op r, a, a => mov r, a" optimization into a function, and use it in the outer opcode fold functions. Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 39 --- 1 file changed, 24 insert

[PATCH v4 27/51] tcg/optimize: Split out fold_bswap

Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index dd65f1afcd..5374c230da 100644 --- a/tcg/optimiz

[PATCH v4 37/51] tcg/optimize: Split out fold_ix_to_i

Pull the "op r, 0, b => movi r, 0" optimization into a function, and use it in fold_shift. Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 28 ++-- 1 file changed, 10 insertions(+), 18 deletions(-) diff

[PATCH v4 38/51] tcg/optimize: Split out fold_masks

Move all of the known-zero optimizations into the per-opcode functions. Use fold_masks when there is a possibility of the result being determined, and simply set ctx->z_mask otherwise. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/optimize.c | 545 ++

[PATCH v4 28/51] tcg/optimize: Split out fold_dup, fold_dup2

Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 53 +- 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5374c230da..8524fe1f8a 1

[PATCH v4 16/51] tcg/optimize: Split out fold_setcond2

Reduce some code duplication by folding the NE and EQ cases. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 145 - 1 file changed, 72 insertions(+), 73 deletions(-) diff --git a/tcg/optimiz

[PATCH v4 25/51] tcg/optimize: Split out fold_deposit

Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 3bd5f043c8..2c57d08760 100644 --- a/tcg/optimize.

[PATCH v4 36/51] tcg/optimize: Split out fold_xi_to_x

Pull the "op r, a, i => mov r, a" optimization into a function, and use them in the outer-most logical operations. Signed-off-by: Richard Henderson --- tcg/optimize.c | 61 +- 1 file changed, 26 insertions(+), 35 deletions(-) diff --git a/tcg/opti

[PATCH v4 30/51] tcg/optimize: Split out fold_xx_to_i

Pull the "op r, a, a => movi r, 0" optimization into a function, and use it in the outer opcode fold functions. Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 41 - 1 file changed, 24 ins

[PATCH v4 15/51] tcg/optimize: Split out fold_const{1,2}

Split out a whole bunch of placeholder functions, which are currently identical. That won't last as more code gets moved. Use CASE_32_64_VEC for some logical operators that previously missed the addition of vectors. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Hender

[PATCH v4 22/51] tcg/optimize: Split out fold_movcond

Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 56 -- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 9d1d045363..110b3d1cc2 1

[PATCH v4 20/51] tcg/optimize: Split out fold_mulu2_i32

Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 37 + 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index f79cb44944..805522f99d 100644 --- a/t

[PATCH v4 26/51] tcg/optimize: Split out fold_count_zeros

Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 ++-- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 2c57d08760..dd65f1afcd 100644 --- a/tcg/op

[PATCH v4 35/51] tcg/optimize: Split out fold_sub_to_neg

Even though there is only one user, place this more complex conversion into its own helper. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 89 ++ 1 file changed, 47 insertions(+), 42 deletions(-) diff --git a/tcg/op

[PATCH v4 21/51] tcg/optimize: Split out fold_addsub2_i32

Add two additional helpers, fold_add2_i32 and fold_sub2_i32 which will not be simple wrappers forever. Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 70 +++--- 1 file changed, 44 ins

[PATCH v4 18/51] tcg/optimize: Split out fold_brcond

Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 33 +++-- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c9db14f1d0..24ba6d2830 100644 --- a/tcg/o

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