Re: [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: -qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS" #SUFFIX "%cX" \ - " at 0x" TARGET_FMT_lx ", RA = " TARGET_FMT_ld " > %d\n",\ - c, env->nip, idx, maxidx);

Re: [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 target/ppc/insn32.decode| 5 + target/ppc/int_helper.c | 21 --- target/ppc/translate/v

Re: [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Implements the following PowerISA v3.1 instructions: vinsbvlx: Vector Insert Byte from VSR using GPR-specified Left-Index vinshvlx: Vector Insert Halfword from VSR using GPR-specified Left-Index vinswvlx: V

Re: [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size, +void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv)) +{ +REQUIRE_INSNS_FLAGS2(ctx, ISA310); +REQUIRE_VECTOR(ctx); + +if (a->

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +#if defined(TARGET_PPC64) +return do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], cpu_gpr[a->vrb], +gen_helper); +#else +bool ok; +TCGv_i64 val; + +val = tcg_temp_new_i64(); +tcg_gen_extu_tl_i6

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +#if defined(HOST_WORDS_BIGENDIAN) +#define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->VsrB(IDX)) +#else +#define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->VsrB(IDX) - (SIZE) + 1) +#endif This is a bit confusing. There's host adjustment in VsrB *and*

Re: [PATCH 14/33] target/ppc: Implement vsldbi/vsrdbi instructions

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +if (a->sh != 0) { +t2 = tcg_temp_new_i64(); + +/* vrt.l = (vrb.l >> sh) | (vrb.h << (64 - sh)) */ +tcg_gen_shri_i64(t0, t0, a->sh); +tcg_gen_shli_i64(t2, t1, 64 - a->sh); +tcg_gen_or_i64(t0, t0

Re: [PATCH v8 07/10] ACPI ERST: create ACPI ERST table for pc/x86 machines

On Fri, 22 Oct 2021, Eric DeVolder wrote: > Ani, inline below. > eric > > On 10/22/21 05:18, Ani Sinha wrote: > > > > > > On Fri, 15 Oct 2021, Eric DeVolder wrote: > > > > > This change exposes ACPI ERST support for x86 guests. > > > > > > Signed-off-by: Eric DeVolder > > > --- > > > hw/i386

Re: Looking for advise on debugging a non-boot kernel on qemu-system-sh4

Hello Zoltan! On 10/23/21 03:07, BALATON Zoltan wrote: >> I can confirm that the default config works for me, too. Both with gcc-8 and >> gcc-11. > > OK with your config I can reproduce the problem too but the kernel with that > config > is 177MB and the r2d board has 64MB RAM so this can't wor

Re: Looking for advise on debugging a non-boot kernel on qemu-system-sh4

On Sat, 23 Oct 2021, John Paul Adrian Glaubitz wrote: On 10/22/21 23:49, John Paul Adrian Glaubitz wrote: How did you compile the kernel that does not boot? What config have you used? The config is constructed from the Debian kernel configuration tree. I have uploaded the resulting config fil

Re: [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Luis Pires Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.inc | 36 + 2 files changed, 38 insertions(+) N

Re: [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Luis Pires Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.inc | 36 + 2 files changed, 38 insertions(+) N

Re: [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 92b9527aff..f0f6d561e1 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1559,6 +1559,24 @@ GEN_VXF

Re: [PATCH 10/33] target/ppc: Implement pextd instruction

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h| 1 + target/ppc/insn32.decode | 1 + target/ppc/int_helper.c| 18 ++ target/pp

Re: [PATCH 09/33] target/ppc: Implement pdepd instruction

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h| 1 + target/ppc/insn32.decode | 1 + target/ppc/int_helper.c| 18 ++ target/pp

Re: [PATCH 08/33] target/ppc: Implement cnttzdm

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +uint64_t helper_CNTTZDM(uint64_t src, uint64_t mask) +{ +uint64_t count = 0; + +while (mask != 0) { +if ((src >> ctz64(mask)) & 1) { +break; +} + +count++; +mask &= mask - 1; +} + +

Re: [PATCH 07/33] target/ppc: Implement cntlzdm

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +uint64_t helper_CNTLZDM(uint64_t src, uint64_t mask) +{ +uint64_t sel_bit, count = 0; + +while (mask != 0) { +sel_bit = 0x8000ULL >> clz64(mask); + +if (src & sel_bit) { +break; +}

Re: Looking for advise on debugging a non-boot kernel on qemu-system-sh4

Hi Zoltan! On 10/22/21 23:49, John Paul Adrian Glaubitz wrote: >> How did you compile the kernel that does not boot? What config have you used? > > The config is constructed from the Debian kernel configuration tree. I have > uploaded > the resulting config file here: > >> https://people.debian

Re: [PATCH 06/33] target/ppc: Implement PLQ and PSTQ

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 4 target/ppc/translate/fixedpoint-impl.c.inc | 12 2 files changed, 16 insertions(+) Reviewed-by: Richard Henders

Re: [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 11 ++ target/ppc/translate.c | 156 + target/ppc/translate/fixedpoint-impl.c.inc | 98 ++

Re: [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: pherde Signed-off-by: Fernando Eckhardt Valle Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 11 +++ target/ppc/translate/fp-impl.c.inc | 14 ++ 2 files changed, 25 insertions(+) Rev

Re: [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +/*Floating-point Load/Store Instructions */ +static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ, + bool update, bool store, bool single) +{ +TCGv ea; +TCGv

RE: [PATCH v3 33/48] tcg/optimize: Add type to OptContext

From: Richard Henderson > @@ -1392,18 +1408,18 @@ void tcg_optimize(TCGContext *s) > /* Proceed with possible constant folding. */ > break; > } > -if (opc == INDEX_op_sub_i32) { > +switch (ctx.type) { > +

Re: [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: pherde Move resolve_PLS_D from fixedpoint-impl.c.inc to translate.c because this way the function can be used not only by fixed point instructions. Signed-off-by: Fernando Eckhardt Valle (pherde) Signed-off-by: Matheus Ferst ---

Re: [PATCH 01/33] target/ppc: introduce do_ea_calc

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: pherde The do_ea_calc function will calculate the effective address(EA) according to PowerIsa 3.1. With that, it was replaced part of do_ldst() that calculates the EA by this new function. Signed-off-by: Fernando Eckhardt Valle (p

Re: [PATCH 01/33] target/ppc: introduce do_ea_calc

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +static inline void do_ea_calc(DisasContext *ctx, int ra, TCGv displ, TCGv ea) +{ +if (ra) { +tcg_gen_add_tl(ea, cpu_gpr[ra], displ); +} else { +tcg_gen_mov_tl(ea, displ); +} +if (NARROW_MODE(ctx)) { +

Re: Looking for advise on debugging a non-boot kernel on qemu-system-sh4

Hi Zoltan! Thanks a lot for helping me to investigate the problem. Much appreciated! On 10/22/21 23:06, BALATON Zoltan wrote: >> I think I've seen problems with compressed kernel images and QEMU before. I >> will switch >> to an uncompressed kernel and try again. > > How did you compile the ker

Re: [PATCH v2 5/5] sgx: Reset the vEPC regions during VM reboot

On 22/10/21 21:27, Yang Zhong wrote: + +for (j = 0; j < num; j++) { +epc = pcms->sgx_epc.sections[j]; +hostmem = MEMORY_BACKEND(epc->hostmem); +fd = memory_region_get_fd(host_memory_backend_get_memory(hostmem)); + +failures = ioctl(fd, SGX_IOC_VEPC_REMOVE_ALL);

Re: [PATCH 1/3] target/mips: Fix MSA MADDV.B opcode

On 10/22/21 10:45 AM, Philippe Mathieu-Daudé wrote: The result of the 'Vector Multiply and Add' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 7a7a162adde mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that.

Re: [PATCH 2/3] target/mips: Fix MSA MSUBV.B opcode

On 10/22/21 10:45 AM, Philippe Mathieu-Daudé wrote: The result of the 'Vector Multiply and Subtract' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 5f148a02327 mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix

Re: [PULL 00/33] riscv-to-apply queue

repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211022-2 for you to fetch changes up to 11ec06f9eaedc801ded34c79861367b76ab2b731: hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id (2021-10-22 23:3

RE: [PATCH v3 32/48] tcg/optimize: Split out fold_xi_to_i

From: Richard Henderson > Pull the "op r, a, 0 => movi r, 0" optimization into a function, and use it > in the > outer opcode fold functions. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 32 +++- > 1 file chang

Re: Looking for advise on debugging a non-boot kernel on qemu-system-sh4

On Thu, 21 Oct 2021, John Paul Adrian Glaubitz wrote: On 10/21/21 15:49, BALATON Zoltan wrote: So somthing seems to overwrite it. Maybe you can try building an uncompressed kernel or one using a different compression and see if that does the same, at least that way we can see if it's in the deco

RE: [PATCH v3 31/48] tcg/optimize: Split out fold_xx_to_x

From: Richard Henderson > Pull the "op r, a, a => mov r, a" optimization into a function, and use it in > the > outer opcode fold functions. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 39 --- > 1 file

RE: [PATCH v3 30/48] tcg/optimize: Split out fold_xx_to_i

From: Richard Henderson > Pull the "op r, a, a => movi r, 0" optimization into a function, and use it > in the > outer opcode fold functions. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 41 - > 1 f

Re: [PULL 0/2] Seabios 20211022 patches

kraxel.org/qemu tags/seabios-20211022-pull-request for you to fetch changes up to 9fb3fcfce512da58cd048eaefd293e1d3f513de2: update seabios binaries (2021-10-22 12:32:29 +0200) seabios: update to master branc

gitlab/cirrus auth token failure

Hi Daniel, you win the cookie because you committed cirrus.yml. I should have reported this before the weekend, but at some point this week the auth tokens expired(?). All of the cirrus-run tests are now failing: cirrus_run.api.CirrusAPIError: API returned 1 error(s): [ { 'extensions': {'clas

[PATCH v16 8/8] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16fac64806..7d53125dbc 100644 --- a/target/riscv/cpu.c ++

[PATCH v16 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 285 + 3 files changed, 298 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 788fa0b11

Re: [PATCH v8 07/10] ACPI ERST: create ACPI ERST table for pc/x86 machines

Ani, inline below. eric On 10/22/21 05:18, Ani Sinha wrote: On Fri, 15 Oct 2021, Eric DeVolder wrote: This change exposes ACPI ERST support for x86 guests. Signed-off-by: Eric DeVolder --- hw/i386/acpi-build.c | 9 + hw/i386/acpi-microvm.c | 9 + include/hw/acpi/erst.

[PATCH v16 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/r

[PATCH v16 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_helper.c | 18 ++ target/riscv/translate.c | 39 +-- 3 files c

[PATCH v16 0/8] RISC-V Pointer Masking implementation

v15: Renamed pm into pointer_masking in machine state. v14: Addressed Richard's comments from previous series. v13: Rebased QEMU and addressed Richard's comment. v12: Updated function for adjusting address with pointer masking to allocate and use temp register. v11: Addressed a few style issue

[PATCH v16 4/8] [RISCV_PM] Add J extension state description

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/machine.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index f64b2a96c1..7b4c739564 100644 --- a/target/riscv/machine.c +++ b/target/ris

[PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b767a4a0b..16fac64806 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -271,6 +271,13 @@ static void riscv_cpu_dump_state(CPUSta

[PATCH v16 1/8] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30be8..1cfc6a53a0 100644 --- a/target/riscv/cpu.h +++

[PATCH v16 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index cffcd3a5df..aa0bce4e06 100644 --- a/target/riscv/cpu_bits.

RE: [PATCH v3 29/48] tcg/optimize: Split out fold_mov

From: Richard Henderson > This is the final entry in the main switch that was in a different form. > After this, > we have the option to convert the switch into a function dispatch table. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 27 +

Re: [PULL 0/3] aspeed queue

github.com/legoater/qemu/ tags/pull-aspeed-20211022 for you to fetch changes up to b12fa6118f4d838d19720ec6476a1666a1b43474: speed/sdhci: Add trace events (2021-10-22 09:52:17 +0200) Aspeed patches : * New fp5280g2-bmc board (Joh

[PATCH 0/3] target/mips: MSA opcode fixes

Fix a pair of MSA opcodes, and update the MSA_IR config register in the Loongson-3A4000 model. Philippe Mathieu-Daudé (3): target/mips: Fix MSA MADDV.B opcode target/mips: Fix MSA MSUBV.B opcode target/mips: Fix Loongson-3A4000 MSAIR config register target/mips/tcg/msa_helper.c | 64 ++

RE: [PATCH v3 26/48] tcg/optimize: Split out fold_count_zeros

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 32 ++-- > 1 file changed, 18 insertions(+), 14 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

[PATCH 2/3] target/mips: Fix MSA MSUBV.B opcode

The result of the 'Vector Multiply and Subtract' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 5f148a02327 mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo Fixes: 5f148a02327 ("ta

RE: [PATCH v3 28/48] tcg/optimize: Split out fold_dup, fold_dup2

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 53 +- > 1 file changed, 31 insertions(+), 22 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

[PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register

When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine : loongson,generic cpu model : Loongson-3 V0.4

[PATCH 1/3] target/mips: Fix MSA MADDV.B opcode

The result of the 'Vector Multiply and Add' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 7a7a162adde mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo Fixes: 7a7a162adde ("target/m

RE: [PATCH v3 24/48] tcg/optimize: Split out fold_extract, fold_sextract

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 48 ++-- > 1 file changed, 30 insertions(+), 18 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

RE: [PATCH v3 27/48] tcg/optimize: Split out fold_bswap

From: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 27 --- > 1 file changed, 16 insertions(+), 11 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Di

RE: [PATCH v3 22/48] tcg/optimize: Split out fold_movcond

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 56 -- > 1 file changed, 31 insertions(+), 25 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

RE: [PATCH v3 25/48] tcg/optimize: Split out fold_deposit

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 25 +++-- > 1 file changed, 15 insertions(+), 10 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

RE: [PATCH v3 23/48] tcg/optimize: Split out fold_extract2

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 39 ++- > 1 file changed, 22 insertions(+), 17 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

RE: [PATCH v3 21/48] tcg/optimize: Split out fold_addsub2_i32

From: Richard Henderson > Add two additional helpers, fold_add2_i32 and fold_sub2_i32 which will not be > simple wrappers forever. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 70 +++--- > 1 file changed, 44 insertions(+), 26 deletion

RE: [PATCH v3 20/48] tcg/optimize: Split out fold_mulu2_i32

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 37 + > 1 file changed, 21 insertions(+), 16 deletions(-) Reviewed-by: Luis Pires -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer

RE: [PATCH v3 17/48] tcg/optimize: Split out fold_brcond2

From: Richard Henderson > Reduce some code duplication by folding the NE and EQ cases. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 159 + > 1 file changed, 81 insertions(+), 78 deletions(-) Reviewed-by: Luis Pires -- Luis Pire

Re: [RFC PATCH v1 2/2] Enable custom instruction suport for Andes A25 and AX25 CPU model

On 10/22/21 4:52 AM, Alex Bennée wrote: Ruinland ChuanTzu Tsai writes: On Thu, Oct 21, 2021 at 12:17:47PM -0700, Richard Henderson wrote: On 10/21/21 8:11 AM, Ruinland Chuan-Tzu Tsai wrote: In this patch, we demonstrate how Andes Performance Extension(c) insn : bfos and bfoz could be used w

[PATCH v4] isa-applesmc: provide OSK forwarding on Apple hosts

On Apple hosts we can read AppleSMC OSK key directly from host's SMC and forward this value to QEMU Guest. Usage: `-device isa-applesmc,hostosk=on` Apple licence allows use and run up to two additional copies or instances of macOS operating within virtual operating system environments on each App

Re: [PATCH v3] isa-applesmc: provide OSK forwarding on Apple hosts

Le 22/10/2021 à 18:07, Vladislav Yaroshchuk a écrit : Hi, Laurent! Thank you for your review! пт, 22 окт. 2021 г. в 14:36, Laurent Vivier mailto:laur...@vivier.eu>>: ... > +        && !applesmc_read_host_osk(&host_osk)) { > +        if (s->osk) { > +            warn_report("pro

Re: [PATCH v3] isa-applesmc: provide OSK forwarding on Apple hosts

Hi, Laurent! Thank you for your review! пт, 22 окт. 2021 г. в 14:36, Laurent Vivier : > Le 22/10/2021 à 13:10, Vladislav Yaroshchuk a écrit : > > On Apple hosts we can read AppleSMC OSK key directly from host's > > SMC and forward this value to QEMU Guest. > > > > Usage: > > `-device isa-applesmc

[PATCH v3 3/3] contrib/plugins: add a drcov plugin

This patch adds the ability to generate files in drcov format. Primary goal this script is to have coverage logfiles thatwork in Lighthouse. Signed-off-by: Ivanov Arkady --- contrib/plugins/Makefile |1 contrib/plugins/drcov.c | 152 ++ 2 files

[PATCH v3 2/3] This patch adds helper functions to the drcov plugin.

Which provide information about: - start_code. - end_code. - entry. - path to the executable binary. Signed-off-by: Ivanov Arkady --- include/qemu/qemu-plugin.h | 17 plugins/api.c| 44 ++ plugins/qemu-plugins.symbols

[PATCH v3 1/3] src/plugins: sorted list

The list is sorted to make it easier to find missing characters Signed-off-by: Ivanov Arkady --- plugins/qemu-plugins.symbols | 52 +- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.sym

[PATCH v3 0/3] plugins: add a drcov plugin

These patches adds the ability to generate files in drcov format. Primary goal this scripts is to have coverage logfiles thatwork in Lighthouse. Changelog: v3: * Increased speed of the plugin. * Added documentation to the helper functions. * Sorted qemu-plugins.symbols. v2: * Added path t

Re: [PULL 0/9] Q800 patches

5:04 +0200) Pull request Q800 20211022 GLUE updates for A/UX mode Mark Cave-Ayland (9): mac_via: update comment for VIA1B_vMystery bit q800: move VIA1 IRQ from level 1 to level 6 q800: use GLUE IRQ numbers instead of IRQ leve

Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()

On 10/22/21 1:34 AM, Ruinland ChuanTzu Tsai wrote: +/* Custom CSR value holder per hart */ +void *custom_csr_val; }; Value singular? Anyhow, I think that it's a mistake trying to hide the value structure in another file. It complicates allocation of the CPURISCVState, and you have

Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length

On 10/22/21 1:26 AM, LIU Zhiwei wrote: As the specification said, "PC bits above XLEN are ignored, and when the PC is written, it is sign-extended to fill the widest supported XLEN." We still need special process of PC for exceptions or jump instructions. I have two methods to implement  PC regi

Re: [PATCH v4] tests: qtest: Add virtio-iommu test

On Tue, Oct 19, 2021 at 08:37:55AM +0200, Eric Auger wrote: > +static void pci_config(void *obj, void *data, QGuestAllocator *t_alloc) > +{ > +QVirtioIOMMU *v_iommu = obj; > +QVirtioDevice *dev = v_iommu->vdev; > +uint64_t input_range_start = qvirtio_config_readq(dev, 8); > +uint64_

Re: [PATCH v3 05/48] tcg/optimize: Move prev_mb into OptContext

On 10/21/21 23:04, Richard Henderson wrote: > This will expose the variable to subroutines that > will be broken out of tcg_optimize. > > Reviewed-by: Alex Bennée > Reviewed-by: Luis Pires > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 11 ++- > 1 file changed, 6 insertion

Re: [PATCH v3 03/48] tcg/optimize: Remove do_default label

On 10/21/21 23:04, Richard Henderson wrote: > Break the final cleanup clause out of the main switch > statement. When fully folding an opcode to mov/movi, > use "continue" to process the next opcode, else break > to fall into the final cleanup. > > Reviewed-by: Alex Bennée > Reviewed-by: Luis Pi

Re: [RESEND PATCH 2/2] hw/i386: Rename default_bus_bypass_iommu

On Fri, Oct 22, 2021 at 10:46:08AM -0400, Michael S. Tsirkin wrote: > On Wed, Oct 13, 2021 at 05:06:08PM +0100, Jean-Philippe Brucker wrote: > > Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine > > parameter definitions cannot use underscores, because keyval_dashify() > > tran

Re: [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function

On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis wrote: > > From: Alistair Francis > > Signed-off-by: Alistair Francis > --- > hw/riscv/sifive_u.c | 14 +- > 1 file changed, 1 insertion(+), 13 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index fc5790b8ce

Re: [PATCH v2 5/5] hw/riscv: virt: Use the PLIC config helper function

On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis wrote: > > From: Alistair Francis > > Signed-off-by: Alistair Francis > --- > hw/riscv/virt.c | 20 +--- > 1 file changed, 1 insertion(+), 19 deletions(-) > Reviewed-by: Bin Meng Tested-by: Bin Meng

Re: [PATCH v2 4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function

On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis wrote: > > From: Alistair Francis > > Signed-off-by: Alistair Francis > --- > include/hw/riscv/microchip_pfsoc.h | 1 - > hw/riscv/microchip_pfsoc.c | 14 +- > 2 files changed, 1 insertion(+), 14 deletions(-) > Reviewed-by:

Re: [PATCH v3 02/48] tcg/optimize: Split out OptContext

On 10/21/21 23:04, Richard Henderson wrote: > Provide what will become a larger context for splitting > the very large tcg_optimize function. > > Reviewed-by: Alex Bennée > Reviewed-by: Luis Pires > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 77 ++

Re: [RESEND PATCH 2/2] hw/i386: Rename default_bus_bypass_iommu

On Wed, Oct 13, 2021 at 05:06:08PM +0100, Jean-Philippe Brucker wrote: > Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine > parameter definitions cannot use underscores, because keyval_dashify() > transforms them to dashes and the parser doesn't find the parameter. > > This a

Re: [PATCH v3 25/48] tcg/optimize: Split out fold_deposit

On 10/21/21 23:05, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 25 +++-- > 1 file changed, 15 insertions(+), 10 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 19/48] tcg/optimize: Split out fold_setcond

On 10/21/21 23:05, Richard Henderson wrote: > Reviewed-by: Luis Pires > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 23 ++- > 1 file changed, 14 insertions(+), 9 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 28/48] tcg/optimize: Split out fold_dup, fold_dup2

On 10/21/21 23:05, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 53 +- > 1 file changed, 31 insertions(+), 22 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 26/48] tcg/optimize: Split out fold_count_zeros

On 10/21/21 23:05, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 32 ++-- > 1 file changed, 18 insertions(+), 14 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 39/48] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies

On 10/21/21 23:05, Richard Henderson wrote: > Rename to fold_multiply2, and handle muls2_i32, mulu2_i64, > and muls2_i64. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 44 +++- > 1 file changed, 35 insertions(+), 9 deletions(-) Reviewed-by

Re: [PATCH v3 18/48] tcg/optimize: Split out fold_brcond

On 10/21/21 23:05, Richard Henderson wrote: > Reviewed-by: Luis Pires > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 33 +++-- > 1 file changed, 19 insertions(+), 14 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 24/48] tcg/optimize: Split out fold_extract, fold_sextract

On 10/21/21 23:05, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 48 ++-- > 1 file changed, 30 insertions(+), 18 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}

On 10/21/21 23:05, Richard Henderson wrote: > This puts the separate mb optimization into the same framework > as the others. While fold_qemu_{ld,st} are currently identical, > that won't last as more code gets moved. > > Reviewed-by: Luis Pires > Signed-off-by: Richard Henderson > --- > tcg/o

Re: [PATCH v3 23/48] tcg/optimize: Split out fold_extract2

On 10/21/21 23:05, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 39 ++- > 1 file changed, 22 insertions(+), 17 deletions(-) > +static bool fold_extract2(OptContext *ctx, TCGOp *op) > +{ > +if (arg_is_const(op->args[1

Re: [PATCH v3 20/48] tcg/optimize: Split out fold_mulu2_i32

On 10/21/21 23:05, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 37 + > 1 file changed, 21 insertions(+), 16 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v3 10/48] tcg/optimize: Change fail return for do_constant_folding_cond*

On 10/21/21 23:05, Richard Henderson wrote: > Return -1 instead of 2 for failure. > This us to use comparisons against 0 for all cases. Typo "This is to use ..."? > > Reviewed-by: Luis Pires > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 145 +-

Re: [PATCH v3 22/48] tcg/optimize: Split out fold_movcond

On 10/21/21 23:05, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 56 -- > 1 file changed, 31 insertions(+), 25 deletions(-) > +static bool fold_movcond(OptContext *ctx, TCGOp *op) > +{ > +TCGOpcode opc = o

Re: [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function

On Fri, Oct 22, 2021 at 2:01 PM Alistair Francis wrote: > > From: Alistair Francis > > Add a generic function that can create the PLIC strings. > > Signed-off-by: Alistair Francis > --- > include/hw/riscv/boot.h | 2 ++ > hw/riscv/boot.c | 25 + > 2 files change

Re: [PATCH v3 21/48] tcg/optimize: Split out fold_addsub2_i32

On 10/21/21 23:05, Richard Henderson wrote: > Add two additional helpers, fold_add2_i32 and fold_sub2_i32 > which will not be simple wrappers forever. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 70 +++--- > 1 file changed, 44 inserti

Re: [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration

On Fri, Oct 22, 2021 at 6:38 PM Philippe Mathieu-Daudé wrote: > > On 10/22/21 08:01, Alistair Francis wrote: > > From: Alistair Francis > > > > Using a macro for the PLIC configuration doesn't make the code any > > easier to read. Instead it makes it harder to figure out what is going > > on, so

[PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.fran...@wdc.com --- hw/intc/sifive_plic.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/intc/sifive_pli

[PULL 32/33] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id

From: Bin Meng Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev s

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