Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
> Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating
> whether the hardware is configured for A/UX mode.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 18 ++
> hw/misc/trace-ev
From: Chih-Min Chao
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,
The original logic:
Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan.
The alternative path:
Set invalid flag if ft1 == sNaN || ft2 == sNaN.
Return NaN only if ft1 == NaN && ft2 == Na
From: Chih-Min Chao
The sNaN propagation behavior has been changed since
cd20cee7 in https://github.com/riscv/riscv-isa-manual
Signed-off-by: Chih-Min Chao
---
target/riscv/fpu_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/targ
From: Frank Chang
In IEEE 754-2019, minNum, maxNum, minNumMag and maxNumMag are removed
and replaced with minimum, minimumNumber, maximum and maximumNumber.
minimumNumber/maximumNumber behavior for SNaN is changed to:
* If both operands are NaNs, a QNaN is returned.
* If either operand is a
於 2021年10月15日 週五 下午2:12寫道：
> From: Chih-Min Chao
>
> The sNaN propagation behavior has been changed since
> cd20cee7 in https://github.com/riscv/riscv-isa-manual
>
> Signed-off-by: Chih-Min Chao
> ---
> target/riscv/fpu_helper.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
On Fri, Oct 15, 2021 at 2:11 PM wrote:
> From: Chih-Min Chao
>
> For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,
>
> The original logic:
> Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan.
>
> The alternative path:
> Set invalid flag if ft1 == sNaN || ft2
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
> In order to allow dynamic routing of IRQs to different IRQ levels on the CPU
> depending upon port B bit 6, use GLUE IRQ numbers and map them to the the
> corresponding CPU IRQ level accordingly.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
> On a Quadra 800 machine Linux sets via_alt_mapping to 1 and clears port B bit
> 6 to
> ensure that the VIA1 IRQ is delivered at level 6 rather than level 1. Even
> though
> QEMU doesn't yet emulate this behaviour, Linux still installs the VIA1 l
On Thu, Sep 16, 2021 at 11:42 PM Anup Patel wrote:
>
> On Wed, Sep 15, 2021 at 6:19 AM Alistair Francis wrote:
> >
> > On Tue, Sep 14, 2021 at 2:33 AM Anup Patel wrote:
> > >
> > > On Thu, Sep 9, 2021 at 12:14 PM Alistair Francis
> > > wrote:
> > > >
> > > > On Thu, Sep 2, 2021 at 9:26 PM Anup
On Wed, Oct 13, 2021 at 6:36 AM Jason Wang wrote:
>
>
> 在 2021/10/1 下午3:06, Eugenio Pérez 写道:
> > Signed-off-by: Eugenio Pérez
>
>
> Commit log please.
>
> Thanks
>
Sorry, this was another commit that was intended to be squashed.
I think I squashed two other (previous) commits by mistake in the
On Wed, Oct 13, 2021 at 6:35 AM Jason Wang wrote:
>
>
> 在 2021/10/1 下午3:05, Eugenio Pérez 写道:
> > Signed-off-by: Eugenio Pérez
> > ---
> > hw/virtio/vhost-shadow-virtqueue.c | 11 ++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/virtio/vhost-shadow-virtqu
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
> According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to
> configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't
> particularly descriptive, the patch leaves this to ensure that the constants
> in mac_via
On Fri, Oct 15, 2021 at 01:38:06PM +0800, lma wrote:
> 在 2021-10-15 07:43，Peter Xu 写道：
> > On Thu, Oct 14, 2021 at 05:15:48PM +0800, Lin Ma wrote:
> > > Since kernel v5.11, Unprivileged user (without SYS_CAP_PTRACE
> > > capability)
> > > must pass UFFD_USER_MODE_ONLY to userfaultd in case
> > > un
From: Chih-Min Chao
The sNaN propagation behavior has been changed since
cd20cee7 in https://github.com/riscv/riscv-isa-manual
Signed-off-by: Chih-Min Chao
---
target/riscv/fpu_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/targ
From: Chih-Min Chao
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,
The original logic:
Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan.
The alternative path:
Set invalid flag if ft1 == sNaN || ft2 == sNaN.
Return NaN only if ft1 == NaN && ft2 == Na
On 14/10/2021 17.58, Mark Cave-Ayland wrote:
On 14/10/2021 16:37, Thomas Huth wrote:
On 14/10/2021 17.26, Philippe Mathieu-Daudé wrote:
On 10/14/21 13:29, Cédric Le Goater wrote:
On 10/14/21 12:34, Christophe Leroy wrote:
I have the following change in QEMU to be able to run the bamboo,
fo
在 2021-10-15 07:43，Peter Xu 写道：
On Thu, Oct 14, 2021 at 05:15:48PM +0800, Lin Ma wrote:
Since kernel v5.11, Unprivileged user (without SYS_CAP_PTRACE
capability)
must pass UFFD_USER_MODE_ONLY to userfaultd in case
unprivileged_userfaultfd
sysctl knob is 0.
Please refer to https://lwn.net/Artic
On Thu, Oct 14, 2021 at 4:43 AM Philipp Tomsich
wrote:
>
> The earlier implementation fell into a corner case for bytes that were
> 0x01, giving a wrong result (but not affecting our application test
> cases for strings, as an ASCII value 0x01 is rare in those...).
>
> This changes the algorithm t
On Thu, Oct 14, 2021 at 09:36:17PM +0200, Gerd Hoffmann wrote:
> Allows edk2 detect virtio-mmio devices and pcie ecam.
> See comment in hw/i386/microvm-dt.c for more details.
>
> Signed-off-by: Gerd Hoffmann
> ---
> hw/i386/microvm-dt.h | 8 +
> include/hw/i386/microvm.h
On Thu, Oct 14, 2021 at 7:08 AM Richard Henderson
wrote:
>
> When target_long is 64-bit, we still want a 32-bit bswap for rev8.
> Since this opcode is specific to RV32, we need not conditionalize.
>
> Reviewed-by: LIU Zhiwei
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alista
On Thu, Oct 14, 2021 at 7:03 AM Richard Henderson
wrote:
>
> In preparation for RV128, consider more than just "w" for
> operand size modification. This will be used for the "d"
> insns from RV128 as well.
>
> Rename oper_len to get_olen to better match get_xlen.
>
> Signed-off-by: Richard Hender
On Thu, Oct 14, 2021 at 6:59 AM Richard Henderson
wrote:
>
> In preparation for RV128, replace a simple predicate
> with a more versatile test.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 32 +---
>
On Thu, Oct 14, 2021 at 6:55 AM Richard Henderson
wrote:
>
> We're currently assuming SEW <= 3, and the "else" from
> the SEW == 3 must be less. Use a switch and explicitly
> bound both SEW and SEQ for all cases.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> -
On Thu, Oct 14, 2021 at 6:57 AM Richard Henderson
wrote:
>
> Use the same REQUIRE_64BIT check that we use elsewhere,
> rather than open-coding the use of is_32bit.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3
On Thu, Oct 14, 2021 at 6:54 AM Richard Henderson
wrote:
>
> Shortly, the set of supported XL will not be just 32 and 64,
> and representing that properly using the enumeration will be
> imperative.
>
> Two places, booting and gdb, intentionally use misa_mxl_max
> to emphasize the use of the reset
On Thu, Oct 14, 2021 at 6:51 AM Richard Henderson
wrote:
>
> The hw representation of misa.mxl is at the high bits of the
> misa csr. Representing this in the same way inside QEMU
> results in overly complex code trying to check that field.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alis
在 2021/10/15 上午1:56, Eugenio Perez Martin 写道:
On Wed, Oct 13, 2021 at 6:31 AM Jason Wang wrote:
在 2021/10/1 下午3:05, Eugenio Pérez 写道:
Initial version of shadow virtqueue that actually forward buffers. There
are no iommu support at the moment, and that will be addressed in future
patches of
在 2021/10/14 下午11:58, Eugenio Perez Martin 写道:
On Wed, Oct 13, 2021 at 5:49 AM Jason Wang wrote:
在 2021/10/1 下午3:05, Eugenio Pérez 写道:
This will make qemu aware of the device used buffers, allowing it to
write the guest memory with its contents if needed.
Since the use of vhost_virtqueue_s
Since the prctl constants are supposed to be generic, supply
any that are not provided by the host.
Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE,
PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL,
PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do
not support these o
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
target/sparc/mmu_helper.c | 72 +--
1 file changed, 46 insertions(+), 26 deletions(-)
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 2ad47391d0..014601e701 100644
---
在 2021/10/15 上午12:39, Eugenio Perez Martin 写道:
On Wed, Oct 13, 2021 at 5:47 AM Jason Wang wrote:
在 2021/10/1 下午3:05, Eugenio Pérez 写道:
This will make qemu aware of the device used buffers, allowing it to
write the guest memory with its contents if needed.
Since the use of vhost_virtqueue_s
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson
---
linux-user/alpha/target_prctl.h | 2 +-
target/alpha/cpu.h | 5 +
target/alpha/translate.c
For s390x, the only unaligned accesses that are signaled are atomic,
and we don't actually want to raise SIGBUS for those, but instead
raise a SPECIFICATION error, which the kernel will report as SIGILL.
Split out a do_unaligned_access function to share between the user-only
s390x_cpu_record_sigbu
Create a list of subcodes that we want to pass on, a list of
subcodes that should not be passed on because they would affect
the running qemu itself, and a list that probably could be
implemented but require extra work. Do not pass on unknown subcodes.
Signed-off-by: Richard Henderson
---
linux-
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson
---
linux-user/hppa/target_prctl.h | 2 +-
target/hppa/cpu.h | 5 -
target/hppa/translate.c
The kernel will fix up unaligned accesses, so emulate that
by allowing unaligned accesses to succeed.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/microblaze/transla
Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS
si_codes to continue into the host-to-guest signal coversion code.
Signed-off-by: Richard Henderson
---
linux-user/signal.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index df
This requires extra work for each target, but adds the
common syscall code, and the necessary flag in CPUState.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 3 +++
linux-user/generic/target_prctl_unalign.h | 27 +++
cpu.c
Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which
has access to complete alignment info from the TCGMemOpIdx arg.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/acc
We will raise SIGBUS directly from cpu_loop_exit_sigbus.
Signed-off-by: Richard Henderson
---
linux-user/hppa/cpu_loop.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
index e0a62deeb9..375576c8f0 100644
--- a/linux-user/hppa/cpu
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
The Linux kernel does not handle all memory operations: no
floating-point and no MAC.
Signed-off-by: Richard Henderson
---
linux-user/sh4/target_prctl
Add a new user-only interface for updating cpu state before
raising a signal. This will take the place of do_unaligned_access
for user-only and should result in less boilerplate for each guest.
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 23 +++
1 fi
Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 92cbffd7c6..7d50dd54f6 100644
To be called from tcg generated code on hosts that support
unaligned accesses natively, in response to an access that
is supposed to be aligned.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg-ldst.h | 5 +
accel/tcg/user-exec.c | 11 +++
2 files ch
The printf should have been qemu_log_mask, the parameters
themselves no longer compile, and because this is placed
before unwinding the PC is actively wrong.
We get better (and correct) logging on the other side of
raising the exception, in sparc_cpu_do_interrupt.
Reviewed-by: Mark Cave-Ayland
R
The fallback code in cpu_loop_exit_sigsegv is sufficient for
openrisc linux-user.
This makes all of the code in mmu.c sysemu only, so remove
the ifdefs and move the file to openrisc_softmmu_ss.
Remove the code from cpu_loop that handled EXCP_DPF.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by
We ought to have been recording the virtual address for reporting
to the guest trap handler.
Cc: Yoshinori Sato
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sh4/op_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/sh4/op_helper.c b/targ
We ought to have been recording the virtual address for reporting
to the guest trap handler. Move the function to mmu_helper.c, so
that we can re-use code shared with get_physical_address_data.
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
target/sparc/ldst_helper.c | 13 -
We will raise SIGBUS directly from cpu_loop_exit_sigbus.
Signed-off-by: Richard Henderson
---
linux-user/ppc/cpu_loop.c | 8
1 file changed, 8 deletions(-)
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index 840b23736b..483e669300 100644
--- a/linux-user/ppc/cpu_lo
This is not used by, nor required by, user-only.
Signed-off-by: Richard Henderson
---
target/ppc/internal.h| 8 +++-
target/ppc/excp_helper.c | 8 +++-
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 339974b7d8..6aa9
Not sure why the user-only code wasn't rewritten to use
probe_access_flags at the same time that the sysemu code
was converted. For the purpose of user-only, this is an
exact replacement.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 18 +-
1 file changed,
We ought to have been recording the virtual address for reporting
to the guest trap handler.
Cc: qemu-...@nongnu.org
Reviewed-by: Warner Losh
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/ppc/excp_helper.c | 14 ++
1 file changed, 14 insertions(+)
diff --g
Because of the complexity of setting ESR, re-use the existing
arm_cpu_do_unaligned_access function. This means we have to
handle the exception ourselves in cpu_loop, transforming it
to the appropriate signal.
Signed-off-by: Richard Henderson
---
target/arm/internals.h| 2 ++
linux-user
Record DAR, DSISR, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
This is exactly what the user-mode ppc_cpu_tlb_fill does,
so simply rename it as ppc_cpu_record_sigsegv.
Reviewed-by: Philippe Mathieu-Daudé
Sig
This is a new interface to be provided by the os emulator for
raising SIGBUS on fault. Use the new record_sigbus target hook.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 14 ++
linux-user/signal.c | 14 ++
2 files changed, 28 insertions(+)
diff --
By doing this while sending the exception, we will have already
done the unwinding, which makes the ppc_cpu_do_unaligned_access
code a bit cleaner.
Update the comment about the expected instruction format.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/ppc/excp_helper.c
Record trap_arg{0,1,2} for the linux-user signal frame.
Raise SIGBUS directly from cpu_loop_exit_sigbus, which means
we can remove the code for EXCP_UNALIGN in cpu_loop.
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 8 +---
linux-user/alpha/cpu_loop.c | 7 ---
tar
The kernel vectors both of these through unhandled_exception, which
results in force_sig(SIGSEGV). This isn't very useful for userland
when enabling overflow traps or fpu traps, but c'est la vie.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
linux-user/openrisc/cpu_loop.c |
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
Despite a comment saying why cpu_common_props cannot be placed in
a file that is compiled once, it was moved anyway. Revert that.
Since then, Property is not defined in hw/core/cpu.h, so it is now
easier to declare a function to insta
We have replaced tlb_fill with record_sigsegv for user mode.
Move the declaration to restrict it to system emulation.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 22 ++
linux-user/signal.c | 3 ---
2 fil
The fallback code in cpu_loop_exit_sigsegv is sufficient
for microblaze linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 8
linux-user/microblaze/cpu_loop.c | 10 --
targe
The fallback code in cpu_loop_exit_sigsegv is sufficient
for sh4 linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Signed-off-by: Richard Henderson
---
target/sh4/cpu.h | 6 +++---
linux-user/sh4/cpu_loop.c | 8
target/sh4/cpu.c | 2 +-
target/sh4/helper.
The fallback code in cpu_loop_exit_sigsegv is sufficient
for xtensa linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Acked-by: Max Filippov
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/xtensa/cpu.h | 2 +-
linux-user/xtensa/cpu_loop.c
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hppa linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
This makes all of the code in mem_helper.c sysemu only,
so remove the ifdefs and move the file to hppa_softmmu_ss.
Signed-off-by: Richard Henderson
---
target/hppa/cp
Record cr2, error_code, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
Use the maperr parameter to properly set PG_ERROR_P_MASK.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Rich
The fallback code in cpu_loop_exit_sigsegv is sufficient
for cris linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
This makes all of the code in helper.c sysemu only, so remove the
ifdefs and move the file to cris_softmmu_ss.
Reviewed-by: Philippe Mathieu-Daudé
The fallback code in cpu_loop_exit_sigsegv is sufficient
for sparc linux-user.
This makes all of the code in mmu_helper.c sysemu only, so remove
the ifdefs and move the file to sparc_softmmu_ss. Remove the code
from cpu_loop that handled TT_DFAULT and TT_TFAULT.
Cc: Mark Cave-Ayland
Reviewed-by
Move the masking of the address from cpu_loop into
s390_cpu_record_sigsegv -- this is governed by hw, not linux.
This does mean we have to raise our own exception, rather
than return to the fallback.
Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING.
Use the appropriate si_code for ea
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hexagon linux-user.
Remove the code from cpu_loop that raises SIGSEGV.
Reviewed-by: Taylor Simpson
Signed-off-by: Richard Henderson
---
linux-user/hexagon/cpu_loop.c | 24 +---
target/hexagon/cpu.c | 23 -
Record trap_arg{0,1,2} for the linux-user signal frame.
Fill in the stores to trap_arg{1,2} that were missing
from the previous user-only alpha_cpu_tlb_fill function.
Use maperr to simplify computation of trap_arg1.
Remove the code for EXCP_MMFAULT from cpu_loop, as
that part is now handled by cp
Use the new os interface for raising the exception,
rather than calling arm_cpu_tlb_fill directly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/mte_helper.c b
The fallback code in cpu_loop_exit_sigsegv is sufficient
for mips linux-user.
This means we can remove tcg/user/tlb_helper.c entirely.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/tcg-internal.h|
The fallback code in cpu_loop_exit_sigsegv is sufficient
for riscv linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/riscv/cpu_loop.c | 7 ---
target/riscv/cpu.c
Do not read 4 bytes before we determine the size of the insn.
Simplify triple switches in favor of checking major opcodes.
Include the missing cases of compact fsd and fsdsp.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/riscv/host-signal.h | 83 ++--
The fallback code in cpu_loop_exit_sigsegv is sufficient
for m68k linux-user.
Remove the code from cpu_loop that handled EXCP_ACCESS.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 10 --
target/m68k/cpu.c | 2 +-
target/
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/riscv/host-signal.h | 85 +-
accel/tcg/user-exec.c | 134
2 files changed, 84 insertions(
Because the linux-user kuser page handling is currently implemented
by detecting magic addresses in the unnamed 0xaa trap, we cannot
simply remove nios2_cpu_tlb_fill and rely on the fallback code.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h| 6
The named function no longer exists.
Refer to host_signal_handler instead.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index dab5f1d1cd..07be55b7e1 100644
--- a/
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/s390/host-signal.h | 93 -
linux-user/host/s390x/host-signal.h | 2 +-
accel/tcg/user-exec.c | 88 +
Because of the complexity of setting ESR, continue to use
arm_deliver_fault. This means we cannot remove the code
within cpu_loop that decodes EXCP_DATA_ABORT and
EXCP_PREFETCH_ABORT.
But using the new hook means that we don't have to do the
page_get_flags check manually, and we'll be able to res
This is a new interface to be provided by the os emulator for
raising SIGSEGV on fault. Use the new record_sigsegv target hook.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 15 +++
accel/tcg/user-exec.c
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/alpha/host-signal.h | 41 +
accel/tcg/user-exec.c | 31 +-
2 files changed, 42 in
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson
---
linux-user/host/aarch64/host-signal.h | 74 -
accel/tcg/user-exec.c | 94 +--
Now that all of the linux-user hosts have been converted
to host-signal.h, drop the compatibility code.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 12
linux-user/signal.c | 14 --
2 fi
Add a new user-only interface for updating cpu state before
raising a signal. This will replace tlb_fill for user-only
and should result in less boilerplate for each guest.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 26 +
Add stub host-signal.h for all linux-user hosts.
Add new code replacing cpu_signal_handler.
Full migration will happen one host at a time.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/aarch64/host-
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson
---
linux-user/host/i386/host-signal.h | 25 -
linux-user/host/x32/host-signal.h| 2 +-
linux-user/host/x86_64/host-signal.h |
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/mips/host-signal.h | 62 +-
accel/tcg/user-exec.c | 52 +
2 files changed, 62
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
linux-user/host/ppc/host-signal.h | 25 -
linux-user/host/ppc64/host-signal.h | 2 +-
accel/tcg/use
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Drop the Solaris code as completely unused.
Signed-off-by: Richard Henderson
---
linux-user/host/sparc/host-signal.h | 54 ++-
linux-user/host/sparc64/
Currently there are only two places that require we reset this
value before exiting to the main loop, but that will change.
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 3 ++-
accel/tcg/user-exec.c | 2 --
2 files changed, 2 insertions(+), 3 deletions(-)
This is the major portion of handle_cpu_signal which is specific
to tcg, handling the page protections for the translations.
Most of the rest will migrate to linux-user/ shortly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Pass guest address to handle_sigsegv_acc
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/arm/host-signal.h | 30 -
accel/tcg/user-exec.c | 4
Remove the comment about siglongjmp. We do use sigsetjmp
in the main cpu loop, but we do not save the signal mask
as most exits from the cpu loop do not require them.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
Split out a function to adjust the raw signal pc into a
value that could be passed to cpu_restore_state.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Adjust pc in place; return MMUAccessType.
---
include/exec/exec-all.h | 10 ++
accel/tcg/user-exec.c |
The existing code for safe-syscall.inc.S will compile
without change for riscv32 and riscv64. We may also
drop the meson.build stanza that merges them for tcg/.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
configure
For v5, I've combined the sigsegv and sigbus patch sets, because
they're so very closely modelled. We've got user-only hooks named
record_sigsegv
record_sigbus
While the tlb_fill hook becomes sysemu only, the corresponding
do_unaligned_access hook was always sysemu only and stays that way.
在 2021/10/14 下午8:00, Eugenio Perez Martin 写道:
On Wed, Oct 13, 2021 at 5:27 AM Jason Wang wrote:
在 2021/10/1 下午3:05, Eugenio Pérez 写道:
Shadow virtqueue notifications forwarding is disabled when vhost_dev
stops, so code flow follows usual cleanup.
Also, host notifiers must be disabled at SVQ
On Thu, Oct 14, 2021 at 07:32:32PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> The value of XER is split in multiple fields of CPUPPCState, like
> env->xer and env->so. To get/set the whole register from gdb, we should
> use cpu_read_xer/cpu_write_xer.
>
> Fixes: da91a0
On Thu, Oct 14, 2021 at 07:32:31PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> We should use cpu_read_xer/cpu_write_xer to save/restore the complete
> register since some of its bits are in other fields of CPUPPCState. A
> test is added to prevent future regressions.
>
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