[PULL 15/26] target/riscv: Remove RVB (replaced by Zb[abcs])

From: Philipp Tomsich With everything classified as Zb[abcs] and pre-0.93 draft-B instructions that are not part of Zb[abcs] removed, we can remove the remaining support code for RVB. Note that RVB has been retired for good and misa.B will neither mean 'some' or 'all of' Zb*: https://lists.ris

[PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci

From: Philipp Tomsich The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and r

[PULL 06/26] target/riscv: Remove the W-form instructions from Zbs

From: Philipp Tomsich Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form instructions for Zbs (single-bit instructions). Remove them. Note that these instructions had already been removed for the 0.93 version of the draft-B extention and have not been present in the binutil

[PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic)

From: Philipp Tomsich Assume clzw being executed on a register that is not sign-extended, such as for the following sequence that uses (1ULL << 63) | 392 as the operand to clzw: bseti a2, zero, 63 addia2, a2, 392 clzwa3, a2 The correct result of clzw would be 23,

[PULL 09/26] target/riscv: Add instructions of the Zbc-extension

From: Philipp Tomsich The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich R

[PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension

From: Philipp Tomsich The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Acked-by: Bin Meng Message-id: 20210911140016.834071-9-philipp.toms...@vrull.eu Signed-of

[PULL 04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

From: Philipp Tomsich The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' pro

[PULL 01/26] target/riscv: Introduce temporary in gen_add_uw()

From: Philipp Tomsich Following the recent changes in translate.c, gen_add_uw() causes failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these regressions by introducing a temporary. Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Rich

[PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)

From: Philipp Tomsich The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-

[PULL 05/26] target/riscv: Reassign instructions to the Zba-extension

From: Philipp Tomsich The following instructions are part of Zba: - add.uw (RV64 only) - sh[123]add (RV32 and RV64) - sh[123]add.uw (RV64-only) - slli.uw (RV64-only) Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Acked-by: Bin Meng Message-id:

[PULL 02/26] target/riscv: fix clzw implementation to operate on arg1

From: Philipp Tomsich The refactored gen_clzw() uses ret as its argument, instead of arg1. Fix it. Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Message-id: 20210911140016.834071-3-philipp.toms...@vrull.eu Fixes: 60903915050

[PULL 00/26] riscv-to-apply queue

From: Alistair Francis The following changes since commit ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def: Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into staging (2021-10-06 12:11:14 -0700) are available in the Git repository at: g...@github.com:alistair23/qem

Re: [PATCH] generic-loader: remove the ram_size limit when a loading binary file

On Wed, Oct 6, 2021 at 10:04 PM Damien Hedde wrote: > > > > On 10/6/21 13:49, Philippe Mathieu-Daudé wrote: > > On 10/6/21 13:37, Damien Hedde wrote: > >> Right now, we cannot load some binary file if it is bigger than the > >> machine's ram size. This limitation only occurs when loading a > >> bi

Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR

On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak wrote: > > mconfigptr is an mandatory CSR as per the priv spec. %s/an/a as per the priv spec v1.12 > This csr holds the physical address of the configuration > data structure if this data structure is implemented > Its an readonly csr set to zero maki

Re: [PATCH] ACPI ERST: specification for ERST support

On Wed, 6 Oct 2021, Eric DeVolder wrote: > > > On 10/6/21 2:00 AM, Ani Sinha wrote: > > > > > > On Wed, 6 Oct 2021, Ani Sinha wrote: > > > > > From: Eric DeVolder > > > > > > > --- > > > > docs/specs/acpi_erst.txt | 147 +++ > > > > 1 file changed, 147 insert

Re: [PATCH v12 16/16] machine: Make smp_parse return a boolean

On 2021/10/2 19:27, Markus Armbruster wrote: Paolo Bonzini writes: On 01/10/21 19:15, Daniel P. Berrangé wrote: On Fri, Oct 01, 2021 at 07:08:51PM +0200, Paolo Bonzini wrote: On 29/09/21 04:58, Yanan Wang wrote: @@ -933,8 +935,7 @@ static void machine_set_smp(Object *obj, Visitor *v, cons

[PATCH v7 5/8] hw/acpi/aml-build: Add PPTT table

From: Andrew Jones Add the Processor Properties Topology Table (PPTT) used to describe CPU topology information to ACPI guests. Note, a DT-boot Linux guest with a non-flat CPU topology will see socket and core IDs being sequential integers starting from zero, which is different from ACPI-boot Li

[PATCH v7 8/8] tests/data/acpi/virt: Update binary files for PPTT

Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory to update PPTT binary. Also empty bios-tables-test-allowed-diff.h. Disassembled output of the updated new files: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180810 (64-bit version) * Copyright (c) 2

[PATCH v7 3/8] hw/arm/virt: Add cpu-map to device tree

From: Andrew Jones Support device tree CPU topology descriptions. In accordance with the Devicetree Specification, the Linux Doc "arm/cpus.yaml" requires that cpus and cpu nodes in the DT are present. And we have already met the requirement by generating /cpus/cpu@* nodes for members within ms->

[PATCH v7 7/8] hw/arm/virt-acpi-build: Generate PPTT table

Generate PPTT table for Arm virt machines. Signed-off-by: Yanan Wang --- hw/arm/virt-acpi-build.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6cec97352b..658a0a5d39 100644 --- a/hw/arm/virt-acpi-build.c +++

[PATCH v7 6/8] tests/data/acpi/virt: Add empty binary files for PPTT

Add empty binary files for the new introduced PPTT table under tests/data/acpi/virt, and list them as files to be changed in tests/qtest/bios-tables-test-allowed-diff.h Signed-off-by: Yanan Wang --- tests/data/acpi/virt/PPTT | 0 tests/data/acpi/virt/PPTT.memhp | 0

[PATCH v7 4/8] hw/acpi/aml-build: Add Processor hierarchy node structure

Add a generic API to build Processor hierarchy node structure (Type 0), which is strictly consistent with descriptions in ACPI 6.2: 5.2.29.1. This function will be used to build ACPI PPTT table for cpu topology. Co-developed-by: Ying Fang Co-developed-by: Henglong Fan Co-developed-by: Yanan Wan

[PATCH v7 1/8] hw/arm/virt: Only describe cpu topology since virt-6.2

On existing older machine types, without cpu topology described in ACPI or DT, the guest will populate one by default. With the topology described, it will read the information and set up its topology as instructed, but that may not be the same as what was getting used by default. It's possible tha

[PATCH v7 0/8] hw/arm/virt: Introduce cpu topology support

Hi, This is a new version rebased on top of master (commit ca61fa4b80). Since both the SMP parsing improvement patchset and the ACPI refactoring patchset have been merged into master, now it's a proper time to respin this series which had some dependency on them. Thanks for reviewing. Description

[PATCH v7 2/8] device_tree: Add qemu_fdt_add_path

qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it also adds all missing subnodes from the given path. We'll use it in a coming patch where we will add cpu-map to the device tree. And we also tweak an error message of qemu_fdt_add_subnode(). Cc: David Gibson Cc: Alistair Francis C

Re: [PATCH v3 02/15] target/ppc: add user write access control for PMU SPRs

On Mon, Sep 27, 2021 at 08:05:22PM -0300, Daniel Henrique Barboza wrote: > > > On 9/27/21 02:08, David Gibson wrote: > > On Thu, Sep 23, 2021 at 11:39:14AM -0300, Daniel Henrique Barboza wrote: > > > > > > > > > On 9/6/21 22:38, David Gibson wrote: > > > > On Fri, Sep 03, 2021 at 05:31:03PM -03

Re: Rust in Qemu BoF followup 2: Rust toolchain availability

On Thu, Sep 30, 2021 at 11:45:11AM +0100, Daniel P. Berrangé wrote: > On Thu, Sep 30, 2021 at 11:59:42AM +1000, David Gibson wrote: > > Hi again all, > > > > I've now done.. or at least started... the second part of my followup > > from the KVM Forum BoF on Rust in Qemu. > > > > I've extended the

Re: [PATCH] spapr/xive: Use xive_esb_rw() to trigger interrupts

On Wed, Oct 06, 2021 at 11:05:46PM +0200, Cédric Le Goater wrote: > xive_esb_rw() is the common routine used for memory accesses on ESB > page. Use it for triggers also. > > Signed-off-by: Cédric Le Goater Applied to ppc-fot-6.2, thanks. > --- > hw/intc/spapr_xive_kvm.c | 4 +--- > 1 file chan

Re: [PATCH] hw/ppc: Fix iothread locking in the 405 code

On Wed, Oct 06, 2021 at 09:11:40AM +0200, Thomas Huth wrote: > When using u-boot as firmware with the taihu board, QEMU aborts with > this assertion: > > ERROR:../accel/tcg/tcg-accel-ops.c:79:tcg_handle_interrupt: assertion failed: > (qemu_mutex_iothread_locked()) > > Running QEMU with "-d in_

Re: [PATCH] hw/ppc/spapr_softmmu: Reduce include list

On Wed, Oct 06, 2021 at 07:08:01PM +0200, Philippe Mathieu-Daudé wrote: > Commit 962104f0448 ("hw/ppc: moved hcalls that depend on softmmu") > introduced a lot of unnecessary #include directives. Remove them. Applied to ppc-for-6.2, thanks. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/

Re: [PATCH v2 2/2] target/riscv: Use dup_const_tl in orc.b to legalise truncation of constant

On Mon, Oct 4, 2021 at 7:44 AM Philipp Tomsich wrote: > > We need to use the newly introduced dup_const_tl in orc.b to legalise > the truncation (to target_long) of the constant generated with dup_const. > > Signed-off-by: Philipp Tomsich > Reviewed-by: Richard Henderson Thanks, I have applied

Re: [PATCH v2 2/2] target/riscv: Use dup_const_tl in orc.b to legalise truncation of constant

On Mon, Oct 4, 2021 at 7:44 AM Philipp Tomsich wrote: > > We need to use the newly introduced dup_const_tl in orc.b to legalise > the truncation (to target_long) of the constant generated with dup_const. > > Signed-off-by: Philipp Tomsich > Reviewed-by: Richard Henderson Reviewed-by: Alistair F

Re: [PATCH v4 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only

On Thu, Oct 7, 2021 at 4:12 AM Richard Henderson wrote: > > The fallback code in cpu_loop_exit_sigsegv is sufficient > for riscv linux-user. > > Remove the code from cpu_loop that raised SIGSEGV. > > Cc: qemu-ri...@nongnu.org > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Richard Henderso

Re: [PATCH v4 17/41] linux-user/host/riscv: Improve host_signal_write

On Thu, Oct 7, 2021 at 3:37 AM Richard Henderson wrote: > > Do not read 4 bytes before we determine the size of the insn. > Simplify triple switches in favor of checking major opcodes. > Include the missing cases of compact fsd and fsdsp. > > Cc: qemu-ri...@nongnu.org > Signed-off-by: Richard Hend

Re: [PATCH v4 15/41] linux-user/host/riscv: Populate host_signal.h

On Thu, Oct 7, 2021 at 3:31 AM Richard Henderson wrote: > > Split host_signal_pc and host_signal_write out of user-exec.c. > > Cc: qemu-ri...@nongnu.org > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > linux-user/host/riscv/host-signal.h | 85 +++

[PATCH v2 24/27] target/riscv: modification of the trans_csrxx for 128-bit support

As opposed to the gen_arith and gen_shift generation helpers, the csr insns do not have a common prototype, so the choice to generate 32/64 or 128-bit helper calls is done in the trans_csrxx functions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/tran

[PATCH v2 26/27] target/riscv: adding 128-bit access functions for some csrs

Access to mstatus, mtvec, mscratch and mepc is implemented. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 111 ++-- 2 files changed, 108 insertions(+), 4 deletions(-) diff --git a/

[PATCH v2 27/27] target/riscv: support for 128-bit satp

Support for a 128-bit satp. This is a bit more involved than necessary because we took the opportunity to increase the page size to 16kB, and change the page table geometry, which makes the page walk a bit more parametrizable (variables instead of defines). Note that is anyway a necessary step for

[PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift

Support for the base shift instructions working on 128-bit registers. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/trans_rvi.c.inc | 224 ++-- 1 file changed, 209 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v2 22/27] target/riscv: adding high part of some csrs

Adding the high part of a minimal set of csr. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 81cbd77d09..a2d7d65efb 100644 --- a/target/ri

[PATCH v2 25/27] target/riscv: actual functions to realize crs 128-bit insns

The csrs are accessed through function pointers: we set-up the table for the 128-bit accesses, make the stub a function that does what it should, and implement basic accesses on read-only csrs. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 16 + targ

[PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns

Given the side effects they have, the csr instructions are realized as helpers. We extend this existing infrastructure for 128-bit sized csr. We have a slight issue with returning 128-bit values: we use the globals we added to support div/rem insns to that end. Theses helpers all call a unique func

[PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic

The RISCV ISA is such that the arithmetic and logic instructions have the same opcode, irrelevant of the base register size. So, for all arithmetic and logic insns existing for the 3 register sizes, excluding shifts, this patch adds the support for the 128-bit computations. Signed-off-by: Frédéric

[PATCH v2 21/27] target/riscv: div and rem insns on 128-bit

Given the complexity of the implementation of these instructions, we call helpers to produce their behavior. From an implementation standpoint, we ended up by adding two more tcg globals to return the 128-bit result in a wrapper that itself is called by gen_arith. Signed-off-by: Frédéric Pétrot C

[PATCH v2 20/27] target/riscv: addition of the 'd' insns for 128-bit mult/div/rem

All mult/div/rem instructions that work on double integers (suffixed 'd') can be tcg-generated in a few micro-ops, they are added here. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvm.c.inc | 11

[PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers

The code generation helpers are now able to handle also the 128-bit functions, although no such function exists yet. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 102 +-- 1 file changed, 88 insertions(+), 14 dele

[PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions

The ISA adds the addid, addd and subd instructions that work on 64-bit while in 128-bit mode. Similarly to what is done for insns working on 32-bit (w suffix), we set a 'd' flag so that masking and sign extension occurs as it should when using the registers' accessors. Signed-off-by: Frédéric Pétr

[PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns

We deal here with the multiplication part of the M extension as, although a bit complex, the code is generated inline, as opposed to division and remainder that resort to helpers (to come soon). Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/trans_rvm.c

[PATCH v2 10/27] target/riscv: adding accessors to the registers upper part

Set and get functions to access the 64 top bits of the register, stored in the gprh field of the cpu state. It looks as if the access to the gprh field can not be protected to make sure it is accessed only in the 128-bit version of the processor because the misa/misah field is writable (as it shoul

[PATCH v2 16/27] target/riscv: support for 128-bit loads and store

The 128-bit ISA adds ldu, lq and sq. We provide here support for these instructions. Note that although we compute a 128-bit address, we only use the lower 64-bit to actually address memory, cowardly utilizing the existing address translation mechanism of QEMU. Signed-off-by: Frédéric Pétrot Co-a

[PATCH v2 07/27] target/riscv: refactoring calls to gen_arith

gen_arith now takes three functions instead of one as arguments, one for each register size. All call sites changed to use this refactored version, without yet supporting sizes other than 32 and 64. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c

[PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions

All variations of shifts on 64-bit values are available in the 128-bit ISA, so we add them now. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 10 + target/riscv/translate.c| 4 +- target/riscv/insn_trans/trans_rvi

[PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers

The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 3 +++ target/riscv/translate.c | 6 +- 2 files changed, 8 insert

[PATCH v2 12/27] target/riscv: moving some insns close to similar insns

lwu and ld are functionally close to the other loads, but were after the stores in the source file. Similarly, xor was away from or and and by two arithmetic functions, while the immediate versions were nicely put together. This patch moves the aforementioned loads after lhu, and xor above or, wher

[PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers

Introduction of a gen_logic function for bitwise logic to implement instructions in which not propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c

[PATCH v2 13/27] target/riscv: rename a few gen function helpers

Add the tl suffix to the existing integer gen_xxx functions that apply to target_long types for which a 128-bit version will also exist, so that it is immediately visible which function is for which type(s). Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_tran

[PATCH v2 05/27] target/riscv: additional macros to check instruction support

Given that the 128-bit version of the riscv spec adds new instructions, and that some instructions that were previously only available in 64-bit mode are now available for both 64-bit and 128-bit, we added new macros to check for the processor mode during translation. Signed-off-by: Frédéric Pétro

[PATCH v2 01/27] memory: add a few defines for octo (128-bit) values

Introducing unsigned quad, signed quad, and octo accesses types to handle load and store by 128-bit processors. This is just a small addition to Richard's patch not yet upstreamed https://lore.kernel.org/qemu-devel/20210818191920.390759-24-richard.hender...@linaro.org/ Note that the patch must be a

[PATCH v2 08/27] target/riscv: refactoring calls to gen_shift

As for arithmetic operations, we now pass functions pointers to deal with 32, 64 and 128-bit shift operations, and to change all call sites accordingly. For now, 128-bit operations are still not handled. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c

[PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles

This patch is kind of a mess because several files have to be slightly modified to allow for a new target. Most of these modifications have to deal with changing what was a binary choice into a ternary one. Although we did our best to avoid testing for TARGET_RISCV128 (which we did), it is implici

[PATCH v2 00/27] Adding partial support for 128-bit riscv target

This series of patches provides partial 128-bit support for the riscv target architecture. Feedback on v1 was most useful and led to many improvements. + the load and store make use of a not yet upstreamed patch from Richard, + use of the existing Int128 computations in helpers, and addition of a

[PATCH v2 03/27] target/riscv: adding upper 64 bits for misa

Addition of misah, upper part of misa in the 128-bit extension. This is required for the is_64bit and is_128bit macros that we introduce in addition to the existing is_32bit one to know which register size the processor uses. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- targ

[PATCH v2 02/27] Int128.h: addition of a few 128-bit operations

Addition of not, xor, div and rem on 128-bit integers, used in particular within div/rem and csr helpers for computations on 128-bit registers. These will be used by the 128-bit riscv version. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- include/qemu/int128.h | 264 +

Re: [PATCH v5 08/13] job: Add job_cancel_requested()

On Wed, Oct 06, 2021 at 05:19:35PM +0200, Hanna Reitz wrote: > Most callers of job_is_cancelled() actually want to know whether the job > is on its way to immediate termination. For example, we refuse to pause > jobs that are cancelled; but this only makes sense for jobs that are > really actually

Re: [PATCH v5 07/13] job: Do not soft-cancel after a job is done

On Wed, Oct 06, 2021 at 05:19:34PM +0200, Hanna Reitz wrote: > The only job that supports a soft cancel mode is the mirror job, and in > such a case it resets its .cancelled field before it leaves its .run() > function, so it does not really count as cancelled. > > However, it is possible to cance

Re: [PATCH v2 08/12] macfb: add common monitor modes supported by the MacOS toolbox ROM

Le 06/10/2021 à 21:24, Laurent Vivier a écrit : > Le 06/10/2021 à 18:09, Mark Cave-Ayland a écrit : >> On 06/10/2021 16:46, Laurent Vivier wrote: >>> Le 06/10/2021 à 15:54, Mark Cave-Ayland a écrit : On 06/10/2021 13:24, Laurent Vivier wrote: >> This is where it becomes a bit trickier

Re: [PATCH] hw/elf_ops.h: switch to ssize_t for elf loader return type

On 10/6/21 21:28, Luc Michel wrote: > Until now, int was used as the return type for all the ELF > loader related functions. The returned value is the sum of all loaded > program headers "MemSize" fields. > > Because of the overflow check in elf_ops.h, trying to load an ELF bigger > than INT_MAX w

[PATCH] spapr/xive: Use xive_esb_rw() to trigger interrupts

xive_esb_rw() is the common routine used for memory accesses on ESB page. Use it for triggers also. Signed-off-by: Cédric Le Goater --- hw/intc/spapr_xive_kvm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 630a71

Re: [PATCH v4 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE

On Wed, Oct 06, 2021 at 10:22:58AM -0700, Richard Henderson wrote: > The kernel vectors both of these through unhandled_exception, which > results in force_sig(SIGSEGV). This isn't very useful for userland > when enabling overflow traps or fpu traps, but c'est la vie. Thanks for looking into it.

Re: [PATCH v3 14/22] target/i386/sev: Move qmp_query_sev_attestation_report() to sev.c

On 10/4/21 10:23, Paolo Bonzini wrote: > On 02/10/21 14:53, Philippe Mathieu-Daudé wrote: >> Move qmp_query_sev_attestation_report() from monitor.c to sev.c >> and make sev_get_attestation_report() static. We don't need the >> stub anymore, remove it. >> >> Signed-off-by: Philippe Mathieu-Daudé >

Re: [PULL 0/3] Hexagon (target/hexagon) update

/pull-hex-20211006 for you to fetch changes up to 23803bbe524c34d5725508f169a0a23f652e6584: target/hexagon: Use tcg_constant_* (2021-10-06 10:29:56 -0500) Change from Philippe - Use tcg_constant_* Change from Philippe - Remove unused

Re: [PATCH 12/12] block-backend: drop INT_MAX restriction from blk_check_byte_request()

On Wed, Oct 06, 2021 at 03:17:18PM +0200, Vladimir Sementsov-Ogievskiy wrote: > blk_check_bytes_request is called from blk_co_do_preadv, > blk_co_do_pwritev_part, blk_co_do_pdiscard and blk_co_copy_range > before (maybe) calling throttle_group_co_io_limits_intercept() (which > has int64_t argument)

Re: [PATCH v3 22/22] MAINTAINERS: Cover AMD SEV files

On 10/4/21 10:27, Paolo Bonzini wrote: > On 02/10/21 14:53, Philippe Mathieu-Daudé wrote: >> Add an entry to list SEV-related files. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   MAINTAINERS | 7 +++ >>   1 file changed, 7 insertions(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >>

Re: [PATCH 11/12] block-backend: blk_pread, blk_pwrite: rename count parameter to bytes

On Wed, Oct 06, 2021 at 03:17:17PM +0200, Vladimir Sementsov-Ogievskiy wrote: > To be consistent with declarations in include/sysemu/block-backend.h. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- > block/block-backend.c | 16 > 1 file changed, 8 insertions(+), 8 deletion

Re: [PATCH 10/12] block-backend: convert blk_aio_ functions to int64_t bytes paramter

On Wed, Oct 06, 2021 at 03:17:16PM +0200, Vladimir Sementsov-Ogievskiy wrote: > 1. Convert bytes in BlkAioEmAIOCB: > aio->bytes is only passed to already int64_t interfaces, and set in > blk_aio_prwv, which is updated here. > > 2. For all updated functions parameter type becomes wider so calle

Re: [PATCH v6 02/10] ACPI ERST: specification for ERST support

On 10/6/21 3:12 AM, Michael S. Tsirkin wrote: On Thu, Aug 05, 2021 at 06:30:31PM -0400, Eric DeVolder wrote: Information on the implementation of the ACPI ERST support. Signed-off-by: Eric DeVolder --- docs/specs/acpi_erst.txt | 147 +++ 1 file

Re: [PATCH] ACPI ERST: specification for ERST support

On 10/6/21 2:00 AM, Ani Sinha wrote: On Wed, 6 Oct 2021, Ani Sinha wrote: From: Eric DeVolder --- docs/specs/acpi_erst.txt | 147 +++ 1 file changed, 147 insertions(+) create mode 100644 docs/specs/acpi_erst.txt OK it did not come out the way I want

Re: [PATCH 09/12] block-backend: convert blk_co_copy_range to int64_t bytes

On Wed, Oct 06, 2021 at 03:17:15PM +0200, Vladimir Sementsov-Ogievskiy wrote: > Function is updated so that parameter type becomes wider, so all > callers should be OK with it. > > Look at blk_co_copy_range() itself: bytes passed only to > blk_check_byte_request() and bdrv_co_copy_range(), which a

[PATCH] hw/elf_ops.h: switch to ssize_t for elf loader return type

Until now, int was used as the return type for all the ELF loader related functions. The returned value is the sum of all loaded program headers "MemSize" fields. Because of the overflow check in elf_ops.h, trying to load an ELF bigger than INT_MAX will fail. Switch to ssize_t to remove this limit

Re: [PATCH v2 08/12] macfb: add common monitor modes supported by the MacOS toolbox ROM

Le 06/10/2021 à 18:09, Mark Cave-Ayland a écrit : > On 06/10/2021 16:46, Laurent Vivier wrote: >> Le 06/10/2021 à 15:54, Mark Cave-Ayland a écrit : >>> On 06/10/2021 13:24, Laurent Vivier wrote: >>> > This is where it becomes a bit trickier, since technically booting Linux > with -kernel y

Re: [PATCH 16/16] tests/acceptance/ppc_prep_40p.py: unify tags

On Wed, Oct 6, 2021 at 4:17 PM Willian Rampazzo wrote: > > On Fri, Sep 24, 2021 at 4:01 PM Cleber Rosa wrote: > > > > The arch and machine tags apply to all tests, so let's define them > > only once. > > > > Signed-off-by: Cleber Rosa > > --- > > tests/acceptance/ppc_prep_40p.py | 12 --

Re: [PATCH 16/16] tests/acceptance/ppc_prep_40p.py: unify tags

On Fri, Sep 24, 2021 at 4:01 PM Cleber Rosa wrote: > > The arch and machine tags apply to all tests, so let's define them > only once. > > Signed-off-by: Cleber Rosa > --- > tests/acceptance/ppc_prep_40p.py | 12 > 1 file changed, 4 insertions(+), 8 deletions(-) > Reviewed-by: Will

Re: [PATCH 13/16] tests/acceptance/boot_xen.py: use class attribute

On Fri, Sep 24, 2021 at 3:59 PM Cleber Rosa wrote: > > Rather than defining a single use variable, let's just use the class > attribute directly. > > Signed-off-by: Cleber Rosa > --- > tests/acceptance/boot_xen.py | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > Reviewed-by: Willian

Re: [PATCH 09/16] tests/acceptance/boot_xen.py: merge base classes

On Fri, Sep 24, 2021 at 3:58 PM Cleber Rosa wrote: > > While it's a good practice to have reusable base classes, in this > specific case there's no other user of the BootXenBase class. > > By unifying the class used in this test, we can improve readability > and have the opportunity to add some fu

Re: [PATCH 10/16] tests/acceptance/boot_xen.py: unify tags

On Fri, Sep 24, 2021 at 3:58 PM Cleber Rosa wrote: > > Because all tests share the same tags, it's possible to have all of > them at the class level. > > Signed-off-by: Cleber Rosa > --- > tests/acceptance/boot_xen.py | 26 +- > 1 file changed, 5 insertions(+), 21 deletio

Re: [PATCH 11/16] tests/acceptance/boot_xen.py: fetch kernel during test setUp()

On Fri, Sep 24, 2021 at 3:59 PM Cleber Rosa wrote: > > The kernel is a common blob used in all tests. By moving it to the > setUp() method, the "fetch asset" plugin will recognize the kernel and > attempt to fetch it and cache it before the tests are started. > > Signed-off-by: Cleber Rosa > ---

Re: [PATCH v3 13/22] target/i386/sev: Remove stubs by using code elision

On 10/4/21 10:19, Paolo Bonzini wrote: > On 02/10/21 14:53, Philippe Mathieu-Daudé wrote: >> Only declare sev_enabled() and sev_es_enabled() when CONFIG_SEV is >> set, to allow the compiler to elide unused code. Remove unnecessary >> stubs. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   i

Re: [PATCH 03/16] Acceptance Tests: add mechanism for listing tests

On Fri, Sep 24, 2021 at 3:57 PM Cleber Rosa wrote: > > It is helpful to know the tests that would be executed with a "make > check-acceptance" without executing them. Let's introduce a "make > list-acceptance" rule for that purpose. > > Signed-off-by: Cleber Rosa > --- > tests/Makefile.include

Re: [PULL 00/28] tcg patch queue

/qemu.git tags/pull-tcg-20211006 for you to fetch changes up to ea3f2af8f1b87d7bced9b75ef2e788b66ec49961: tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec (2021-10-05 16:53:17 -0700) More fixes for fedora-i386-cross Add dup_const_tl Expand

Re: [PATCH 01/16] Acceptance Tests: bump Avocado requirement to 91.0

On Fri, Sep 24, 2021 at 3:57 PM Cleber Rosa wrote: > > Avocado 91.0, brings, among other changes, a switch to a new runner > implementation, known as "nrunner". While my personal testing shows > that it's suitable for running the QEMU tests, there are some > considerations that should be addresse

Re: [Virtio-fs] [PATCH 12/13] virtiofsd: Implement blocking posix locks

On Wed, Oct 06, 2021 at 05:34:59PM +0200, Christophe de Dinechin wrote: > > On 2021-09-30 at 11:30 -04, Vivek Goyal wrote... > > As of now we don't support fcntl(F_SETLKW) and if we see one, we return > > -EOPNOTSUPP. > > > > Change that by accepting these requests and returning a reply > > immed

[PATCH] target/sh4: Split user/system helpers

cpu_sh4_is_cached() is the single user-emulation helper: move the function to its own file and simplify the #ifdef'ry. Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <20211006172307.780893-1-richard.hender...@linaro.org> --- target/sh4/{helper.c => helper_system.c} | 15 + targe

[PATCH v4 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for riscv linux-user. Remove the code from cpu_loop that raised SIGSEGV. Cc: qemu-ri...@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 --- target/riscv/cpu.c

[PATCH v4 36/41] target/s390x: Use probe_access_flags in s390_probe_access

Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Cc: qemu-s3...@nongnu.org Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 18 +

[PATCH v4 34/41] target/ppc: Implement ppc_cpu_record_sigsegv

Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Philippe Mathieu-Daudé Sig

[PATCH v4 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for openrisc linux-user. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by

Re: [Virtio-fs] [PATCH 11/13] virtiofsd: Shutdown notification queue in the end

On Wed, Oct 06, 2021 at 05:15:57PM +0200, Christophe de Dinechin wrote: > > On 2021-09-30 at 11:30 -04, Vivek Goyal wrote... > > So far we did not have the notion of cross queue traffic. That is, we > > get request on a queue and send back response on same queue. So if a > > request be being proc

[PATCH v4 29/41] target/microblaze: Make mb_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for microblaze linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 8 linux-user/microblaze/cpu_loop.c

Re: [PULL 12/12] meson: show library versions in the summary

On 10/6/21 19:16, Paolo Bonzini wrote: > On 06/10/21 18:55, Philippe Mathieu-Daudé wrote: >> So something doesn't work, because my system has 0.59.1 and it is used >> instead of the submodule... > > How do you run "./configure"?  If you passed explicitly > "--meson=/usr/bin/meson" or something lik

[PATCH v4 40/41] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for xtensa linux-user. Remove the code from cpu_loop that raised SIGSEGV. Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c

  1   2   3   4   >