Hi Markus,
On Mon, Sep 27, 2021 at 2:51 PM Markus Armbruster wrote:
>
> Bin Meng writes:
>
> > GCC seems to be strict about processing pattern like "!!for & bar".
> > When 'bar' is not 0 or 1, it complains with -Werror=parentheses:
> >
> > suggest parentheses around operand of ‘!’ or change ‘&
Bin Meng writes:
> GCC seems to be strict about processing pattern like "!!for & bar".
> When 'bar' is not 0 or 1, it complains with -Werror=parentheses:
>
> suggest parentheses around operand of ‘!’ or change ‘&’ to ‘&&’ or ‘!’ to
> ‘~’ [-Werror=parentheses]
>
> Add a () around "foo && bar",
Hi Philippe,
On Mon, Sep 27, 2021 at 12:47 PM Philippe Mathieu-Daudé wrote:
>
> On 9/27/21 04:21, Bin Meng wrote:
> > GCC seems to be strict about processing pattern like "!!for & bar".
> > When 'bar' is not 0 or 1, it complains with -Werror=parentheses:
> >
> > suggest parentheses around opera
On 25/09/2021 18:01, Philippe Mathieu-Daudé wrote:
On 9/25/21 17:32, Richard Henderson wrote:
On 9/25/21 11:27 AM, Philippe Mathieu-Daudé wrote:
+static bool qtest_cpu_has_work(CPUState *cpu)
+{
+ g_assert_not_reached();
+}
Sigh, this triggers:
Running test qtest-i386/cpu-plug-test
**
ERR
On 9/24/21 13:24, Paolo Bonzini wrote:
> From: Sean Christopherson
>
> EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
Typo "Enclave Page Cache".
> SGX (Software Guard Extensions). The SDM desribes EPC as:
>
> The Enclave Page Cache (EPC) is the secure storage used t
On Fri, Sep 24, 2021 at 08:56:40AM -0500, Eric Blake wrote:
> On Fri, Sep 24, 2021 at 01:24:47PM +0200, Paolo Bonzini wrote:
> > From: Yang Zhong
> >
> > Add the new 'memory-backend-epc' user creatable QOM object in
> > the ObjectOptions to support SGX since v6.1, or the sgx backend
> > object ca
From: Klaus Jensen
Add a new experimental 'x-nvme-ctrl' device which allows us to get rid
of a bunch of legacy options and slightly change others to better use
the qdev property system.
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 137 +++
hw/n
On 9/27/21 01:06, Richard Henderson wrote:
> On 9/26/21 5:39 PM, Philippe Mathieu-Daudé wrote:
>> The tcg_target_call_clobber_regs variable is of type TCGRegSet,
>> which is unsigned and might be 64-bit wide. By initializing it
>> as unsigned type, only 32-bit are set. Currently the RISCV TCG
>> ba
From: Klaus Jensen
Add implementations of namespaces that supports the NVM and Zoned
Command Sets.
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 11 +-
hw/nvme/dif.h | 2 +
hw/nvme/meson.build | 2 +-
hw/nvme/ns-nvm.c| 354 +++
hw/nvme/ns-
On 9/27/21 01:08, Richard Henderson wrote:
> On 9/26/21 6:01 PM, Philippe Mathieu-Daudé wrote:
>> Reported-by: Warner Losh
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> bsd-user/meson.build | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/bsd-user/meson.build b/bsd-user/mes
From: Klaus Jensen
Add a basic user creatable object that models an NVMe NVM subsystem.
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 14 ++---
hw/nvme/ns.c | 5 +-
hw/nvme/nvme.h | 10 +++-
hw/nvme/subsys.c | 144 +--
qapi/qom.json
From: Klaus Jensen
Add the abstract NvmeNamespace object to base proper namespace types on.
Signed-off-by: Klaus Jensen
---
hw/nvme/ns.c | 216 +++
hw/nvme/nvme.h | 22 +
hw/nvme/subsys.c | 31 +++
qapi/qom.json| 17
4 files
From: Klaus Jensen
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 32 +++---
hw/nvme/ns.c | 263 +--
hw/nvme/nvme.h | 44 +---
hw/nvme/subsys.c | 2 +-
4 files changed, 186 insertions(+), 155 deletions(-)
diff --git a/hw/nvme/ctrl.c
From: Klaus Jensen
Signed-off-by: Klaus Jensen
---
docs/system/device-emulation.rst | 1 +
docs/system/devices/nvme-experimental.rst | 107 ++
2 files changed, 108 insertions(+)
create mode 100644 docs/system/devices/nvme-experimental.rst
diff --git a/docs/syste
From: Klaus Jensen
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 282 +++--
hw/nvme/dif.c | 101 +-
hw/nvme/dif.h | 12 +--
hw/nvme/ns.c | 72 +++--
hw/nvme/nvme.h | 45 +---
5 files changed, 290 insertions(+), 22
From: Klaus Jensen
Add a structured type for NGUID.
Signed-off-by: Klaus Jensen
---
include/block/nvme.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/block/nvme.h b/include/block/nvme.h
index 2bcabe561589..f41464ee19bd 100644
--- a/include/block/nvme.h
+++
From: Klaus Jensen
Move ZNS related helpers and types into zns.h. Use a common prefix
(nvme_zoned or nvme_ns_zoned) for zns related functions.
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 110 +
hw/nvme/ns.c | 47 ++---
hw/
From: Klaus Jensen
Add an abstract object NvmeState.
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 382 +--
hw/nvme/dif.c| 4 +-
hw/nvme/dif.h| 2 +-
hw/nvme/ns.c | 4 +-
hw/nvme/nvme.h | 52 ---
hw/nvme/subsys.c | 4 +
From: Klaus Jensen
In preparation for nvm and zoned namespace separation, move zoned
related members from NvmeNamespace into NvmeNamespaceZoned.
There are no functional changes here, basically just a
s/NvmeNamespace/NvmeNamespaceZoned and s/ns/zoned where applicable.
Signed-off-by: Klaus Jensen
From: Klaus Jensen
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 1 +
hw/nvme/dif.c | 1 +
hw/nvme/dif.h | 53 ++
hw/nvme/nvme.h | 50 ---
4 files changed, 55 insertions(+), 50 deletions(-)
creat
From: Klaus Jensen
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 66 +-
hw/nvme/dif.c | 14 +--
hw/nvme/nvme.h | 6 +
3 files changed, 46 insertions(+), 40 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 026dfaa71
From: Hannes Reinecke
With commit 5ffbaeed16 ("hw/nvme: fix controller hot unplugging")
namespaces get moved from the controller to the subsystem if one
is specified.
That keeps the namespaces alive after a controller hot-unplug, but
after a controller hotplug we have to reconnect the namespaces
From: Klaus Jensen
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 10 +++---
hw/nvme/ns.c | 2 +-
hw/nvme/nvme.h | 24 +++-
hw/nvme/subsys.c | 36 ++--
4 files changed, 41 insertions(+), 31 deletions(-)
diff --git a/hw/nvme/ctr
From: Klaus Jensen
Change namespaces to be shared namespaces by default (parameter
shared=on). Keep shared=off for older machine types.
Signed-off-by: Klaus Jensen
---
docs/system/devices/nvme.rst | 24 ++--
hw/core/machine.c| 4 +++-
hw/nvme/ns.c
From: Klaus Jensen
v2
* Use 'zns' instead of 'zoned' for various zns based function name
prefixes (Keith)
* Fix the intialization order and get rid of the machine done
notifier (Kevin). This requires removing the 'attached-ctrls'
parameter and instead controller just attaching to
On 9/27/21 06:47, Philippe Mathieu-Daudé wrote:
> On 9/27/21 04:21, Bin Meng wrote:
>> GCC seems to be strict about processing pattern like "!!for & bar".
What GCC version btw?
>> When 'bar' is not 0 or 1, it complains with -Werror=parentheses:
>>
>> suggest parentheses around operand of ‘!’ or
On Tue, Sep 21, 2021 at 06:11:24PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 9/6/21 22:57, David Gibson wrote:
> > On Fri, Sep 03, 2021 at 05:31:06PM -0300, Daniel Henrique Barboza wrote:
> > > The PMU is already counting cycles by calculating time elapsed in
> > > nanoseconds. Counting inst
On Thu, Sep 23, 2021 at 11:39:14AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 9/6/21 22:38, David Gibson wrote:
> > On Fri, Sep 03, 2021 at 05:31:03PM -0300, Daniel Henrique Barboza wrote:
> > > The PMU needs to enable writing of its uregs to userspace, otherwise
> > > Perf applications will
On Fri, Sep 24, 2021 at 04:05:37PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 9/24/21 15:34, Matheus K. Ferst wrote:
> > On 24/09/2021 11:41, Daniel Henrique Barboza wrote:
> > > On 9/22/21 08:24, Matheus K. Ferst wrote:
> > > > On 03/09/2021 17:31, Daniel Henrique Barboza wrote:
> > > > > [E
The OpenPIC interrupt controller was once the de facto standard on ppc
machines. In qemu it's now only used on some Macintosh and the
Freescale e500 machine. It has no listed maintainer, and as far as I
know, no-one who's really familiar with it any more.
Since I'm moving away from the area, I n
With our interests moving to other areas, Greg and myself no longer have
capacity to be regular reviewers of code for the powernv machine type, let
alone co-maintainers. Additionally, not being IBM employees, we don't have
easy access to the hardware information we'd need for good review.
Therefo
ping
https://lore.kernel.org/qemu-devel/2b5ab039-8495-b55f-03f1-ecfd99690...@zapateado.de/T/#u
https://patchew.org/QEMU/2b5ab039-8495-b55f-03f1-ecfd99690...@zapateado.de/
Am 15.09.21 um 12:56 schrieb Helge Konetzka:
This patch enables native builds on MSYS2 with symlinks disabled.
Signed-off
There are a nunber of old embedded ppc machine types which have been little
changed and in "Odd Fixes" state for a long time. With both myself and
Greg Kurz moving toward other areas, we no longer have the capacity to
keep reviewing and maintaining even the rare patches that come in for those
plat
Greg Kurz and myself have been co-maintainers for the ppc and ppc64
targets for some time now. However, both our day job responsibilities
and interests are leading us towards other areas, so we have less time
to devote to this any more.
Therefore, here's a bunch of updates to MAINTAINERS, intende
On 9/27/21 06:48, David Gibson wrote:
> machine_ppc.py contains tests for 3 different ppc based machine types. It
> is listed in MAINTAINERS along with the PPC TCG cpu code. That's not
> really accurate though, since it's really more about testing those machines
> than the CPUs.
>
> Therefore, s
qemu/KVM on Power is no longer my primary job responsibility, nor Greg
Kurz'. I still have some time for upstream maintenance, but it's no longer
accurate to say that I'm paid to do so. Therefore, reduce sPAPR (the
"pseries" machine type) from Supported to Maintained.
Signed-off-by: David Gibson
machine_ppc.py contains tests for 3 different ppc based machine types. It
is listed in MAINTAINERS along with the PPC TCG cpu code. That's not
really accurate though, since it's really more about testing those machines
than the CPUs.
Therefore, split it up into separate files for the separate ma
Currently the PowerPC TCG CPUs entry in MAINTAINERS lists all of hw/ppc/
and include/hw/ppc. Nearly all the files in those places are related to
specific ppc machine types, rather than to the actual CPUs however. Those
machine types list their own files separately, often overlapping with this.
Fo
Greg and I are moving towards other areas and no longer have capacity to
act as regular reviewers for several of the secondary ppc machine types.
So, remove ourselves as reviewers for Macintosh, PReP, sam460ex and
pegasos2 in MAINTAINERS.
Signed-off-by: David Gibson
Reviewed-by: Greg Kurz
Acked-
On 9/27/21 04:21, Bin Meng wrote:
> GCC seems to be strict about processing pattern like "!!for & bar".
> When 'bar' is not 0 or 1, it complains with -Werror=parentheses:
>
> suggest parentheses around operand of ‘!’ or change ‘&’ to ‘&&’ or ‘!’ to
> ‘~’ [-Werror=parentheses]
>
> Add a () arou
On 9/27/21 02:12, Richard Henderson wrote:
> On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
>> All accelerators but TCG implement their AccelOpsClass::has_work()
>> handler, meaning all the remaining CPUClass::has_work() ones are
>> only reachable from TCG accelerator; and these has_work() handl
On Thu, Sep 23, 2021 at 01:33:44PM +0800, Bin Meng wrote:
> On Tue, Sep 21, 2021 at 4:13 PM Philippe Mathieu-Daudé
> wrote:
> >
> > On 9/21/21 05:25, David Gibson wrote:
> > > On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> > >> The reset value of IPIDR should be zero for Freescale ch
On Fri, Sep 24, 2021 at 05:16:45PM +0200, Philippe Mathieu-Daudé wrote:
65;6402;1c> On 9/24/21 11:55, David Gibson wrote:
> > Greg Kurz and myself have been co-maintainers for the ppc and ppc64
> > targets for some time now. However, both our day job responsibilities
> > and interests are leading
On 9/27/21 10:42, WANG Xuerui wrote:
On 9/27/21 06:01, Philippe Mathieu-Daudé wrote:
Reported-by: Warner Losh
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/meson.build | 4
1 file changed, 4 insertions(+)
I'm newcomer here, but this is just 4 lines of Meson, and two similar
us
On 9/27/21 06:01, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/meson.build | 4
1 file changed, 4 insertions(+)
Reviewed-by: WANG Xuerui
On 9/27/21 06:01, Philippe Mathieu-Daudé wrote:
Reported-by: Warner Losh
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/meson.build | 4
1 file changed, 4 insertions(+)
I'm newcomer here, but this is just 4 lines of Meson, and two similar
usages already exist within QEMU proper s
> On 9/26/21 04:56, Xuzhou Cheng wrote:
> > From: Xuzhou Cheng
> >
> > The Linux spi-imx driver does not work on QEMU. The reason is that the
> > state of m25p80 loops in STATE_READING_DATA state after receiving RDSR
> > command, the new command is ignored. Before sending a new command, CS
> >
If Control.run bit is set while not preserving the Control.claim
bit, the DMA transfer shall not be started.
The following result is PDMA tested in U-Boot on Unleashed board:
=> mw.l 0x300 0x0 <= Disclaim channel 0
=> mw.l 0x300 0x1 <= Claim chann
GCC seems to be strict about processing pattern like "!!for & bar".
When 'bar' is not 0 or 1, it complains with -Werror=parentheses:
suggest parentheses around operand of ‘!’ or change ‘&’ to ‘&&’ or ‘!’ to ‘~’
[-Werror=parentheses]
Add a () around "foo && bar", which also improves code readab
On Sun, Sep 26, 2021 at 1:07 PM Guy Yur wrote:
> On 26/9/21 20:08, Warner Losh wrote:
> >
> >
> > On Fri, Sep 24, 2021 at 6:00 AM Richard Henderson
> > wrote:
> >
> > On 9/21/21 9:56 PM, Warner Losh wrote:
> > > /* no page was there, so we allocate one */
> > > vo
On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
All accelerators but TCG implement their AccelOpsClass::has_work()
handler, meaning all the remaining CPUClass::has_work() ones are
only reachable from TCG accelerator; and these has_work() handlers
belong to TCGCPUOps.
We will gradually move eac
On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
Since there is no specific NVMM handling for cpu_has_work() in
cpu_thread_is_idle(), implement NVMM has_work() handler as a
simple 'return false' code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/nvmm/nvmm-accel-ops.c | 6 ++
1 f
On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
Since there is no specific HAX handling for cpu_has_work() in
cpu_thread_is_idle(), implement HAX has_work() handler as a
simple 'return false' code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/hax/hax-accel-ops.c | 6 ++
1 file
On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
Since there is no specific Xen handling for cpu_has_work() in
cpu_thread_is_idle(), implement Xen has_work() handler as a
simple 'return false' code.
Acked-by: Paul Durrant
Signed-off-by: Philippe Mathieu-Daudé
---
accel/xen/xen-all.c | 6 +
On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
Since there is no specific QTest handling for cpu_has_work() in
cpu_thread_is_idle(), implement QTest has_work() handler as a
simple 'return false' code. Besides, QTest is a "dummy" accelerator
so not much can be done on vCPUs.
Signed-off-by: Phi
On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
Since there is no specific HVF handling for cpu_has_work() in
cpu_thread_is_idle(), implement HVF has_work() handler as a
simple 'return false' code.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/hvf/hvf-accel-ops.c | 6 ++
1 file change
On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
Introduce an accelerator-specific has_work() handler.
Eventually call it from cpu_has_work().
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/accel-ops.h | 5 +
softmmu/cpus.c | 3 +++
On 9/26/21 6:26 PM, Philippe Mathieu-Daudé wrote:
cpu_class_init() always register cpu_common_has_work() as
CPUClass::has_work() handler, so the assertion check in
cpu_has_work() is pointless.
Since cpu_common_has_work() simply returns 'false', we can
inline it in cpu_has_work(), improving the fu
On Sun, Sep 26, 2021 at 5:08 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 9/26/21 6:01 PM, Philippe Mathieu-Daudé wrote:
> > Reported-by: Warner Losh
> > Signed-off-by: Philippe Mathieu-Daudé
> > ---
> > bsd-user/meson.build | 4
> > 1 file changed, 4 insertions(+)
>
On 9/26/21 5:39 PM, Philippe Mathieu-Daudé wrote:
The tcg_target_call_clobber_regs variable is of type TCGRegSet,
which is unsigned and might be 64-bit wide. By initializing it
as unsigned type, only 32-bit are set. Currently the RISCV TCG
backend only uses 32 registers, so this is not a problem.
On 9/26/21 6:01 PM, Philippe Mathieu-Daudé wrote:
Reported-by: Warner Losh
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/meson.build | 4
1 file changed, 4 insertions(+)
diff --git a/bsd-user/meson.build b/bsd-user/meson.build
index 03695493408..a7607e1c884 100644
--- a/bsd-user/m
On 9/26/21 3:15 AM, Philippe Mathieu-Daudé wrote:
On 9/25/21 19:30, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 27 +++
1 file changed, 27 insertions(+)
+static void tcg_target_init(TCGContext
Now that all TCG targets converted their CPUClass::has_work()
handler to a TCGCPUOps::has_work() one, we can remove has_work
from CPUClass.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 2 --
accel/tcg/tcg-accel-ops.c | 3 ---
2 files chan
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Reviewed-by: Bastian Koppelmann
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index b95682b7f04..4
The SPARC target only support TCG acceleration. Remove the CONFIG_TCG
definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops:
move to tcg-cpu-ops.h, keep a pointer in CPUClass").
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
-
Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work()
- SysemuCPUOps::has_work() implementation - to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu-qom.h | 4 +++-
target/ppc/cpu_init.c | 24 ++--
2 files changed,
All TCG targets implement the TCGCPUOps::has_work() handler.
We can remove the non-NULL handler check in tcg_cpu_has_work().
Add an assertion in tcg_exec_realizefn() for future TCG targets.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec.c | 6 ++
accel/tcg/tcg-accel-ops.c
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/xtensa/cpu.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index c1cbd03595e..5cb19a88819 100644
--- a/ta
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/nios2/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 947bb09bc1e..9938d7c2919 100644
--- a/target/nios2/cpu.
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 00e0c55d0e4..3639c03f8ea 100644
--- a/target/mips/cpu.
We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is
a const structure, so to avoid creating multiple versions of
the same structure, simply changing the has_work() handler,
introduce yet another indirection with a has_work() handler in
PowerPCCPUClass, and ppc_cpu_has_work() method which
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 15db277925f..36e6e540483 100644
---
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/openrisc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 27cb04152f9..3c368a1bde7 100644
--- a/target/o
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 89cba9d7a2c..000c2e7793a 100644
--- a/target/hppa/cpu.c
++
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.c | 6 --
target/i386/tcg/tcg-cpu.c | 8 +++-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6b
has_work() is sysemu specific, and Hexagon target only provides
a linux-user implementation. Remove the unused hexagon_cpu_has_work().
Reviewed-by: Richard Henderson
Reviewed-by: Taylor Simpson
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu.c | 6 --
1 file changed, 6 deletio
Restrict arm_cpu_has_work() and has_work() handler to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 4 +++-
target/arm/cpu.c | 7 +--
target/arm/cpu_tcg.c | 2 +-
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/arm/internals.h b/
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Reviewed-by: Michael Rolnik
Signed-off-by: Philippe Mathieu-Daudé
---
target/avr/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5d70e34dd54..6d51f91ca2c 100644
---
ARM v7M cores inherit TYPE_ARM_CPU, so TYPE_ARM_CPU's class_init runs
first and sets up most of the class fields, setting in particular the
has_work handler to the generic arm_cpu_has_work(). Thus M-profile
and A-profile share the same arm_cpu_has_work() function. Some of the
checks the code there
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 25a4aa2976d..ac6b40b2716 100644
--- a/target/rx/cpu.c
+++ b/targ
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 0d252cb5bdc..8d61bf15f6c 100644
--- a/target/sparc/cpu.
Restrict has_work() to sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 93e16a2ffb4..1ca601cac5b 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -3
Now that all accelerators implement a has_work() handler, we can
simplify cpu_has_work() by removing the non-NULL handler check.
Add an assertion in cpus_register_accel() for future accelerators.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/cpus.c | 6 ++---
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 66d22d11895..ad5d26b5c9e 100644
--- a/target/m68k/cpu.c
++
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 2047742d03c..fb2116dc52e 100644
--- a/target/sh4/cpu.c
+++
All accelerators but TCG implement their AccelOpsClass::has_work()
handler, meaning all the remaining CPUClass::has_work() ones are
only reachable from TCG accelerator; and these has_work() handlers
belong to TCGCPUOps.
We will gradually move each target CPUClass::has_work() to
TCGCPUOps in the fo
Since there is no specific HAX handling for cpu_has_work() in
cpu_thread_is_idle(), implement HAX has_work() handler as a
simple 'return false' code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/hax/hax-accel-ops.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/ha
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index c2e7483f5bd..b2761f8b110 100644
--- a/target/cris/cpu.c
+
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/s390_flic.c | 15 ---
target/s390x/cpu.c | 4 +++-
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c
index 74
cpu_class_init() always register cpu_common_has_work() as
CPUClass::has_work() handler, so the assertion check in
cpu_has_work() is pointless.
Since cpu_common_has_work() simply returns 'false', we can
inline it in cpu_has_work(), improving the function readability.
Suggested-by: Richard Henderson
Since there is no specific HVF handling for cpu_has_work() in
cpu_thread_is_idle(), implement HVF has_work() handler as a
simple 'return false' code.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/hvf/hvf-accel-ops.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/accel/hvf/hvf-accel-
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7c626d89cd7..ca76b
Introduce a target-specific has_work() handler for TCG.
Eventually call it from tcg_cpu_has_work(), our
AccelOpsClass::has_work() handler.
Inspired-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/tcg-cpu-ops.h | 4
accel/tcg/tcg-accel-ops.c | 4
2 f
We want to make cpu_has_work() per-accelerator. Only declare its
prototype and move its definition to softmmu/cpus.c.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 8 +---
softmmu/cpus.c| 8
2 files changed, 9 insertions(+)
Implement KVM has_work() handler in AccelOpsClass and
remove it from cpu_thread_is_idle() since cpu_has_work()
is already called.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-accel-ops.c | 6 ++
softmmu/cpus.c| 2 +-
2 files changed, 7 i
Since there is no specific Xen handling for cpu_has_work() in
cpu_thread_is_idle(), implement Xen has_work() handler as a
simple 'return false' code.
Acked-by: Paul Durrant
Signed-off-by: Philippe Mathieu-Daudé
---
accel/xen/xen-all.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/ac
Since there is no specific QTest handling for cpu_has_work() in
cpu_thread_is_idle(), implement QTest has_work() handler as a
simple 'return false' code. Besides, QTest is a "dummy" accelerator
so not much can be done on vCPUs.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/qtest/qtest.c | 6 ++
cpu_has_work() is only called from system emulation code.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core
Introduce an accelerator-specific has_work() handler.
Eventually call it from cpu_has_work().
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/accel-ops.h | 5 +
softmmu/cpus.c | 3 +++
2 files changed, 8 insertions(+)
diff --git a/includ
Implement WHPX has_work() handler in AccelOpsClass and
remove it from cpu_thread_is_idle() since cpu_has_work()
is already called.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/cpus.c| 4 +---
target/i386/whpx/whpx-accel-ops.c | 6 ++
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