Re: [PATCH v6 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops

On 9/25/21 19:30, WANG Xuerui wrote: > Signed-off-by: WANG Xuerui > Reviewed-by: Richard Henderson > --- > tcg/loongarch64/tcg-target.c.inc | 32 > tcg/loongarch64/tcg-target.h | 10 +- > 2 files changed, 37 insertions(+), 5 deletions(-) Reviewed-by:

Re: [PATCH v6 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi

On 9/25/21 19:30, WANG Xuerui wrote: > Signed-off-by: WANG Xuerui > Reviewed-by: Richard Henderson > --- > tcg/loongarch64/tcg-target.c.inc | 137 +++ > 1 file changed, 137 insertions(+) > +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)

Re: [RFC PATCH 0/5] Make Intel PT configurable

Ping... Eduardo, could you please take a look at this series. Thanks! -Xiaoyao On 9/9/2021 10:41 PM, Xiaoyao Li wrote: Initial Intel PT support was added by making it as fixed feature set as ICX's capabilities, which allowed different CPU model with PT enabled live migration on ICX host. Howev

[PATCH] hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19

From: Xuzhou Cheng The Linux spi-imx driver does not work on QEMU. The reason is that the state of m25p80 loops in STATE_READING_DATA state after receiving RDSR command, the new command is ignored. Before sending a new command, CS line should be pulled high to make the state of m25p80 back to IDL

Re: [PATCH 14/14] bsd-user/signal: Create a dummy signal queueing function

On Sat, Sep 25, 2021 at 8:53 AM Warner Losh wrote: > > > On Sat, Sep 25, 2021, 4:50 AM Philippe Mathieu-Daudé > wrote: > >> On 9/22/21 08:14, Warner Losh wrote: >> > Create dummy signal queueing function so we can start to integrate other >> > architectures (at the cost of signals remaining brok

Re: [PATCH] hw/ssi: imx_spi: Improve chip select handling

On Sat, Sep 18, 2021 at 12:19 PM Guenter Roeck wrote: > > On 9/17/21 8:09 PM, Cheng, Xuzhou wrote: > >>> I got some free time in the past days to investigate this issue. Guenter > >>> is right, the Linux imx-spi driver does not work on QEMU. > >>> > >>> The reason is that the state of m25p80 mach

RE: [question] VFIO Device Migration: The vCPU may be paused during vfio device DMA in iommu nested stage mode && vSVA

> From: Kirti Wankhede > Sent: Friday, September 24, 2021 5:29 PM > > On 9/24/2021 12:17 PM, Tian, Kevin wrote: > >> From: Kunkun Jiang > >> Sent: Friday, September 24, 2021 2:19 PM > >> > >> Hi all, > >> > >> I encountered a problem in vfio device migration test. The > >> vCPU may be paused dur

[PATCH] hw/misc: Add a virtual pci device to dynamically attach memory to QEMU

Add a virtual pci to QEMU, the pci device is used to dynamically attach memory to VM, so driver in guest can apply host memory in fly without virtualization management software's help, such as libvirt/manager. The attached memory is isolated from System RAM, it can be used in heterogeneous memory m

[no subject]

Add a virtual pci to QEMU, this pci device is used to dynamically attach memroy to VM, so driver in guest can apply host memory in fly without virtualization management software's help, such as libvirt/manager. The attached memory is isolated from System RAM, it can be used in heterogeneous m

Re: [PATCH] net/slirp: Use newer slirp_*_hostxfwd API

Hi, Sorry for the duplicate email. The cc’s for the maintainers on the email didn’t go through the first time. Nicholas Ngai On 9/25/21 2:48 PM, Nicholas Ngai wrote: libslirp provides a newer slirp_*_hostxfwd API meant for address-agnostic forwarding instead of the is_udp parameter which is

[PATCH] net/slirp: Use newer slirp_*_hostxfwd API

libslirp provides a newer slirp_*_hostxfwd API meant for address-agnostic forwarding instead of the is_udp parameter which is limited to just TCP/UDP. Signed-off-by: Nicholas Ngai --- net/slirp.c | 64 +++-- 1 file changed, 42 insertions(+), 22 del

Re: [PATCH v12 00/10] hvf: Implement Apple Silicon Support

On Sat, 25 Sept 2021 at 18:22, Philippe Mathieu-Daudé wrote: > So this part of Xilinx Versal: > > * When loading an OS, we turn on QEMU's PSCI implementation with SMC > * as the PSCI conduit. When there's no -kernel, we assume the user > * provides EL3 firmware to handle PSCI. >

[PATCH v6 28/30] linux-user: Add safe syscall handling for loongarch64 hosts

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- linux-user/host/loongarch64/hostdep.h | 34 .../host/loongarch64/safe-syscall.inc.S | 80 +++ 2 files changed, 114 insertions(+) create mode 100644 linux-user/host/loongarch64/hostdep.h create

[PATCH v6 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler for loongarch64 hosts

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/user-exec.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8fed542622..38d4ad8a7d 100

[PATCH v6 30/30] configure, meson.build: Mark support for loongarch64 hosts

Example output of `uname -a` on an initial Gentoo LA64 port, running the upstream submission version of Linux (with some very minor patches not influencing output here): > Linux 5.14.0-10342-g37a00851b145 #5 SMP PREEMPT Tue Aug 10 > 12:56:24 PM CST 2021 loongarch64 GNU/Linux And the same on the

[PATCH v6 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 32 tcg/loongarch64/tcg-target.h | 10 +- 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch

[PATCH v6 27/30] tcg/loongarch64: Register the JIT

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 44 1 file changed, 44 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index e3c73f9fe7..73f230b412 100644 --- a/tcg/l

[PATCH v6 21/30] tcg/loongarch64: Implement tcg_out_call

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 34 1 file changed, 34 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 682bf76ceb..e470d7e145 100644 --- a/tcg/l

[PATCH v6 20/30] tcg/loongarch64: Implement setcond ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 69 2 files changed, 70 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-co

[PATCH v6 15/30] tcg/loongarch64: Implement clz/ctz ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 42 tcg/loongarch64/tcg-target.h | 8 +++--- 3 files changed, 47 insertions(+), 4 deletions(-) diff --git a/tcg

Need to merge - QEMU patch for booting eMMC image for AST2600 machine

Hi, I am attaching a patch that will fix eMMC image booting on QEMU for AST2600 machine, without this patch it will be stuck after SPL saying, "booting from RAM". Please review and merge, thanks. Let me know in case of any concern. Thanks. BR, Shitalkumar Seagate Internal 0001-hw-arm-asp

[PATCH v6 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 68 1 file changed, 68 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index ebf886ef8c..207d15ed88 100644 --- a/tcg/l

[PATCH v6 26/30] tcg/loongarch64: Implement tcg_target_init

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 27 +++ 1 file changed, 27 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index d0b8ac05c9..e3c73f9fe7 100644 --- a/tcg/loonga

[PATCH v6 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 + tcg/loongarch64/tcg-target.c.inc | 353 +++ 2 files changed, 355 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-

[PATCH v6 13/30] tcg/loongarch64: Implement deposit/extract ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 21 + tcg/loongarch64/tcg-target.h | 8 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/tcg/loon

[PATCH v6 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 65 tcg/loongarch64/tcg-target.h | 16 +++ 3 files changed, 74 insertion

[PATCH v6 22/30] tcg/loongarch64: Implement simple load/store ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 131 +++ 2 files changed, 132 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con

[PATCH v6 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 91 tcg/loongarch64/tcg-target.h | 4 +- 3 files changed, 94 insertions(+),

[PATCH v6 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 137 +++ 1 file changed, 137 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index f12955723d..4487851b5e 100644 --- a/tcg/

[PATCH v6 07/30] tcg/loongarch64: Implement necessary relocation operations

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 66 1 file changed, 66 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 64e57bd055..fbacaef862 100644 --- a/tcg/l

[PATCH v6 25/30] tcg/loongarch64: Implement exit_tb/goto_tb

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 19 +++ 1 file changed, 19 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 207d15ed88..d0b8ac05c9 100644 --- a/tcg/loongarch64/tc

[PATCH v6 17/30] tcg/loongarch64: Implement add/sub ops

The neg_i{32,64} ops is fully expressible with sub, so omitted for simplicity. Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-set.h | 2 ++ tcg/loongarch64/tcg-target.c.inc | 38

[PATCH v6 08/30] tcg/loongarch64: Implement the memory barrier op

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target.c.inc | 32 1 file changed, 32 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index fbac

[PATCH v6 19/30] tcg/loongarch64: Implement br/brcond ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 53 2 files changed, 54 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-s

[PATCH v6 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 118 +++ 1 file changed, 118 insertions(+) create mode 100644 tcg/loongarch64/tcg-target.c.inc diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target

[PATCH v6 11/30] tcg/loongarch64: Implement sign-/zero-extension ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 82 tcg/loongarch64/tcg-target.h | 24 3 files changed, 95 insertio

[PATCH v6 06/30] tcg/loongarch64: Define the operand constraints

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-str.h | 28 +++ tcg/loongarch64/tcg-target.c.inc | 52 2 files changed, 80 insertions(+) create mode 100644 tcg/loongarc

[PATCH v6 00/30] LoongArch64 port of QEMU TCG

Hi all, This is a port of QEMU TCG to the brand-new CPU architecture LoongArch, introduced by Loongson with their 3A5000 chips. Tests (run with `ninja test`) all passed, as usual; I also boot-tested x86_64 (Debian and Gentoo installation CDs) and install-tested aarch64 (Debian netboot installer),

[PATCH v6 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers

Signed-off-by: WANG Xuerui Acked-by: Richard Henderson --- tcg/loongarch64/tcg-insn-defs.c.inc | 979 1 file changed, 979 insertions(+) create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-in

[PATCH v6 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target-con-set.h | 2 + tcg/loongarch64/tcg-target.c.inc | 88 tcg/loongarch64/tcg-target.h | 16 ++--- 3 files changed, 98 insertions(

[PATCH v6 10/30] tcg/loongarch64: Implement goto_ptr

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 17 + tcg/loongarch64/tcg-target.c.inc | 15 +++ 2 files changed, 32 insertions(+) create mode 100644 tcg/loongarch64/tcg-target-con-set.h diff --git a/tcg/loong

[PATCH v6 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer

I ported the initial code, so I should maintain it of course. Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d7915ec128..859e5b5ba2 100644 ---

[PATCH v6 03/30] tcg/loongarch64: Add the tcg-target.h file

Support for all optional TCG ops are initially marked disabled; the bits are to be set in individual commits later. Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/loongarch64/tcg-target.h | 180 +++ 1 file c

[PATCH v6 01/30] elf: Add machine type value for LoongArch

This is already officially allocated as recorded in GNU binutils repo [1], and the description is updated in [2]. Add to enable further work. [1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4cf2ad720078a9f490dd5b5bc8893a926479196e [2]: https://sourceware.org/git/?p=binutils-gdb.gi

Re: [PATCH v5 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers

On Sat, Sep 25, 2021 at 7:11 PM WANG Xuerui wrote: > On 9/25/21 23:20, Richard Henderson wrote: > > On 9/25/21 10:31 AM, Philippe Mathieu-Daudé wrote: > >> Xuerui said on the cover 1/ we can buy a board on Taobao and 2/ Loongson > >> might help the community with hardware. > >> > >> I tried 1/, sp

Re: [PATCH v12 00/10] hvf: Implement Apple Silicon Support

On 9/21/21 15:30, Alexander Graf wrote: On 21.09.21 11:29, Philippe Mathieu-Daudé wrote: On 9/20/21 22:21, Alexander Graf wrote: On 20.09.21 18:17, Philippe Mathieu-Daudé wrote: On 9/20/21 15:15, Peter Maydell wrote: On Mon, 20 Sept 2021 at 11:11, Peter Maydell wrote: On Thu, 16 Sept 2021 a

Re: [PATCH v5 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers

Hi Richard, On 9/25/21 23:20, Richard Henderson wrote: Adding Alex to the Cc list re docker testing. On 9/25/21 10:31 AM, Philippe Mathieu-Daudé wrote: Xuerui said on the cover 1/ we can buy a board on Taobao and 2/ Loongson might help the community with hardware. I tried 1/, spend more than

Re: [PATCH v5 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi

On 9/25/21 16:04, Richard Henderson wrote: On 9/25/21 5:54 AM, Philippe Mathieu-Daudé wrote: +    /* High bits must be set; load with lu12i.w + optional ori.  */ +    tcg_target_long hi12 = sextreg(val, 12, 20); +    tcg_out_opc_lu12i_w(s, rd, hi12); +    if (lo != 0) { +    tcg_out_opc_o

Re: [PATCH v5 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi

Hi Philippe, On 9/25/21 17:54, Philippe Mathieu-Daudé wrote: On 9/24/21 19:25, WANG Xuerui wrote: Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson ---   tcg/loongarch64/tcg-target.c.inc | 109 +++   1 file changed, 109 insertions(+) +/* Loads a 32-bit im

Re: [PATCH v5 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers

Hi Richard, On 9/25/21 22:20, Richard Henderson wrote: On 9/24/21 11:51 PM, WANG Xuerui wrote: Hi all, On 9/25/21 01:25, WANG Xuerui wrote: Signed-off-by: WANG Xuerui Acked-by: Richard Henderson ---   tcg/loongarch64/tcg-insn-defs.c.inc | 979   1 file changed,

Re: [PATCH v7 12/40] accel/qtest: Implement AccelOpsClass::has_work()

On 9/25/21 17:32, Richard Henderson wrote: On 9/25/21 11:27 AM, Philippe Mathieu-Daudé wrote: +static bool qtest_cpu_has_work(CPUState *cpu) +{ +    g_assert_not_reached(); +} Sigh, this triggers: Running test qtest-i386/cpu-plug-test ** ERROR:../accel/qtest/qtest.c:52:qtest_cpu_has_work: cod

Re: [PATCH v7 00/40] accel: Move has_work() from CPUClass to AccelOpsClass

On 9/25/21 17:28, Richard Henderson wrote: On 9/25/21 10:50 AM, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (40):    accel: Simplify qemu_init_vcpu()    hw/core: Restrict cpu_has_work() to sysemu    hw/core: Un-inline cpu_has_work()    hw/core: Move cpu_common_has_work() to cpu_has_work

Re: [PATCH v7 01/40] accel: Simplify qemu_init_vcpu()

On 9/25/21 10:50 AM, Philippe Mathieu-Daudé wrote: cpus_register_accel() already checks for ops->create_vcpu_thread being non-NULL, so it is pointless to re-check for it in qemu_init_vcpu(). Signed-off-by: Philippe Mathieu-Daudé --- softmmu/cpus.c | 7 +-- 1 file changed, 5 insertions(+),

[PATCH v7 40/40] accel/tcg: Simplify tcg_cpu_has_work()

All TCG targets implement the TCGCPUOps::has_work() handler. We can remove the non-NULL handler check in tcg_cpu_has_work(). Add an assertion in tcg_exec_realizefn() for future TCG targets. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cpu-exec.c | 6 ++ accel/tcg/tcg-accel-ops.c

[PATCH v7 35/40] target/sparc: Remove pointless use of CONFIG_TCG definition

The SPARC target only support TCG acceleration. Remove the CONFIG_TCG definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé -

[PATCH v7 34/40] target/sh4: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03c..fb2116dc52e 100644 --- a/target/sh4/cpu.c +++

Re: [PATCH v7 12/40] accel/qtest: Implement AccelOpsClass::has_work()

On 9/25/21 11:27 AM, Philippe Mathieu-Daudé wrote: +static bool qtest_cpu_has_work(CPUState *cpu) +{ +    g_assert_not_reached(); +} Sigh, this triggers: Running test qtest-i386/cpu-plug-test ** ERROR:../accel/qtest/qtest.c:52:qtest_cpu_has_work: code should not be reached ERROR qtest-i386/cpu

Re: [PATCH v7 00/40] accel: Move has_work() from CPUClass to AccelOpsClass

On 9/25/21 10:50 AM, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (40): accel: Simplify qemu_init_vcpu() hw/core: Restrict cpu_has_work() to sysemu hw/core: Un-inline cpu_has_work() hw/core: Move cpu_common_has_work() to cpu_has_work() accel: Introduce AccelOpsClass::has_wo

Re: [PATCH v7 12/40] accel/qtest: Implement AccelOpsClass::has_work()

+Igor On 9/25/21 16:50, Philippe Mathieu-Daudé wrote: Implement QTest has_work() handler in AccelOpsClass. Since no CPU are available under QTest accelerator, this function is not reachable. Signed-off-by: Philippe Mathieu-Daudé --- accel/qtest/qtest.c | 6 ++ 1 file changed, 6 insertio

[PATCH v7 31/40] target/riscv: Restrict has_work() handler to sysemu and TCG

Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Acked-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7c626d89cd7..ca76b

[PATCH v7 24/40] target/m68k: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/m68k/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d11895..ad5d26b5c9e 100644 --- a/target/m68k/cpu.c ++

[PATCH v7 19/40] target/avr: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Reviewed-by: Michael Rolnik Signed-off-by: Philippe Mathieu-Daudé --- target/avr/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d70e34dd54..6d51f91ca2c 100644 ---

[PATCH v7 39/40] accel/tcg: Remove CPUClass::has_work()

Now that all TCG targets converted their CPUClass::has_work() handler to a TCGCPUOps::has_work() one, we can remove has_work from CPUClass. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 -- accel/tcg/tcg-accel-ops.c | 3 --- 2 files chan

[PATCH v7 37/40] target/tricore: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Reviewed-by: Bastian Koppelmann Signed-off-by: Philippe Mathieu-Daudé --- target/tricore/cpu.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index b95682b7f04..4

Re: [PATCH v5 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers

Adding Alex to the Cc list re docker testing. On 9/25/21 10:31 AM, Philippe Mathieu-Daudé wrote: Xuerui said on the cover 1/ we can buy a board on Taobao and 2/ Loongson might help the community with hardware. I tried 1/, spend more than 2h to read a translated version of the EULA, succeeded at

[PATCH v7 17/40] target/arm: Restrict has_work() handler to sysemu and TCG

Restrict arm_cpu_has_work() and has_work() handler to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 4 +++- target/arm/cpu.c | 7 +-- target/arm/cpu_tcg.c | 2 +- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/

[PATCH v7 36/40] target/sparc: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 0d252cb5bdc..8d61bf15f6c 100644 --- a/target/sparc/cpu.

[PATCH v7 33/40] target/s390x: Restrict has_work() handler to sysemu and TCG

Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/s390_flic.c | 15 --- target/s390x/cpu.c | 4 +++- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c index 74

[PATCH v7 16/40] target/arm: Explicit v7M cores use arm_cpu_has_work as CPUClass:has_work

ARM v7M cores inherit TYPE_ARM_CPU, so TYPE_ARM_CPU's class_init runs first and sets up most of the class fields, setting in particular the has_work handler to the generic arm_cpu_has_work(). Thus M-profile and A-profile share the same arm_cpu_has_work() function. Some of the checks the code there

[PATCH v7 32/40] target/rx: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 25a4aa2976d..ac6b40b2716 100644 --- a/target/rx/cpu.c +++ b/targ

[PATCH v7 38/40] target/xtensa: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595e..5cb19a88819 100644 --- a/ta

[PATCH v7 30/40] target/ppc: Restrict has_work() handlers to sysemu and TCG

Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work() - SysemuCPUOps::has_work() implementation - to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/cpu-qom.h | 4 +++- target/ppc/cpu_init.c | 24 ++-- 2 files changed,

[PATCH v7 15/40] accel/tcg: Introduce TCGCPUOps::has_work()

Introduce a target-specific has_work() handler for TCG. Eventually call it from tcg_cpu_has_work(), our AccelOpsClass::has_work() handler. Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/tcg-cpu-ops.h | 4 accel/tcg/tcg-accel-ops.c | 4 2 f

Re: [PATCH 14/14] bsd-user/signal: Create a dummy signal queueing function

On Sat, Sep 25, 2021, 4:50 AM Philippe Mathieu-Daudé wrote: > On 9/22/21 08:14, Warner Losh wrote: > > Create dummy signal queueing function so we can start to integrate other > > architectures (at the cost of signals remaining broken) to tame the > > dependency graph a bit and to bring in signal

[PATCH v7 29/40] target/ppc: Introduce PowerPCCPUClass::has_work()

We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is a const structure, so to avoid creating multiple versions of the same structure, simply changing the has_work() handler, introduce yet another indirection with a has_work() handler in PowerPCCPUClass, and ppc_cpu_has_work() method which

[PATCH v7 13/40] accel/tcg: Implement AccelOpsClass::has_work()

All accelerators but TCG implement their AccelOpsClass::has_work() handler, meaning all the remaining CPUClass::has_work() ones are only reachable from TCG accelerator; and these has_work() handlers belong to TCGCPUOps. We will gradually move each target CPUClass::has_work() to TCGCPUOps in the fo

[PATCH v7 27/40] target/nios2: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/nios2/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 947bb09bc1e..9938d7c2919 100644 --- a/target/nios2/cpu.

[PATCH v7 12/40] accel/qtest: Implement AccelOpsClass::has_work()

Implement QTest has_work() handler in AccelOpsClass. Since no CPU are available under QTest accelerator, this function is not reachable. Signed-off-by: Philippe Mathieu-Daudé --- accel/qtest/qtest.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest

[PATCH v7 11/40] accel/nvmm: Implement AccelOpsClass::has_work()

Since there is no specific NVMM handling for cpu_has_work() in cpu_thread_is_idle(), implement NVMM has_work() handler as a simple 'return false' code. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/nvmm/nvmm-accel-ops.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/i38

[PATCH v7 28/40] target/openrisc: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/openrisc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f9..3c368a1bde7 100644 --- a/target/o

[PATCH v7 26/40] target/mips: Restrict has_work() handler to sysemu and TCG

Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e4..3639c03f8ea 100644 --- a/target/mips/cpu.

[PATCH v7 25/40] target/microblaze: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925f..36e6e540483 100644 ---

[PATCH v7 10/40] accel/hax: Implement AccelOpsClass::has_work()

Since there is no specific HAX handling for cpu_has_work() in cpu_thread_is_idle(), implement HAX has_work() handler as a simple 'return false' code. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/hax/hax-accel-ops.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/i386/ha

[PATCH v7 08/40] accel/hvf: Implement AccelOpsClass::has_work()

Since there is no specific HVF handling for cpu_has_work() in cpu_thread_is_idle(), implement HVF has_work() handler as a simple 'return false' code. Signed-off-by: Philippe Mathieu-Daudé --- accel/hvf/hvf-accel-ops.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/accel/hvf/hvf-accel-

[PATCH v7 22/40] target/hppa: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 89cba9d7a2c..000c2e7793a 100644 --- a/target/hppa/cpu.c ++

[PATCH v7 23/40] target/i386: Restrict has_work() handler to sysemu and TCG

Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.c | 6 -- target/i386/tcg/tcg-cpu.c | 8 +++- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6b

[PATCH v7 04/40] hw/core: Move cpu_common_has_work() to cpu_has_work()

cpu_class_init() always register cpu_common_has_work() as CPUClass::has_work() handler, so the assertion check in cpu_has_work() is pointless. Since cpu_common_has_work() simply returns 'false', we can inline it in cpu_has_work(), improving the function readability. Suggested-by: Richard Henderson

[PATCH v7 06/40] accel/kvm: Implement AccelOpsClass::has_work()

Implement KVM has_work() handler in AccelOpsClass and remove it from cpu_thread_is_idle() since cpu_has_work() is already called. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- accel/kvm/kvm-accel-ops.c | 6 ++ softmmu/cpus.c| 2 +- 2 files changed, 7 i

[PATCH v7 21/40] target/hexagon: Remove unused has_work() handler

has_work() is sysemu specific, and Hexagon target only provides a linux-user implementation. Remove the unused hexagon_cpu_has_work(). Reviewed-by: Richard Henderson Reviewed-by: Taylor Simpson Signed-off-by: Philippe Mathieu-Daudé --- target/hexagon/cpu.c | 6 -- 1 file changed, 6 deletio

[PATCH v7 14/40] accel: Simplify cpu_has_work()

Now that all accelerators implement a has_work() handler, we can simplify cpu_has_work() by removing the non-NULL handler check. Add an assertion in cpus_register_accel() for future accelerators. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- softmmu/cpus.c | 6 ++---

[PATCH v7 05/40] accel: Introduce AccelOpsClass::has_work()

Introduce an accelerator-specific has_work() handler. Eventually call it from cpu_has_work(). Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/accel-ops.h | 5 + softmmu/cpus.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/includ

[PATCH v7 20/40] target/cris: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/cris/cpu.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5bd..b2761f8b110 100644 --- a/target/cris/cpu.c +

[PATCH v7 02/40] hw/core: Restrict cpu_has_work() to sysemu

cpu_has_work() is only called from system emulation code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core

[PATCH v7 09/40] accel/xen: Implement AccelOpsClass::has_work()

Since there is no specific Xen handling for cpu_has_work() in cpu_thread_is_idle(), implement Xen has_work() handler as a simple 'return false' code. Acked-by: Paul Durrant Signed-off-by: Philippe Mathieu-Daudé --- accel/xen/xen-all.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/ac

[PATCH v7 03/40] hw/core: Un-inline cpu_has_work()

We want to make cpu_has_work() per-accelerator. Only declare its prototype and move its definition to softmmu/cpus.c. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 8 +--- softmmu/cpus.c| 8 2 files changed, 9 insertions(+)

[PATCH v7 18/40] target/alpha: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb4..1ca601cac5b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -3

[PATCH v7 01/40] accel: Simplify qemu_init_vcpu()

cpus_register_accel() already checks for ops->create_vcpu_thread being non-NULL, so it is pointless to re-check for it in qemu_init_vcpu(). Signed-off-by: Philippe Mathieu-Daudé --- softmmu/cpus.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/softmmu/cpus.c b/softmmu

[PATCH v7 07/40] accel/whpx: Implement AccelOpsClass::has_work()

Implement WHPX has_work() handler in AccelOpsClass and remove it from cpu_thread_is_idle() since cpu_has_work() is already called. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- softmmu/cpus.c| 4 +--- target/i386/whpx/whpx-accel-ops.c | 6 ++ 2

[PATCH v7 00/40] accel: Move has_work() from CPUClass to AccelOpsClass

Hi, CPU has_work() is a per-accelerator handler. This series is organized in 2 parts: - Patches 1-15: Move has_work() from CPUClass to AccelOpsClass - Patches 16-40: Move remainging has_work() to TCGCPUOps I prefer to send as a single big series to be sure it is merged at once, since the 2nd part

Re: [PATCH] seabios-hppa: Update SeaBIOS to seabios-hppa-v2

On 9/24/21 3:53 PM, Helge Deller wrote: Changes in seabios-hppa: * Include all latest upstream SeaBIOS patches * add support for the qemu "bootindex" parameter * add support for the qemu "-boot order=g-m" parameter to choose SCSI ID Signed-off-by: Helge Deller Thanks, queued. r~

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