We added a new unit test for testing acpi hotplug on multifunction bridges in
q35 machines. Here, we update the DSDT table gloden master blob for this unit
test.
Signed-off-by: Ani Sinha
---
tests/data/acpi/q35/DSDT.multi-bridge | Bin 0 -> 8435 bytes
tests/qtest/bios-tables-test-allowed-d
We are adding a new unit test to cover the acpi hotplug support in q35 for
multi-function bridges. This test uses a new table DSDT.multi-bridge.
We need to allow changes in DSDT acpi table for addition of this new
unit test.
Signed-off-by: Ani Sinha
---
tests/data/acpi/q35/DSDT.multi-bridge
Am 20.09.21 um 08:23 schrieb Philippe Mathieu-Daudé:
The following commits (released in v6.0.0) made raised the
quality of the TCI backend to the other TCG architectures,
thus is is not considerated experimental anymore:
- c6fbea47664..2f74f45e32b
- dc09f047edd..9e9acb7b348
- b6139eb0578..2fc6f1
commit d7346e614f4ec ("acpi: x86: pcihp: add support hotplug on multifunction
bridges")
added ACPI hotplug descriptions for cold plugged bridges for functions other
than 0. For all other devices, the ACPI hotplug descriptions are limited to
function 0 only. This change adds unit tests for this fea
This patchset adds a unit test to exercize acpi hotplug support for
multifunction
bridges on q35 machines. This support was added with the commit:
d7346e614f4ec ("acpi: x86: pcihp: add support hotplug on multifunction bridges")
changelist:
v1 : initial RFC patch.
v2: incorporated some of the fee
Vladimir Sementsov-Ogievskiy writes:
> Add command that can add and remove filters.
>
> Key points of functionality:
>
> What the command does is simply replace some BdrvChild.bs by some other
> nodes. The tricky thing is selecting there BdrvChild objects.
> To be able to select any kind of BdrvC
We want to use the OBJECT_DECLARE_SIMPLE_TYPE() macro to QOM'ify
this device in the next commit. To make its review simpler, as a
first step move the LASIPS2State and LASIPS2Port declarations to
'hw/input/lasips2.h'
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/input/lasips2.h | 18 ++
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/input/lasips2.h | 17 +
hw/hppa/lasi.c | 10 +-
hw/input/lasips2.c | 38 --
3 files changed, 50 insertions(+), 15 deletions(-)
diff --git a/include/hw/input/lasips
Artist is another device, this one is the Lasi PS/2.
Rename the functions accordingly.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/input/lasips2.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index e7faf24058b..68d741d3421 1
Slowly nuking non-QOM devices: Lasi PS/2's turn.
Philippe Mathieu-Daudé (3):
hw/input/lasips2: Fix typos in function names
hw/input/lasips2: Move LASIPS2State declaration to
'hw/input/lasips2.h'
hw/input/lasips2: QOM'ify the Lasi PS/2
include/hw/input/lasips2.h | 31 --
The following commits (released in v6.0.0) made raised the
quality of the TCI backend to the other TCG architectures,
thus is is not considerated experimental anymore:
- c6fbea47664..2f74f45e32b
- dc09f047edd..9e9acb7b348
- b6139eb0578..2fc6f16ca5e
- dbcbda2cd84..5e8892db93f
Signed-off-by: Philipp
The current way the mask is built can overflow with a 64-bit decrementer.
Use sextract64() to extract the signed values and remove the logic to
handle negative values which has become useless.
Cc: Luis Fernando Fujita Pires
Fixes: a8dafa525181 ("target/ppc: Implement large decrementer support for
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc.c| 169
hw/ppc/trace-events | 22 +-
2 files changed, 82 insertions(+), 109 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index a327206a0a1e..b813ef732ec1 100644
--- a/hw/ppc/ppc.c
++
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 38 ++
target/ppc/trace-events | 8
2 files changed, 18 insertions(+), 28 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d7e32ee107e0..b7d176792098 1
If an unknown pin of the IRQ controller is raised, something is very
wrong in the QEMU model. It is better to abort.
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc.c | 24 ++--
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 73
Hello,
This series converts custom PPC debug messages in trace events. Last
patch is fix for the decrementer when using a 64-bit width.
Thanks,
C.
Cédric Le Goater (4):
target/ppc: Convert debug to trace events (exceptions)
target/ppc: Replace debug messages by asserts for unknown IRQ pin
Vladimir Sementsov-Ogievskiy writes:
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> softmmu/qdev-monitor.c | 42 ++
> 1 file changed, 42 insertions(+)
>
> diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c
> index 0117989009..2e149aa9b8 1
On Sun, 19 Sep 2021 08:29:51 +0530 (IST)
Ani Sinha wrote:
> On Sun, 19 Sep 2021, Ani Sinha wrote:
>
> >
> >
> > On Fri, 17 Sep 2021, Igor Mammedov wrote:
> >
> > > On Fri, 6 Aug 2021 23:16:42 +0530
> > > Ani Sinha wrote:
> > >
> > > > commit d7346e614f4ec ("acpi: x86: pcihp: add support ho
Vladimir Sementsov-Ogievskiy writes:
> Add a class that will unify block parents for blockdev-replace
> functionality we are going to add.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> include/block/block-parent.h | 32 +
> block/block-parent.c | 66 +++
Hi,
> Yes, I really like your approach, makes more sense indeed. But, how do I
> get the core modules that other modules depend on?
>
> I see that Kconfig already has something in this line:
>
> config VGA (from hw/display)
> bool
>
> config PCI (from hw/pci)
> bool
>
> config QXL
On Sun, Sep 19, 2021 at 10:23:21PM -0400, Brad Smith wrote:
> On 9/17/2021 4:58 AM, David Gibson wrote:
> > Hi all,
> >
> > At the qemu-in-rust BoF at KVM Forum, I volunteered to look into
> > whether Rust supported all the host/build platforms that qemu does,
> > which is obviously vital if we wa
On Fri, Sep 17, 2021 at 10:04:50AM -0600, Warner Losh wrote:
> On Fri, Sep 17, 2021 at 5:35 AM Daniel P. Berrangé
> wrote:
>
> > On Fri, Sep 17, 2021 at 06:58:37PM +1000, David Gibson wrote:
> > > Hi all,
> > >
> > > At the qemu-in-rust BoF at KVM Forum, I volunteered to look into
> > > whether R
On Fri, Sep 17, 2021 at 12:34:29PM +0100, Daniel P. Berrangé wrote:
> On Fri, Sep 17, 2021 at 06:58:37PM +1000, David Gibson wrote:
> > Hi all,
> >
> > At the qemu-in-rust BoF at KVM Forum, I volunteered to look into
> > whether Rust supported all the host/build platforms that qemu does,
> > which
On Sat, Sep 18, 2021 at 01:01:35PM -0700, Richard Henderson wrote:
> On 9/17/21 4:03 AM, David Gibson wrote:
> > > For sparc 32, it was added to support Gentoo at that time which didn't
> > > switch to 64-bit yet (https://github.com/rust-lang/rust/pull/48297)
> > >
> > > For the past 2-3y, Gentoo
lishan writes:
> AIO read/write. The size of iocb->aio_nbytes in the kernel cannot exceed
> UIO_MAXIOV = 1024.
> max_segments read from the block device layer may be greater than UIO_MAXIOV,
> this causes the ioq_submit interface to return a -22(-EINVAL) error result.
> ---
> block/file-posix.c
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/pcalign-a64.c | 37 +
tests/tcg/arm/pcalign-a32.c | 46 +++
tests/tcg/aarch64/Makefile.target | 4 +--
tests/tcg/arm/Makefile.target | 4 +++
4 file
Misaligned thumb PC is architecturally impossible.
Assert is better than proceeding, in case we've missed
something somewhere.
Expand a comment about aligning the pc in gdbstub.
Fail an incoming migrate if a thumb pc is misaligned.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
Both single-step and pc alignment faults have priority over
breakpoint exceptions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_
For A64, any input to an indirect branch can cause this.
For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not. This includes the BX instruction but also
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
With v8, this is CONSTRAINED UNPRE
Pull the fault information from where we placed it, in
arm_cpu_tlb_fill and arm_cpu_do_unaligned_access.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/arm/cpu_loop.c | 39 ++-
1 file changed, 34 insertions(+), 5 deletions(-)
diff
Raise pc alignment faults.
Fix single-step and pc-align priority over breakpoints.
Not yet fixing insn abort priority over breakpoints.
Based-on: 20210919015718.466207-1-richard.hender...@linaro.org
("linux-user: Clean up siginfo_t handling")
Changes for v3:
* Rebase on siginfo_t patch set -- w
This will shortly be raised for execution with a misaligned pc.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/aarch64/cpu_loop.c | 44 +--
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/linux-user/aarch64/cpu_loop.c b
On 9/17/2021 4:58 AM, David Gibson wrote:
Hi all,
At the qemu-in-rust BoF at KVM Forum, I volunteered to look into
whether Rust supported all the host/build platforms that qemu does,
which is obviously vital if we want to make Rust a non-optional
component of the build.
I've added the informati
On 8/26/21 6:45 AM, Peter Maydell wrote:
On Sat, 21 Aug 2021 at 21:00, Richard Henderson
wrote:
For A64, any input to an indirect branch can cause this.
For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not. This includes the BX instruction but also
other
On Sun, Sep 19, 2021 at 4:07 AM Philippe Mathieu-Daudé wrote:
>
> - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it
> - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART
> - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()
> - Keep mchp_pfsoc_mmuart_create() behavior
>
>
On Sun, Sep 19, 2021 at 2:55 AM Philippe Mathieu-Daudé wrote:
>
> On Thu, Sep 10, 2020 at 8:29 PM Alistair Francis
> wrote:
> >
> > From: Bin Meng
> >
> > Microchip PolarFire SoC MMUART is ns16550 compatible, with some
> > additional registers. Create a simple MMUART model built on top
> > of th
On Sun, Sep 19, 2021 at 4:55 AM Richard Henderson
wrote:
>
> Add stub host-signal.h for all linux-user hosts.
> Add new code replacing cpu_signal_handler.
> Full migration will happen one host at a time.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> linux-u
On Sun, Sep 19, 2021 at 4:53 AM Richard Henderson
wrote:
>
> The existing code for safe-syscall.inc.S will compile
> without change for riscv32 and riscv64. We may also
> drop the meson.build stanza that merges them for tcg/.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
On 8/21/21 1:46 PM, Philippe Mathieu-Daudé wrote:
+/* Misaligned thumb PC is architecturally impossible. */
+assert((dc->base.pc_next & 1) == 0);
What about using tcg_debug_assert() instead?
I don't think we want to let this one compile out.
r~
On 8/26/21 6:31 AM, Peter Maydell wrote:
+si_signo = TARGET_SIGSEGV;
+si_code = TARGET_SEGV_ACCERR;
+break;
+case 0x5: /* Translation fault, level 1 */
+case 0x7: /* Translation fault, level 2 */
+si_signo = T
On 9/16/21 12:05, Mark Cave-Ayland wrote:
> Slot 0x9 is reserved for use by the in-built framebuffer whilst only slots
> 0xc, 0xd and 0xe physically exist on the Quadra 800.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by:
On 9/16/21 12:05, Mark Cave-Ayland wrote:
> Nubus IRQs are routed to the CPU through the VIA2 device so wire up the IRQs
> using gpios accordingly.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q
On 9/16/21 12:05, Mark Cave-Ayland wrote:
> Since there is no need to generate a dummy declaration ROM, remove both
> nubus_register_rom() and nubus_register_format_block(). These will shortly be
> replaced with a mechanism to optionally load a declaration ROM from disk to
> allow real images to be
On Mon, Aug 16, 2021 at 6:50 PM Eric Blake wrote:
>
> On Fri, Aug 13, 2021 at 11:55:19PM +0300, Nir Soffer wrote:
> > Both qemu and qemu-img use writeback cache mode by default, which is
> > already documented in qemu(1). qemu-nbd uses writethrough cache mode by
> > default, and the default cache
> On Sep 18, 2021, at 12:44 PM, Richard Henderson
> wrote:
>
> Currently there are only two places that require we reset this
> value before exiting to the main loop, but that will change.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/cpu-exec.c | 3 ++-
> accel/tcg/user-exec.c | 2
> On Sep 18, 2021, at 12:44 PM, Richard Henderson
> wrote:
>
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/ppc/host-signal.h | 25 -
> linux
> On Sep 18, 2021, at 12:44 PM, Richard Henderson
> wrote:
>
> Add stub host-signal.h for all linux-user hosts.
> Add new code replacing cpu_signal_handler.
> Full migration will happen one host at a time.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/aarch64/host-signal.h |
> On Sep 18, 2021, at 12:45 PM, Richard Henderson
> wrote:
>
> Now that all of the linux-user hosts have been converted
> to host-signal.h, drop the compatibility code.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/exec-all.h | 12
> linux-user/signal.c | 13
> On Sep 18, 2021, at 12:45 PM, Richard Henderson
> wrote:
>
> Record cr2, error_code, and exception_index. That last means
> that we must exit to cpu_loop ourselves, instead of letting
> exception_index being overwritten.
>
> Use the maperr parameter to properly set PG_ERROR_P_MASK.
>
> S
> On Sep 19, 2021, at 12:43 PM, Philippe Mathieu-Daudé wrote:
>
> On 9/19/21 20:35, Richard Henderson wrote:
>> On 9/18/21 11:45 AM, Richard Henderson wrote:
>>> +/**
>>> + * raise_sigsegv:
>>> + * @cpu: the cpu context
>>> + * @addr: the guest address of the fault
>>> + * @access_type: access
On 9/19/21 20:06, Peter Maydell wrote:
> On Sat, 18 Sept 2021 at 09:12, Ali Vatankhah wrote:
>> then to check what instructions are executing I run this command:
>>
>> qemu-system-ppc64 -nographic -M ppce500 -cpu e5500 -kernel uImage
>> -singlestep -d in_asm -D target_asm.log
>>
>> Obviously this
On 9/18/21 20:45, Richard Henderson wrote:
> We have replaced tlb_fill with record_sigsegv for user mod.
> Move the declaration to restrict it to system emulation.
>
> Signed-off-by: Richard Henderson
> ---
> include/hw/core/tcg-cpu-ops.h | 22 ++
> linux-user/signal.c
On 9/19/21 20:35, Richard Henderson wrote:
> On 9/18/21 11:45 AM, Richard Henderson wrote:
>> +/**
>> + * raise_sigsegv:
>> + * @cpu: the cpu context
>> + * @addr: the guest address of the fault
>> + * @access_type: access was read/write/execute
>> + * @maperr: true for invalid page, false for perm
On 9/18/21 20:45, Richard Henderson wrote:
> Record DAR, DSISR, and exception_index. That last means
> that we must exit to cpu_loop ourselves, instead of letting
> exception_index being overwritten.
Maybe complete:
"This is exactly what the user-mode ppc_cpu_tlb_fill() does,
so simply rename it
On 9/18/21 20:45, Richard Henderson wrote:
> Move the masking of the address from cpu_loop into
> s390_cpu_record_sigsegv -- this is governed by hw, not linux.
> This does mean we have to raise our own exception, rather
> than return to the fallback.
>
> Use maperr to choose between PGM_PROTECTION
On 9/18/21 11:45 AM, Richard Henderson wrote:
+/**
+ * raise_sigsegv:
+ * @cpu: the cpu context
+ * @addr: the guest address of the fault
+ * @access_type: access was read/write/execute
+ * @maperr: true for invalid page, false for permission fault
+ * @ra: host pc for unwinding
+ *
+ * Use the T
On 9/19/21 11:24 AM, Philippe Mathieu-Daudé wrote:
On 9/19/21 20:22, Philippe Mathieu-Daudé wrote:
On 9/18/21 20:45, Richard Henderson wrote:
Add a new user-only interface for updating cpu state before
raising a signal. This will replace tlb_fill for user-only
and should result in less boilerp
On 9/18/21 20:45, Richard Henderson wrote:
> Record cr2, error_code, and exception_index. That last means
> that we must exit to cpu_loop ourselves, instead of letting
> exception_index being overwritten.
>
> Use the maperr parameter to properly set PG_ERROR_P_MASK.
>
> Signed-off-by: Richard He
On 9/18/21 20:45, Richard Henderson wrote:
> The fallback code in raise_sigsegv is sufficient for cris-linux-user.
> Remove the code from cpu_loop that handled the unnamed 0xaa exception.
>
> This makes all of the code in helper.c sysemu only, so remove the
> ifdefs and move the file to cris_softm
On 9/18/21 20:45, Richard Henderson wrote:
> This is a new interface to be provided by the os emulator
> for raising SIGSEGV on fault. Use the new record_sigsegv
> target hook.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/exec-all.h | 15 +++
> accel/tcg/user-exec.c |
On 9/19/21 20:22, Philippe Mathieu-Daudé wrote:
> On 9/18/21 20:45, Richard Henderson wrote:
>> Add a new user-only interface for updating cpu state before
>> raising a signal. This will replace tlb_fill for user-only
>> and should result in less boilerplate for each guest.
>>
>> Signed-off-by: Ri
On Sat, 18 Sept 2021 at 03:55, Duo jia wrote:
>
> Many SOCs have unique id, which is a fixed string of bytes.
> I use "memory_region_init_ram" and "memory_region_add_subregion" to simulate
> this region, how can I initialize specific bytes to fill?
Mostly we just model that kind of thing as a re
On 9/18/21 20:45, Richard Henderson wrote:
> Add a new user-only interface for updating cpu state before
> raising a signal. This will replace tlb_fill for user-only
> and should result in less boilerplate for each guest.
>
> Signed-off-by: Richard Henderson
> ---
> include/hw/core/tcg-cpu-ops.
On 9/18/21 20:44, Richard Henderson wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/alpha/host-signal.h | 41 +
> accel/tcg/user-exec.c | 31 +-
> 2
On 9/18/21 20:45, Richard Henderson wrote:
> Now that all of the linux-user hosts have been converted
> to host-signal.h, drop the compatibility code.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/exec-all.h | 12
> linux-user/signal.c | 13 -
> 2 files c
On 9/19/21 20:07, Richard Henderson wrote:
> On 9/19/21 11:03 AM, Philippe Mathieu-Daudé wrote:
>> On 9/18/21 20:44, Richard Henderson wrote:
>>> Split host_signal_pc and host_signal_write out of user-exec.c.
>>>
>>> Signed-off-by: Richard Henderson
>>> ---
>>> linux-user/host/alpha/host-signal.
On 9/18/21 20:45, Richard Henderson wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/mips/host-signal.h | 62 +-
> accel/tcg/user-exec.c | 52 +
>
On 9/18/21 20:44, Richard Henderson wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/s390/host-signal.h | 93 -
> linux-user/host/s390x/host-signal.h | 2 +-
> accel/tcg/user-exec.c
On 9/19/21 11:03 AM, Philippe Mathieu-Daudé wrote:
On 9/18/21 20:44, Richard Henderson wrote:
Split host_signal_pc and host_signal_write out of user-exec.c.
Signed-off-by: Richard Henderson
---
linux-user/host/alpha/host-signal.h | 41 +
accel/tcg/user-exec.c
On Sat, 18 Sept 2021 at 09:12, Ali Vatankhah wrote:
> then to check what instructions are executing I run this command:
>
> qemu-system-ppc64 -nographic -M ppce500 -cpu e5500 -kernel uImage -singlestep
> -d in_asm -D target_asm.log
>
> Obviously this results in a Kernel panic, but the point is th
On 9/18/21 20:44, Richard Henderson wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/alpha/host-signal.h | 41 +
> accel/tcg/user-exec.c | 31 +-
> 2
On 9/18/21 20:44, Richard Henderson wrote:
> Add stub host-signal.h for all linux-user hosts.
> Add new code replacing cpu_signal_handler.
> Full migration will happen one host at a time.
>
> Signed-off-by: Richard Henderson
> ---
> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index
On 9/18/21 20:44, Richard Henderson wrote:
> The existing code for safe-syscall.inc.S will compile
> without change for riscv32 and riscv64. We may also
> drop the meson.build stanza that merges them for tcg/.
>
> Signed-off-by: Richard Henderson
> ---
> configure
(Cc'ing qemu-devel@ mailing list since this is a development question).
On 9/19/21 19:44, Robert Henry wrote:
> What is the range of the values for vcpu_index given to callbacks, such as:
>
> typedef void (*qemu_plugin_vcpu_udata_cb_t)(unsigned int vcpu_index,
> void *userdata);
>
> Empirically,
On 8/24/21 10:17 AM, Peter Maydell wrote:
I think that EXCP_RANGE should for us be unreachable in user-only
mode (because it can only happen if the relevant bits in SR are
set, and SR is writeable only in supervisor mode, and its starting
value doesn't set these bits). So we could just delete the
On 9/18/21 6:56 PM, Richard Henderson wrote:
Based-on: 20210918184527.408540-1-richard.hender...@linaro.org
("linux-user: Streamline handling of SIGSEGV")
which is in turn based on at least 3 other patch sets, so:
https://gitlab.com/rth7680/qemu/-/commits/tcg-siginfo
Changes since v2:
*
On 9/18/21 7:54 PM, Frank Chang wrote:
Do you mean it's better to change to code sequence to something like:
static void mark_fs_dirty(DisasContext *ctx)
{
.
if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
/* Remember the stage change for the rest of the TB.
On Sun, 19 Sep 2021, Ani Sinha wrote:
> > > > +static void test_acpi_q35_multif_bridge(void)
> > > > +{
> > > > +test_data data = {
> > > > +.machine = MACHINE_Q35,
> > > > +.variant = ".multi-bridge",
> > >
> > > > +.required_struct_types = base_required_struct_typ
On 9/18/21 20:44, Richard Henderson wrote:
> linux-user: Reorg handling for SIGSEGV
> linux-user/host/x86: Populate host_signal.h
> linux-user/host/ppc: Populate host_signal.h
> linux-user/host/alpha: Populate host_signal.h
> linux-user/host/sparc: Populate host_signal.h
> linux-user/h
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