Re: [RFC PATCH] tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges for q35

On Sun, 19 Sep 2021, Ani Sinha wrote: > > > On Fri, 17 Sep 2021, Igor Mammedov wrote: > > > On Fri, 6 Aug 2021 23:16:42 +0530 > > Ani Sinha wrote: > > > > > commit d7346e614f4ec ("acpi: x86: pcihp: add support hotplug on > > > multifunction bridges") > > > added ACPI hotplug descriptions for

Re: [PATCH RESEND v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()

On Sun, Sep 19, 2021 at 2:46 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 9/17/21 2:31 AM, frank.ch...@sifive.com wrote: > > From: Frank Chang > > > > When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. > > Modifying the floating-point state when V=1 causes both

Re: [RFC PATCH] tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges for q35

On Fri, 17 Sep 2021, Igor Mammedov wrote: > On Fri, 6 Aug 2021 23:16:42 +0530 > Ani Sinha wrote: > > > commit d7346e614f4ec ("acpi: x86: pcihp: add support hotplug on > > multifunction bridges") > > added ACPI hotplug descriptions for cold plugged bridges for functions other > > than 0. For

[PATCH v3 23/25] linux-user/sh4: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/sh4/cpu_loop.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/linux-user/sh4/cpu_loop.c b/linux

[PATCH v3 24/25] linux-user/sparc: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 15 +++ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/linux-user/sparc/cpu_l

[PATCH v3 22/25] linux-user/s390x: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Signed-off-by: Richard Henderson --- linux-user/s390x/cpu_loop.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 7a1d0

[PATCH v3 21/25] linux-user/riscv: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 32 ++-- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/

[PATCH v3 25/25] linux-user/xtensa: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/xtensa/cpu_loop.c | 28 +++- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/linux-u

[PATCH v3 20/25] linux-user/ppc: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. The fault address for POWERPC_EXCP_ISI is nip exactly, not nip - 4. Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 146 +-

[PATCH v3 17/25] target/mips: Extract break code into env->error_code

Simplify cpu_loop by doing all of the decode in translate. This fixes a bug in that cpu_loop was not handling the different layout of the R6 version of break16. This fixes a bug in that cpu_loop extracted the wrong bits for the mips16e break16 instruction. Signed-off-by: Richard Henderson ---

[PATCH v3 14/25] linux-user/microblaze: Fix SIGFPE si_codes

Fix a typo for ESR_EC_DIVZERO, which is integral not floating-point. Fix the if ladder for decoding floating-point exceptions. Signed-off-by: Richard Henderson --- linux-user/microblaze/cpu_loop.c | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/linux-use

[PATCH v3 18/25] target/mips: Extract trap code into env->error_code

Simplify cpu_loop by doing all of the decode in translate. Signed-off-by: Richard Henderson --- linux-user/mips/cpu_loop.c| 41 +-- target/mips/tcg/translate.c | 24 ++--- target/mips/tcg/micromips_translate.c.inc | 4 +-- target/mips/tc

[PATCH v3 16/25] linux-user/mips: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/mips/cpu_loop.c | 38 +- 1 file changed, 13 insertions(+), 25 deletions(-) diff --git a

[PATCH v3 19/25] linux-user/openrisc: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/linux-user/openr

[PATCH v3 15/25] linux-user/mips: Improve do_break

Rename to do_tr_or_bp, as per the kernel function. Add a 'trap' argument, akin to the kernel's si_code, but clearer. The return value is always 0, so change the return value to void. Use force_sig and force_sig_fault. Signed-off-by: Richard Henderson --- linux-user/mips/cpu_loop.c | 47 +

[PATCH v3 13/25] linux-user/microblaze: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/microblaze/cpu_loop.c | 63 ++-- 1 file changed, 27 insertions(+), 36 deletions(-) diff --git a

[PATCH v3 07/25] linux-user/hppa: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/linux-user/

[PATCH v3 11/25] linux-user/i386: Use force_sig, force_sig_fault

Replace the local gen_signal with the generic functions that match how the kernel raises signals. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/i386/cpu_loop.c | 48 +++--- 1 file changed, 19 insertions(+), 29 deletions(-) di

[PATCH v3 06/25] linux-user/cris: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/cris/cpu_loop.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/linux-user/cris/cpu_loop.

[PATCH v3 12/25] linux-user/m68k: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/linux-user/m

[PATCH v3 09/25] linux-user/hppa: Set FPE_CONDTRAP for COND

This si_code was changed in 75abf64287cab, for linux 4.17. Signed-off-by: Richard Henderson --- linux-user/syscall_defs.h | 1 + linux-user/hppa/cpu_loop.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 55ccc6ae03..f9efbffe0c 1

[PATCH v3 08/25] linux-user/hppa: Use the proper si_code for PRIV_OPR, PRIV_REG, OVERFLOW

These si_codes have been properly set by the kernel since the beginning. Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index c01ccbbdc0..10487d

[PATCH v3 05/25] linux-user/alpha: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Signed-off-by: Richard Henderson --- linux-user/alpha/cpu_loop.c | 69 - 1 file changed, 22 insertions(+), 47 deletions(-) diff --git a/linux-user/alpha/cpu_loop.c b/linux

[PATCH v3 10/25] linux-user/i386: Split out maybe_handle_vm86_trap

Reduce the number of ifdefs within cpu_loop(). Signed-off-by: Richard Henderson --- linux-user/i386/cpu_loop.c | 31 +++ 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index f813e87294..5866e9844

[PATCH v3 03/25] linux-user/alpha: Set TRAP_UNK for bugchk and unknown gentrap

These si_codes were changed in 535906c684fca, for linux 4.17. Signed-off-by: Richard Henderson --- linux-user/syscall_defs.h | 1 + linux-user/alpha/cpu_loop.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index a

[PATCH v3 02/25] linux-user/aarch64: Use force_sig_fault()

From: Peter Maydell Use the new force_sig_fault() function instead of setting up a target_siginfo_t and calling queue_signal(). Signed-off-by: Peter Maydell Message-Id: <20210813131809.28655-8-peter.mayd...@linaro.org> Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 34 ++

[PATCH v3 01/25] linux-user/arm: Use force_sig_fault()

From: Peter Maydell Use the new force_sig_fault() function instead of setting up a target_siginfo_t and calling queue_signal(). Signed-off-by: Peter Maydell Message-Id: <20210813131809.28655-7-peter.mayd...@linaro.org> Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 53 ++

[PATCH v3 00/25] linux-user: Clean up siginfo_t handling

Based-on: 20210918184527.408540-1-richard.hender...@linaro.org ("linux-user: Streamline handling of SIGSEGV") which is in turn based on at least 3 other patch sets, so: https://gitlab.com/rth7680/qemu/-/commits/tcg-siginfo Changes since v2: * Rebase on top of sigsegv cleanup, which eliminate

[PATCH v3 04/25] linux-user/alpha: Set FPE_FLTUNK for gentrap ROPRAND

This si_code was changed in 4cc13e4f6d441, for linux 4.17. Signed-off-by: Richard Henderson --- linux-user/alpha/cpu_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 13ba9bc1d4..18698d9515 100644 --- a/linu

Re: Rust in Qemu BoF followup: Rust vs. qemu platform support

On 9/17/21 4:03 AM, David Gibson wrote: For sparc 32, it was added to support Gentoo at that time which didn't switch to 64-bit yet (https://github.com/rust-lang/rust/pull/48297) For the past 2-3y, Gentoo sparc is now 64 bit. (like Debian apparently for a while) But apparently, by lack of CI it

Re: [PATCH RESEND v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()

On 9/17/21 2:31 AM, frank.ch...@sifive.com wrote: From: Frank Chang When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty). However, it's possible that HS-level sstatus.FS is Clean and VS-level vss

[PATCH v2 38/41] target/sh4: Make sh4_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for sh4. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8 target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 +---

[PATCH v2 39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for sparc. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Signed-off-by: Richard Henderson --- linux-user/sp

[PATCH v2 37/41] target/s390x: Implement s390_cpu_record_sigsegv

Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for ea

[PATCH v2 34/41] target/ppc: Implement ppc_cpu_record_sigsegv

Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 + target/ppc/cpu_init.c

[PATCH v2 28/41] target/m68k: Make m68k_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for m68k-linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 10 -- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +- 3 files chang

[PATCH v2 29/41] target/microblaze: Make mb_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for mb linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 8 linux-user/microblaze/cpu_loop.c | 10 -- target/microblaze/cpu.

[PATCH v2 40/41] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for xtensa. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c | 9 - target/xtensa/cpu.c | 2 +- target/xtensa/helper.c

[PATCH v2 26/41] target/hppa: Make hppa_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for hppa-linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Signed-off-by: Richard Henderson --- target/hppa/cpu.h

[PATCH v2 36/41] target/s390x: Use probe_access_flags in s390_probe_access

Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 18 +- 1 file changed,

[PATCH v2 30/41] target/mips: Make mips_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for mips linux-user. This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/mips/tcg/tcg-internal.h| 7 ++-- linux-user/mips/cpu_loop.c|

[PATCH v2 24/41] target/cris: Make cris_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for cris-linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Signed-off-by: Richard Henderson --- target

[PATCH v2 41/41] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu

We have replaced tlb_fill with record_sigsegv for user mod. Move the declaration to restrict it to system emulation. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++ linux-user/signal.c | 3 --- 2 files changed, 10 insertions(+), 15 delet

[PATCH v2 15/41] linux-user/host/riscv: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 85 +- accel/tcg/user-exec.c | 134 2 files changed, 84 insertions(+), 135 deletions(-) diff --gi

[PATCH v2 31/41] target/nios2: Make nios2_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for nios2. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Signed-off-by: Richard Henderson --- linux-user/nios2/cpu_loop.c | 10 -- target/nios2/cpu.c | 2 +- target/nios2/helper.c | 8 3 f

[PATCH v2 16/41] target/arm: Fixup comment re handle_cpu_signal

The named function no longer exists. Refer to host_signal_handler instead. Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dab5f1d1cd..07be55b7e1 100644 --- a/

[PATCH v2 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for openrisc. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h

[PATCH v2 27/41] target/i386: Implement x86_cpu_record_sigsegv

Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 6 +++

[PATCH v2 18/41] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER

Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 linux-user/signal.c | 13 - 2 files changed, 25 deletions(-) diff --git a/include/exec/exec-all

[PATCH v2 12/41] linux-user/host/aarch64: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 74 - accel/tcg/user-exec.c | 94 +--

[PATCH v2 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for riscv. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 --- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 + 3 files chang

[PATCH v2 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE

The kernel vectors both of these through unhandled_exception, which results in force_sig(SIGSEGV). This isn't very useful for userland when enabling overflow traps or fpu traps, but c'est la vie. Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 14 ++ 1 file cha

[PATCH v2 14/41] linux-user/host/mips: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Signed-off-by: Richard Henderson --- linux-user/host/mips/host-signal.h | 62 +- accel/tcg/user-exec.c | 52 + 2 files changed, 62 insertions(+), 52 deletions(-) diff

[PATCH v2 25/41] target/hexagon: Remove hexagon_cpu_tlb_fill

The fallback code in raise_sigsegv is sufficient for hexagon. Remove the code from cpu_loop that raises SIGSEGV. Signed-off-by: Richard Henderson --- linux-user/hexagon/cpu_loop.c | 24 +--- target/hexagon/cpu.c | 23 --- 2 files changed, 1 insert

[PATCH v2 11/41] linux-user/host/arm: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/arm/host-signal.h | 30 - accel/tcg/user-exec.c | 45 +-- 2

[PATCH v2 07/41] linux-user/host/x86: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/i386/host-signal.h | 25 - linux-user/host/x32/host-signal.h| 2 +- linux-user/host/x86_64/host-signal.h |

[PATCH v2 23/41] target/arm: Implement arm_cpu_record_sigsegv

Because of the complexity of setting ESR, continue to use arm_deliver_fault. This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to res

[PATCH v2 22/41] target/arm: Use raise_sigsegv for mte tag lookup

Use the new os interface for raising the exception, rather than calling arm_cpu_tlb_fill directly. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 724175

[PATCH v2 20/41] linux-user: Add raise_sigsegv

This is a new interface to be provided by the os emulator for raising SIGSEGV on fault. Use the new record_sigsegv target hook. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++ accel/tcg/user-exec.c | 33 ++--- linux-user/signal.c

[PATCH v2 06/41] linux-user: Reorg handling for SIGSEGV

Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 1 + linux-user/host/arm/host-signal.h | 1 + linux-user/host/i386/host-

[PATCH v2 10/41] linux-user/host/sparc: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solais code as completely unused. Signed-off-by: Richard Henderson --- linux-user/host/sparc/host-signal.h | 54 ++- linux-user/host/sparc64/h

[PATCH v2 13/41] linux-user/host/s390: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 93 - linux-user/host/s390x/host-signal.h | 2 +- accel/tcg/user-exec.c | 88 +-- 3 files c

[PATCH v2 05/41] configure: Merge riscv32 and riscv64 host architectures

The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Signed-off-by: Richard Henderson --- configure | 8 ++-- meson.build

[PATCH v2 21/41] target/alpha: Make alpha_cpu_tlb_fill sysemu only

The fallback code in raise_sigsegv is sufficient for alpha-linux-user. Remove the code from cpu_loop that handled EXCP_MMFAULT. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 7 --- linux-user/alpha/cpu_loop.c | 8 target/alpha/cpu.c | 2 +- target/al

[PATCH v2 00/41] linux-user: Streamline handling of SIGSEGV

Based-on: 20210915174951.1852266-1-richard.hender...@linaro.org ("linux-user/nios2: trap and kuser fixes") ... which itself is Based-on: 20210813131809.28655-1-peter.mayd...@linaro.org ("linux-user: Clean up siginfo_t handling for arm, aarch64") ... for force_sig_fault(). and in turn based on my

[PATCH v2 04/41] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller

Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 ++ 1 file changed, 2 insertions(+), 12 deletions(-)

[PATCH v2 17/41] linux-user/host/riscv: Improve host_signal_write

Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++--- 1 file chang

[PATCH v2 19/41] hw/core: Add TCGCPUOps.record_sigsegv

Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26 ++ 1 file changed, 26 ins

[PATCH v2 02/41] accel/tcg: Move clear_helper_retaddr to cpu loop

Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/accel/tcg/c

[PATCH v2 01/41] accel/tcg: Split out adjust_signal_pc

Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++ accel/tcg/user-exec.c |

[PATCH v2 03/41] accel/tcg: Split out handle_sigsegv_accerr_write

This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Pass guest address to handle_sigsegv_acc

[PATCH v2 09/41] linux-user/host/alpha: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 41 + accel/tcg/user-exec.c | 31 +- 2 files changed, 42 insertions(+), 30 deletions(-) create

[PATCH v2 08/41] linux-user/host/ppc: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 25 - linux-user/host/ppc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 7

[PATCH] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART

- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() - Keep mchp_pfsoc_mmuart_create() behavior Signed-off-by: Philippe Mathieu-Daudé --- include/hw/char/mchp_pfsoc_mmua

Re: [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation

On Thu, Sep 10, 2020 at 8:29 PM Alistair Francis wrote: > > From: Bin Meng > > Microchip PolarFire SoC MMUART is ns16550 compatible, with some > additional registers. Create a simple MMUART model built on top > of the existing ns16550 model. > > Signed-off-by: Bin Meng > Reviewed-by: Alistair Fr

[PULL 3/3] hexagon: use env keyword argument to pass PYTHONPATH

This feature is new in meson 0.57 and allows getting rid of the "env" wrapper. Signed-off-by: Paolo Bonzini --- target/hexagon/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 6fd9360b74..c6d858ffb2 10

[PULL 2/3] meson: switch minimum meson version to 0.58.2

Meson 0.58.2 does not need b_staticpic=$pie anymore, and has stabilized the keyval module. Remove the workaround and use a few replacements for features deprecated in the 0.57.0 release cycle. Reviewed-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- configure | 8 ++

[PULL 0/3] Update meson version

The following changes since commit 831aaf24967a49d7750090b9dcfd6bf356f16529: Merge remote-tracking branch 'remotes/marcandre/tags/misc-pull-request' into staging (2021-09-14 18:14:56 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for yo

Re: [PATCH v2 0/2] coverity-scan: Add accelerator and sysemu components

ping^3 On 7/31/21 17:25, Philippe Mathieu-Daudé wrote: > ping^2? > > On 7/22/21 6:08 PM, Philippe Mathieu-Daudé wrote: >> ping? >> >> On 7/8/21 5:57 PM, Philippe Mathieu-Daudé wrote: >>> Add 'sysemu' component for issues not related to TCG. >>> >>> Since v1: >>> - add accelerator components (Pete

[PULL 1/3] meson: bump submodule to 0.58.2

The update to 0.57 has been delayed due to it causing warnings for some actual issues, but it brings in important bugfixes and new features. 0.58 also brings in a bugfix that is useful for modinfo. Important bugfixes: - 0.57: https://github.com/mesonbuild/meson/pull/7760, build: use PIE objects

Re: [PATCH-for-6.1] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6

On 7/27/21 18:38, Richard Henderson wrote: > On 7/26/21 10:30 PM, Philippe Mathieu-Daudé wrote: >> Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04, >> MULT and MULTU opcodes: >> >>    The value of ac selects an accumulator numbered from 0 to 3. >>    When ac=0, this refers to the

Re: [PATCH-for-6.2 0/2] disas/nios2: Simplify endianess conversion

Cc'ing qemu-trivial@ (series fully reviewed). On 8/7/21 13:09, Philippe Mathieu-Daudé wrote: > After chatting with Richard Henderson and Paolo Bonzini, we > concluded the load/store API is mature enough to have target > code endianess-agnostic. > Thus we could remove the TARGET_WORDS_BIGENDIAN def

Re: high cpu usage in idle state

Hi Philippe, Thank for your email I investigated your advice, first checked the CPU's programmer's reference manual and it has wait for interrupt instruction. then to check what instructions are executing I run this command: qemu-system-ppc64 -nographic -M ppce500 -cpu e5500 -kernel uImage -sin

[RFC 06/10] target/riscv: rvb: add bfp/bfpw instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index fa4597b44b..35f7b0926b 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -245,3 +245,30 @@ target_ulong HELPER(xperm_w)(target_ulong rs1, target_ulong rs2

[RFC 10/10] target/riscv: rvb: add funnel shfit instructions

Add funnel shfit instructions except fsri/fsriw for opcode ecoding reason. Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index e936444c12..08a2fbb376 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @

[RFC 05/10] target/riscv: rvb: add crossbar permutation instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 19c64756c5..fa4597b44b 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -205,3 +205,43 @@ target_ulong HELPER(unshflw)(target_ulong rs1, target_ulong rs2

[RFC 08/10] target/riscv: rvb: add bit-matrix instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 469145ffa9..e936444c12 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -327,3 +327,78 @@ target_ulong HELPER(crc32c_d)(target_ulong rs1) { return d

[RFC 09/10] target/riscv: rvb: fixed an issue about clzw instruction

Signed-off-by: Eric Tang diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 39ca5a573f..4523a5cd4c 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -456,7 +456,7 @@ GEN_TRANS_SHADD(3) static

[RFC 02/10] target/riscv: rvb: add carry-less multiply instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 5b2f795d03..e31cf582ca 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -88,3 +88,38 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2) {

[RFC 07/10] target/riscv: rvb: add CRC instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 35f7b0926b..469145ffa9 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -272,3 +272,58 @@ target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong rs2)

[RFC 04/10] target/riscv: rvb: add generalized shuffle instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index e31cf582ca..19c64756c5 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -123,3 +123,85 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)

[RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions

According to spec, these instructions ignore the upper 32 bit of their input and sign-extend their 32 bit output values. Fixed the output's error when their input values greater than 0x. Signed-off-by: Eric Tang diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/r

[RFC 03/10] target/riscv: rvb: add cmix/cmov instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9eff9d5f5c..989ea3c602 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -43,6 +43,7 @@ &rrd rs1 rs2 &r2 rd rs1 &r2_s rs1 rs2 +&r4 rd rs1 rs2 rs3 &simm rs1

[PATCH] block/file-posix: Limit max_iov to IOV_MAX

AIO read/write. The size of iocb->aio_nbytes in the kernel cannot exceed UIO_MAXIOV = 1024. max_segments read from the block device layer may be greater than UIO_MAXIOV, this causes the ioq_submit interface to return a -22(-EINVAL) error result. --- block/file-posix.c | 3 ++- 1 file changed, 2 i

[RFC 00/10] add the rest of riscv bitmapip-0.93 instructions

These patches fixed some issues about srow/sroiw/clzw instructions and add the rest of riscv bitmapip-0.93 instructions except fsri/fsriw & bext/bdep & bextw/bdepw for opcode coding or name conflict problems. The problems had been fixed in riscv bitmapip-1.0 version. I have tested these bitmapip i

[PATCH] block/file-posix: Limit max_iov to IOV_MAX

AIO read/write. The size of iocb->aio_nbytes in the kernel cannot exceed UIO_MAXIOV = 1024. max_segments read from the block device layer may be greater than UIO_MAXIOV, this causes the ioq_submit interface to return a -22(-EINVAL) error result. --- block/file-posix.c | 3 ++- 1 file changed, 2 i