Re: hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in q35

On Fri, Sep 17, 2021 at 10:11 AM Ani Sinha wrote: > > > > On Thu, 16 Sep 2021, Michael S. Tsirkin wrote: > > > On Thu, Sep 16, 2021 at 06:58:35PM +0530, Ani Sinha wrote: > > > Here's sending v2. > > > > > > changelog : > > > v1: original patch. > > > v2: typo fixed. reviewed-by tags added. > > > >

Re: [PATCH v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()

On Fri, Sep 17, 2021 at 2:14 PM wrote: > From: Frank Chang > > When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. > Modifying the floating-point state when V=1 causes both fields to > be set to 3 (Dirty). > > However, it's possible that HS-level sstatus.FS is Clean and VS-level >

Re: [PATCH RFC 00/13] hw/nvme: experimental user-creatable objects

On Sep 16 18:30, Klaus Jensen wrote: > On Sep 16 14:41, Kevin Wolf wrote: > > Am 14.09.2021 um 22:37 hat Klaus Jensen geschrieben: > > > From: Klaus Jensen > > > > > > Hi, > > > > > > This is an attempt at adressing a bunch of issues that have presented > > > themselves since we added subsystem

[PATCH v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()

From: Frank Chang When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty). However, it's possible that HS-level sstatus.FS is Clean and VS-level vsstatus.FS is Dirty at the time mark_fs_dirty() is cal

[PATCH 15/15] python, iotests: replace qmp with aqmp

Swap out the synchronous QEMUMonitorProtocol from qemu.qmp with the sync wrapper from qemu.aqmp instead. Add an escape hatch in the form of the environment variable QEMU_PYTHON_LEGACY_QMP which allows you to cajole QEMUMachine into using the old interface, proving that both implementations work co

Re: [PATCH v3 00/16] python/iotests: Run iotest linters during Python CI

On Thu, Sep 16, 2021 at 12:10 AM John Snow wrote: > GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-package-iotest > CI: https://gitlab.com/jsnow/qemu/-/pipelines/371611883 > Based-On: <20210915175318.853225-1-hre...@redhat.com> > "[PULL 00/32] Block patches" > > Since iotests ar

[PATCH 11/15] python/aqmp: Create sync QMP wrapper for iotests

This is a wrapper around the async QMPClient that mimics the old, synchronous QEMUMonitorProtocol class. It is designed to be interchangeable with the old implementation. It does not, however, attempt to mimic Exception compatibility. Signed-off-by: John Snow --- python/qemu/aqmp/legacy.py | 13

[PATCH 14/15] python/aqmp: Remove scary message

The scary message interferes with the iotests output. Coincidentally, if iotests works by removing this, then it's good evidence that we don't really need to scare people away from using it. Signed-off-by: John Snow --- python/qemu/aqmp/__init__.py | 14 -- 1 file changed, 14 deletio

[PATCH 09/15] python/machine: remove has_quit argument

If we spy on the QMP commands instead, we don't need callers to remember to pass it. Seems like a fair trade-off. The one slightly weird bit is overloading this instance variable for wait(), where we use it to mean "don't issue the qmp 'quit' command". This means that wait() will "fail" if the QEM

[PATCH 13/15] iotests: Accommodate async QMP Exception classes

(But continue to support the old ones for now, too.) There are very few cases of any user of QEMUMachine or a subclass thereof relying on a QMP Exception type. If you'd like to check for yourself, you want to grep for all of the derivatives of QMPError, excluding 'AQMPError' and its derivatives. T

[PATCH 06/15] python, iotests: remove socket_scm_helper

It's not used anymore, now. Signed-off-by: John Snow --- tests/qemu-iotests/socket_scm_helper.c | 136 - python/qemu/machine/machine.py | 3 - python/qemu/machine/qtest.py | 2 - tests/Makefile.include | 1 - tests/meson.build

[PATCH 10/15] python/machine: Add support for AQMP backend

To use the AQMP backend, Machine just needs to be a little more diligent about what happens when closing a QMP connection. The operation is no longer a freebie in the async world. Because async QMP continues to check for messages asynchronously, it's almost certainly likely that the loop will have

[PATCH 05/15] python/qmp: add send_fd_scm directly to QEMUMonitorProtocol

It turns out you can do this directly from Python ... and because of this, you don't need to worry about setting the inheritability of the fds or spawning another process. Doing this is helpful because it allows QEMUMonitorProtocol to keep its file descriptor and socket object as private implement

[PATCH 07/15] python/aqmp: add send_fd_scm

The single space is indeed required to successfully transmit the file descriptor to QEMU. Signed-off-by: John Snow --- python/qemu/aqmp/qmp_client.py | 17 + 1 file changed, 17 insertions(+) diff --git a/python/qemu/aqmp/qmp_client.py b/python/qemu/aqmp/qmp_client.py index d2ad7

[PATCH 08/15] python/aqmp: Create MessageModel and StandaloneModel classes

This allows 'Greeting' to be subclass of 'Message'. We need the adapter classes to avoid some typing problems that occur if we try to put too much into the 'Model' class itself; the exact details of why are left as an exercise to the reader. Why bother? This makes 'Greeting' ⊆ 'Message', which is

[PATCH 03/15] python/aqmp: Return cleared events from EventListener.clear()

This serves two purposes: (1) It is now possible to discern whether or not clear() removed any event(s) from the queue with absolute certainty, and (2) It is now very easy to get a List of all pending events in one chunk, which is useful for the sync bridge. Signed-off-by: John Snow --- python

[PATCH 12/15] iotests: Disable AQMP logging under non-debug modes

Disable the aqmp logger, which likes to (at the moment) print out intermediate warnings and errors that cause session termination; disable them so they don't interfere with the job output. Leave any "CRITICAL" warnings enabled though, those are ones that we should never see, no matter what. Signe

[PATCH 02/15] python/aqmp: add .empty() method to EventListener

Synchronous clients may want to know if they're about to block waiting for an event or not. A method such as this is necessary to implement a compatible interface for the old QEMUMonitorProtocol using the new async internals. Signed-off-by: John Snow --- python/qemu/aqmp/events.py | 6 ++ 1

[PATCH 04/15] python/qmp: clear events on get_events() call

All callers in the tree *already* clear the events after a call to get_events(). Do it automatically instead and update callsites to remove the manual clear call. These semantics are quite a bit easier to emulate with async QMP, and nobody appears to be abusing some emergent properties of what hap

[PATCH 01/15] python/aqmp: add greeting property to QMPClient

Expose the greeting as a read-only property of QMPClient so it can be retrieved at-will. Signed-off-by: John Snow --- python/qemu/aqmp/qmp_client.py | 5 + 1 file changed, 5 insertions(+) diff --git a/python/qemu/aqmp/qmp_client.py b/python/qemu/aqmp/qmp_client.py index 82e9dab124..d2ad7459

[PATCH 00/15] Switch iotests to using Async QMP

Based-on: <20210916220716.1353698-1-js...@redhat.com> Based-on: <20210915162955.333025-1-js...@redhat.com> [PULL 0/2] Python patches [PATCH v4 00/27] python: introduce Asynchronous QMP package Hiya, This series continues where the first AQMP series left off and adds a synchron

[PATCH v3 3/9] hw/nvram: Introduce Xilinx ZynqMP eFuse device

This implements the Xilinx ZynqMP eFuse, an one-time field-programmable non-volatile storage device. There is only one such device in the Xilinx ZynqMP product family. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias Signed-off-by: Sai Pavan B

[PATCH v3 1/9] hw/nvram: Introduce Xilinx eFuse QOM

This introduces the QOM for Xilinx eFuse, an one-time field-programmable storage bit array. The actual mmio interface to the array varies by device families and will be provided in different change-sets. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E.

[PATCH v3 6/9] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device

Connect the support for Versal eFUSE one-time field-programmable bit array. The command argument: -drive if=pflash,index=1,... Can be used to optionally connect the bit array to a backend storage, such that field-programmed values in one invocation can be made available to next invocation. The

[PATCH v3 7/9] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device

Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM) The command argument: -drive if=pflash,index=2,... Can be used to optionally connect the bbram to a backend storage, such that field-programmed values in one invocation can be made available to next invocation. The backend storage

[PATCH v3 9/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage

Add BBRAM and eFUSE usage to the Xilinx Versal Virt board document. Signed-off-by: Tong Ho --- docs/system/arm/xlnx-versal-virt.rst | 49 1 file changed, 49 insertions(+) diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst index

[PATCH v3 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM

This series implements the Xilinx eFUSE and BBRAM devices for the Versal and ZynqMP product families. Furthermore, both new devices are connected to the xlnx-versal-virt board and the xlnx-zcu102 board. See changes in docs/system/arm/xlnx-versal-virt.rst for detail. --- Changelogs: v2->v3: * M

[PATCH v3 8/9] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device

Connect the support for ZynqMP eFUSE one-time field-programmable bit array. The command argument: -drive if=pflash,index=3,... Can be used to optionally connect the bit array to a backend storage, such that field-programmed values in one invocation can be made available to next invocation. The

[PATCH v3 4/9] hw/nvram: Introduce Xilinx battery-backed ram

This device is present in Versal and ZynqMP product families to store a 256-bit encryption key. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias Signed-off-by: Sai Pavan Boddu Signed-off-by: Tong Ho --- hw/nvram/Kconfig | 4 +

[PATCH v3 2/9] hw/nvram: Introduce Xilinx Versal eFuse device

This implements the Xilinx Versal eFuse, an one-time field-programmable non-volatile storage device. There is only one such device in the Xilinx Versal product family. This device has two separate mmio interfaces, a controller and a flatten readback. The controller provides interfaces for field-

[PATCH v3 5/9] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device

Connect the support for Versal Battery-Backed RAM (BBRAM) The command argument: -drive if=pflash,index=0,... Can be used to optionally connect the bbram to a backend storage, such that field-programmed values in one invocation can be made available to next invocation. The backend storage must b

Re: hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in q35

On Thu, 16 Sep 2021, Michael S. Tsirkin wrote: > On Thu, Sep 16, 2021 at 06:58:35PM +0530, Ani Sinha wrote: > > Here's sending v2. > > > > changelog : > > v1: original patch. > > v2: typo fixed. reviewed-by tags added. > > > Thanks, tagged! > Ani pls make sure the voer letter in the series has

[Bug 1749393] Re: sbrk() not working under qemu-user with a PIE-compiled binary?

I'm running qemu-arm version 4.2.1 (Debian 1:4.2-3ubuntu6.17) on Ubuntu 20.04.03, but I seem to still be affected by this (or something very much like it). In my case it is armhf exim4 crashing while creating a chroot on an amd64 host. The final command run from deeply within exim4's postinst is:

Re: [PATCH 7/9] bsd-user: Don't try to mmap fd when it is -1 independently from MAP_ANONYMOUS flag

On Thu, Sep 16, 2021 at 8:56 PM Warner Losh wrote: > From: Guy Yur > I need to fix this email address in the next round or for the pull request. It's gmail.com, not ngmail.com. Switch checks for !(flags & MAP_ANONYMOUS) with checks for fd != -1. > MAP_STACK and MAP_GUARD also force fd == -1 an

[PATCH 9/9] bsd-user: Apply 86abac06c14 from linux-user (target_mprotect can't fail)

From: Paolo Bonzini linux-user: assert that target_mprotect cannot fail All error conditions that target_mprotect checks are also checked by target_mmap. EACCESS cannot happen because we are just removing PROT_WRITE. ENOMEM should not happen because we are modifying a whole VMA (and we have bi

[PATCH 8/9] bsd-user: Implement MAP_EXCL, required by jemalloc in head

From: Kyle Evans jemalloc requires a working MAP_EXCL. Emulate it by ensuring we don't double map anything. Signed-off-by: Kyle Evans Signed-off-by: Warner Losh --- bsd-user/mmap.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c

[PATCH 4/9] bsd-user: mmap return ENOMEM on overflow

mmap should return ENOMEM on len overflow rather than EINVAL. Return EINVAL when len == 0 and ENOMEM when the rounded to a page length is 0. Found by make check-tcg. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/bsd-use

[PATCH 5/9] bsd-user: mmap prefer MAP_ANON for BSD

MAP_ANON and MAP_ANONYMOUS are identical. Prefer MAP_ANON for BSD since the file is now a confusing mix of the two. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index 0acc2db712..b

[PATCH 7/9] bsd-user: Don't try to mmap fd when it is -1 independently from MAP_ANONYMOUS flag

From: Guy Yur Switch checks for !(flags & MAP_ANONYMOUS) with checks for fd != -1. MAP_STACK and MAP_GUARD also force fd == -1 and they don't require mapping the fd either. Signed-off-by: Guy Yur [ partially merged before, finishing the job and documenting origin] Signed-off-by: Warner Losh --

[PATCH 3/9] bsd-user: MAP_ symbols are defined, so no need for ifdefs

All these MAP_ symbols are always defined on supported FreeBSD versions (12.2 and newer), so remove the #ifdefs since they aren't needed. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 14 -- 1 file changed, 14 deletions(-) diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index 90b6

[PATCH 1/9] bsd-user: Apply e6deac9cf99 from linux-user (zero anonymous memory)

From: Mikaël Urankar linux-user/mmap.c: Always zero MAP_ANONYMOUS memory in mmap_frag() When mapping MAP_ANONYMOUS memory fragments, still need notice about to set it zero, or it will cause issues. Signed-off-by: Chen Gang Reviewed-by: Laurent Vivier Signed-off-by: Riku Voipio [ bsd-user mer

[PATCH 6/9] bsd-user: mmap line wrap change

Keep the shifted expression on one line. It's the same number of lines and easier to read like this. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index bafbdacd31..8b763fffc3 100644 --- a/

[PATCH 2/9] bsd-user: Apply fb7e378cf9c from linux-user (fix FORTIFY warnings)

From: Mikaël Urankar linux-user/mmap.c: fix warnings with _FORTIFY_SOURCE CCi386-linux-user/mmap.o cc1: warnings being treated as errors /usr/src/RPM/BUILD/qemu-0.11.92/linux-user/mmap.c: In function 'mmap_frag': /usr/src/RPM/BUILD/qemu-0.11.92/linux-user/mmap.c:253: error: ignoring return

[PATCH 0/9] bsd-user mmap fixes

This series synchronizes mmap.c with the bsd-user fork. This is a mix of old bug fixes pulled in from linux-user, as well as some newer fixes to adress bugs found in check-tcg and recent FreeBSD developments. There are also a couple of style commits. Guy Yur (1): bsd-user: Don't try to mmap fd w

[PATCH 2/2] modules: use a list of supported arch for each module

When compiling QEMU with more than one target, for instance, --target-list=s390x-softmmu,x86_64-softmmu, modinfo.c will be filled with modules available for both, with no specification of what modules can/cannot be loaded for a particular target. This will cause message errors when executing the t

[PATCH 1/2] meson: introduce modules_arch

This variable keeps track of all modules enabled for a target architecture. This will be used in modinfo to refine the architectures that can really load the .so to avoid errors. Signed-off-by: Jose R. Ziviani --- hw/display/meson.build | 48 ++ hw/usb/mes

[PATCH 0/2] modules: Improve modinfo.c architecture support

When building a single target, the build system detects the architecture and generates a modinfo.c with modules related to that arch only. However, when more than one target is built, modinfo.c is generated with modules available for each architecture - without any way to know what arch supports wh

[PATCH 3/4] ui/gtk: gd_draw_event returns FALSE when no cairo surface is bound

gd_draw_event shouldn't try to repaint if surface does not exist for the VC. Cc: Gerd Hoffmann Signed-off-by: Dongwon Kim --- ui/gtk.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ui/gtk.c b/ui/gtk.c index 92df3d4c5c..5346c331f4 100644 --- a/ui/gtk.c +++ b/ui/gtk.c @@ -778,6 +778,9 @@

[PATCH 4/4] ui/gtk-egl: guest fb texture needs to be regenerated when reinitializing egl

If guest fb is backed by dmabuf (blob-resource), the texture bound to the old context needs to be recreated in case the egl is re-initialized (e.g. new window for vc is created in case of detaching/reattaching of the tab) v2: call egl_dmabuf_release_texutre instead of putting 0 to dmabuf->texture

[PATCH 0/4] ui/gtk-egl: fix for untab/tab problem

This series fixes several problems happening while doing VC untab/tab. Dongwon Kim (4): ui/gtk-egl: un-tab and re-tab should destroy egl surface and context ui/gtk-egl: make sure the right context is set as the current ui/gtk: gd_draw_event returns FALSE when no cairo surface is bound ui/g

[PATCH 2/4] ui/gtk-egl: make sure the right context is set as the current

Making the vc->gfx.ectx current before handling texture associated with it Cc: Gerd Hoffmann Signed-off-by: Dongwon Kim --- ui/gtk-egl.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/ui/gtk-egl.c b/ui/gtk-egl.c index 72ce5e1f8f..7c9629d6cc 100644 --- a/ui/gtk-egl.c +++ b/ui/gtk-egl.

[PATCH 1/4] ui/gtk-egl: un-tab and re-tab should destroy egl surface and context

An old esurface should be destroyed and set to be NULL when doing un-tab and re-tab so that a new esurface an context can be created for the window widget that those will be bound to. Cc: Gerd Hoffmann Signed-off-by: Dongwon Kim Signed-off-by: Khairul Anuar Romli --- ui/gtk.c | 16

[PATCH] ui/gtk: skip any extra draw of same guest scanout blob res

Any extra draw call for the same blob resource representing guest scanout before the previous drawing is not finished can break synchronous draw sequence. To prevent this, drawing is now done only once for each draw submission (when draw_submitted == true). Mutex is added to protect this draw itera

Re: hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in q35

On Thu, Sep 16, 2021 at 06:58:35PM +0530, Ani Sinha wrote: > Here's sending v2. > > changelog : > v1: original patch. > v2: typo fixed. reviewed-by tags added. Thanks, tagged! Ani pls make sure the voer letter in the series has subject [PATCH 0/3] hw/i386/acpi: fix conflicting IO address range

[PULL 0/2] Python patches

The following changes since commit 831aaf24967a49d7750090b9dcfd6bf356f16529: Merge remote-tracking branch 'remotes/marcandre/tags/misc-pull-request' into staging (2021-09-14 18:14:56 +0100) are available in the Git repository at: https://gitlab.com/jsnow/qemu.git tags/python-pull-request f

[PULL 2/2] python: pylint 2.11 support

We're not ready to enforce f-strings everywhere, so just silence this new warning. Signed-off-by: John Snow Reviewed-by: Eduardo Habkost Reviewed-by: Willian Rampazzo Message-id: 20210916182248.721529-3-js...@redhat.com Signed-off-by: John Snow --- python/setup.cfg | 2 +- 1 file changed, 1 i

[PULL 1/2] python: Update for pylint 2.10

A few new annoyances. Of note is the new warning for an unspecified encoding when opening a text file, which actually does indicate a potentially real problem; see https://www.python.org/dev/peps/pep-0597/#motivation Use LC_CTYPE to determine an encoding to use for interpreting QEMU's terminal out

[PULL 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped

From: Frank Chang When virtual registers are swapped, mstatus.SD bit should also be backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept across the world switches. Signed-off-by: Frank Chang Reviewed-by: Vincent Chen Reviewed-by: Alistair Francis Message-id: 20210914013717.8

[PULL 21/21] hw/riscv: opentitan: Correct the USB Dev address

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: d6cb4dfe75a2f536f217d7075b750ece3acb1535.1631767043.git.alistair.fran...@wdc.com Signed-off-by: Alistair Francis --- hw/riscv/opentitan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PULL 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions

From: Bin Meng In U-Boot v2021.07 release, there were 2 major changes for the SiFive Unleashed board support: - Board config name was changed from sifive_fu540_defconfig to sifive_unleashed_defconfig - The generic binman tool was used to generate the FIT image (combination of U-Boot proper,

[PULL 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends

From: Bin Meng The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but in fact it applies to M-mode and S-mode CSR too. Rename these macros to have the COUNTEREN_ prefix. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210915084601.24304-1-bmeng...@gmail.com Sig

[PULL 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer

From: Frank Chang Real PDMA doesn't set Control.error if there are 0 bytes to be transferred. The DMA transfer is still success. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x300 0x0 <= Disclaim channel 0 => mw.l 0x300 0x1

[PULL 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine

From: Anup Patel We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20210831110603.338681-5-anup.pa...@wdc.com Signed

[PULL 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources

From: Anup Patel We will be upgrading SiFive CLINT implementation into RISC-V ACLINT implementation so let's first rename the sources. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20210831110603.338681-2-anup.pa...@wdc.com Signed-off-by: Alistair F

[PULL 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

From: Anup Patel The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel Reviewed-by: Ali

[PULL 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions

From: Frank Chang Real PDMA must have Control.claim bit to be set before Control.run bit is set to start any DMA transactions. Otherwise nothing will be transferred. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x300 0x0 <= Disclaim channel

[PULL 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions

From: Green Wan Real PDMA is able to deal with non-multiple transaction size transactions. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x300 0x0 <= Disclaim channel 0 => mw.l 0x300 0x1 <= Claim channel 0 => mw.l 0x3

[PULL 08/21] hw/timer: Add SiFive PWM support

From: Alistair Francis This is the initial commit of the SiFive PWM timer. This is used by guest software as a timer and is included in the SiFive FU540 SoC. Signed-off-by: Justin Restivo Signed-off-by: Alexandra Clifford Signed-off-by: Amanda Strnad Signed-off-by: Alistair Francis Reviewed-

[PULL 12/21] hw/riscv: virt: Re-factor FDT generation

From: Anup Patel We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20210831110603.338681-4-anup.

[PULL 09/21] sifive_u: Connect the SiFive PWM device

From: Alistair Francis Connect the SiFive PWM device and expose it via the device tree. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.fran...@wdc.com --- docs/system/riscv/sifive_u.rst | 1 + include/hw/ris

[PULL 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set

From: Frank Chang Setting Control.claim clears all of the chanel's Next registers. This is effective only when Control.claim is set from 0 to 1. Signed-off-by: Frank Chang Tested-by: Max Hsu Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 20210912130553.179501-2-frank.ch...@sifive.com

[PULL 04/21] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer and soft MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: LIU Zhiwei Message-id: 946e1ef5e268b24084c7ddad84c146de62

[PULL 06/21] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Tested-by: Bin Meng Message-i

[PULL 05/21] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 0a76946981852f5bd15f0c37ab35b253371027a8

[PULL 01/21] target/riscv: Update the ePMP CSR address

From: Alistair Francis Update the ePMP CSRs to match the 0.9.3 ePMP spec https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git

[PULL 07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.16

[PULL 03/21] target/riscv: Expose interrupt pending bits as GPIO lines

From: Alistair Francis Expose the 12 interrupt pending bits in MIP as GPIO lines. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git

[PULL 02/21] target/riscv: Fix satp write

From: LIU Zhiwei These variables should be target_ulong. If truncated to int, the bool conditions they indicate will be wrong. As satp is very important for Linux, this bug almost fails every boot. Signed-off-by: LIU Zhiwei Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 2021

[PULL 00/21] riscv-to-apply queue

From: Alistair Francis The following changes since commit d1fe59377bbbf91dfded1f08ffe3c636e9db8dc0: Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.2-pull-request' into staging (2021-09-16 16:02:31 +0100) are available in the Git repository at: g...@github.com:ali

Re: [PATCH v1 1/1] hw/riscv: opentitan: Correct the USB Dev address

On Thu, Sep 16, 2021 at 2:37 PM Alistair Francis wrote: > > From: Alistair Francis > > Signed-off-by: Alistair Francis Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/riscv/opentitan.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/opentitan.c b

Re: [PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends

On Wed, Sep 15, 2021 at 6:47 PM Bin Meng wrote: > > The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but > in fact it applies to M-mode and S-mode CSR too. Rename these macros > to have the COUNTEREN_ prefix. > > Signed-off-by: Bin Meng Thanks! Applied to riscv-to-apply.next Ali

plugins: Missing Store Exclusive Memory Accesses

Hello, I recently noticed that the plugin interface does not appear to be emitting callbacks to functions registered via `qemu_plugin_register_vcpu_mem_cb` for AArch64 store exclusives. This would include instructions like `stxp w16, x2, x3, [x4]` (encoding: 0xc8300c82). Seeing as how I'm only ru

Re: [PULL 00/10] Trivial branch for 6.2 patches

pu_dump_state() static (2021-09-16 14:52:46 +0200) > > ---- > Trivial patches pull request 20210916 > > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.2 for any user-visible changes. -- PMM

Re: [RFC PATCH 0/4] block layer: split block APIs in graph and I/O

I think either -global or -global-state. Paolo Il gio 16 set 2021, 16:03 Emanuele Giuseppe Esposito ha scritto: > > > On 15/09/2021 16:43, Stefan Hajnoczi wrote: > > On Wed, Sep 15, 2021 at 02:11:41PM +0200, Paolo Bonzini wrote: > >> On 13/09/21 15:10, Stefan Hajnoczi wrote: > >>> On Wed, Sep

[PATCH v2 4/4] ui/console: prevent use after free error

Make chr in the QemuConsole object a strong reference to the referenced chardev device. This prevents a use after free error if the chardev device goes away unexpectedly. To reproduce the error start qemu-system built with address sanitizer with the the following command line options. -display sd

[PATCH v2 2/4] ui/console: replace kbd_timer with chr_accept_input callback

There's a ChardevClass chr_accept_input() callback function that can replace the write retry timer. Reviewed-by: Marc-André Lureau Signed-off-by: Volker Rümelin --- ui/console.c | 28 +--- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/ui/console.c b/ui/

[PATCH v2 3/4] ui/console: remove chardev frontend connected test

The test if the chardev frontend is connected in kbd_put_keysym_console() is redundant, because the call to qemu_chr_be_can_write() in kbd_send_chars() tests the connected condition again. Remove the redundant test whether the chardev frontend is connected. Reviewed-by: Marc-André Lureau Signed-

[PATCH v2 1/4] ui/console: replace QEMUFIFO with Fifo8

One of the two FIFO implementations QEMUFIFO and Fifo8 is redundant. Replace QEMUFIFO with Fifo8. Signed-off-by: Volker Rümelin --- ui/console.c | 86 1 file changed, 20 insertions(+), 66 deletions(-) diff --git a/ui/console.c b/ui/console.c

[PATCH v2 0/4] ui/console: chardev backend improvements

A few things I learnt while writing a fix for a chardev bug in the GTK backend. v2: Patch "ui/console: replace QEMUFIFO with Fifo8". Renamed the variable free to num_free to help reading the code. (Marc-André) New patch "ui/console: prevent use after free error". ui/gtk.c needs a similar patch.

Re: [PATCH 0/2] Python: update CI tests for pylint 2.10 and 2.11

On Thu, Sep 16, 2021 at 2:22 PM John Snow wrote: > GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-package-pylint-211 > CI: https://gitlab.com/jsnow/qemu/-/pipelines/372122981 > > While debating the fix for 2.10, 2.11 released and added new warnings to > suppress. > > This version includes

Re: [ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable

On Wed, Sep 15, 2021 at 7:51 AM Bin Meng wrote: > > On Fri, Sep 10, 2021 at 4:29 AM Atish Patra wrote: > > > > The RISC-V privilege specification provides flexibility to implement > > any number of counters from 29 programmable counters. However, the Qemu > > nits: %s/Qemu/QEMU > > > implements a

Re: [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR

On Wed, Sep 15, 2021 at 7:54 AM Bin Meng wrote: > > On Fri, Sep 10, 2021 at 4:29 AM Atish Patra wrote: > > > > As per the privilege specification v1.11, mcountinhibit allows to start/stop > > a pmu counter selectively. > > > > Signed-off-by: Atish Patra > > --- > > target/riscv/cpu.h | 2

Re: [PATCH 1/2] python: Update for pylint 2.10

On Thu, Sep 16, 2021 at 3:29 PM John Snow wrote: > > A few new annoyances. Of note is the new warning for an unspecified > encoding when opening a text file, which actually does indicate a > potentially real problem; see > https://www.python.org/dev/peps/pep-0597/#motivation > > Use LC_CTYPE to de

Re: [PATCH 2/2] python: pylint 2.11 support

On Thu, Sep 16, 2021 at 3:24 PM John Snow wrote: > > We're not ready to enforce f-strings everywhere, so just silence this > new warning. Oh, boy! We are good, thanks :) > > Signed-off-by: John Snow > --- > python/setup.cfg | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by

Re: [PATCH 2/2] python: pylint 2.11 support

On Thu, Sep 16, 2021 at 02:22:48PM -0400, John Snow wrote: > We're not ready to enforce f-strings everywhere, so just silence this > new warning. > > Signed-off-by: John Snow Reviewed-by: Eduardo Habkost -- Eduardo

Re: [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function

On Wed, Sep 15, 2021 at 7:51 AM Bin Meng wrote: > > On Fri, Sep 10, 2021 at 4:27 AM Atish Patra wrote: > > > > Currently, the predicate function for PMU related CSRs only works if > > virtualization is enabled. Ideally, they should check the mcountern > > bits before cycle/minstret/hpmcounterx ac

Re: [PATCH 1/2] python: Update for pylint 2.10

On Thu, Sep 16, 2021 at 02:22:47PM -0400, John Snow wrote: > A few new annoyances. Of note is the new warning for an unspecified > encoding when opening a text file, which actually does indicate a > potentially real problem; see > https://www.python.org/dev/peps/pep-0597/#motivation > > Use LC_CTY

Re: [PATCH] hw/rtc/pl031: Send RTC_CHANGE QMP event

On Thu, 16 Sept 2021 at 18:19, Eric Auger wrote: > > Hi Peter, > On 9/16/21 3:32 PM, Peter Maydell wrote: > > None of the other users of qapi_event_send_rtc_change() > > seem to have to track the baseline time like this. Shouldn't > > this be doing something involving using qemu_ref_timedate() > >

[PATCH 1/2] python: Update for pylint 2.10

A few new annoyances. Of note is the new warning for an unspecified encoding when opening a text file, which actually does indicate a potentially real problem; see https://www.python.org/dev/peps/pep-0597/#motivation Use LC_CTYPE to determine an encoding to use for interpreting QEMU's terminal out

[PATCH 0/2] Python: update CI tests for pylint 2.10 and 2.11

GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-package-pylint-211 CI: https://gitlab.com/jsnow/qemu/-/pipelines/372122981 While debating the fix for 2.10, 2.11 released and added new warnings to suppress. This version includes everything needed to get the Gitlab CI green again. John Snow

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