On 8/30/21 10:16 AM, Frédéric Pétrot wrote:
This series of patches aims at adding partial 128-bit support to the riscv
target, following the (unratified) RV128I specification, Chapter 7 of
riscv-spec document dated 20191214.
It provides support for all user integer (I) instructions and for an M
e
On 30/08/2021 23.15, Philippe Mathieu-Daudé wrote:
On 8/30/21 6:02 PM, Thomas Huth wrote:
On 30/08/2021 15.33, Philippe Mathieu-Daudé wrote:
Hi Thomas,
On 8/25/21 1:00 PM, Thomas Huth wrote:
From: Daniel P. Berrangé
This splits the CI docs into one file talking about job setup and usage
and
Hi,
> In particular, I wasn't able to have a hdd in the virtual machine
> using virtio-blk-device like this:
>
> -drive file=foo,if=none,id=drv -device virtio-blk-device,drive=drv
>
> What modules/options are needed within linux guest to see such a
> drive? By loading just virtio-blk module
On 8/30/21 3:00 PM, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 8/30/21 8:24 AM, Richard Henderson wrote:
Currently, we have support for optimizing redundant zero extensions,
which I think was done with x86 and aarch64 in mind, which zero-extend
all 32-bit operations into the 64-bit register.
On 8/30/21 10:16 AM, Frédéric Pétrot wrote:
target/riscv/utils_128.h| 173
You should extend include/qemu/int128.h as needed, rather than this.
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4321b03b94..0d18055e08 100644
--- a/target/riscv/cpu.h
+
On 8/30/21 10:16 AM, Frédéric Pétrot wrote:
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6528b4540e..4321b03b94 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -60,6 +60,19 @@
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
/* To be used on misah, the upper
On 8/30/21 2:38 PM, Philippe Mathieu-Daudé wrote:
+#if defined(TARGET_RISCV128)
+if (is_128bit(ctx)) {
Maybe this could allow the compiler eventually elide the
code and avoid superfluous #ifdef'ry:
if (TARGET_LONG_BITS >= 128) {
TCG does not support TARGET_LONG_BITS != {3
On 8/30/21 10:16 AM, Frédéric Pétrot wrote:
Adding the support for the 128-bit arithmetic and logic instructions.
Remember that all (i) instructions are now acting on 128-bit registers, that
a few others are added to cope with values that are held on 64 bits within
the 128-bit registers, and that
On Tue, Aug 31, 2021 at 5:29 AM Frédéric Pétrot
wrote:
>
> This series of patches aims at adding partial 128-bit support to the riscv
> target, following the (unratified) RV128I specification, Chapter 7 of
> riscv-spec document dated 20191214.
> It provides support for all user integer (I) instruc
On Tue, Aug 31, 2021 at 5:26 AM Frédéric Pétrot
wrote:
>
> Starting 128-bit extension support implies a few modifications in the
> existing sources because checking for 32-bit is done by checking that
> it is not 64-bit and vice-versa.
> We now consider the 3 possible xlen values so as to allow co
On 8/30/21 10:16 AM, Frédéric Pétrot wrote:
+void tcg_gen_ext_i64_i128(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg)
+{
+tcg_gen_mov_i64(lo, arg);
+tcg_gen_sari_i64(hi, arg, 63);
+}
No, don't add this until we add TCGv_i128.
Just use sari as needed in target/riscv when dealing with TCGv_i64.
On 8/30/21 10:16 AM, Frédéric Pétrot wrote:
+#if defined(TARGET_RISCV128)
+/*
+ * Accessing signed 64-bit or 128-bit values should be part of MemOp in
+ * include/exec/memop.h
+ * Unfortunately, this requires to change the defines there, as MO_SIGN is 4,
+ * and values 0 to 3 are usual types size
Hi,
On 2021/8/31 2:32, Peter Maydell wrote:
On Mon, 30 Aug 2021 at 08:36, Greg Kurz wrote:
On Fri, 27 Aug 2021 06:24:51 -0300
Daniel Henrique Barboza wrote:
Signed-off-by: Daniel Henrique Barboza
---
We usually introduce the compat machine types for all archs in a
single patch. One was al
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Yanan Wang
Acked-by: David Gibson
Reviewed-by: Andrew Jones
Reviewed-by: Cornelia Huck
Reviewed-by: Pankaj Gupta
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c
This patch adds 6.2 machine types for arm/i440fx/q35/s390x/spapr,
which is originally from [1]. Here resend it separately and hopefully
it can get into upstream first, so that some other patches currently
on the mail list which depend on 6.2 machine compat stuff can be
rebased on this.
[1]
https:
Hi Richard,
On Mon, Apr 19, 2021 at 01:22:43PM -0700, Richard Henderson wrote:
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target/arm/translate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/transla
On Mon, Aug 30, 2021 at 05:44:00PM +0200, BALATON Zoltan wrote:
> On Mon, 30 Aug 2021, David Gibson wrote:
> > On Sun, Aug 29, 2021 at 04:09:54AM +, Joseph wrote:
> > > Hi Mark, Cédric, Greg at the openbsd-ppc ML,
> > >
> > > It is great to talk to you. Thank you for taking on the conversation
On Mon, Aug 30, 2021 at 06:04:31PM +0200, Michal Suchánek wrote:
> On Mon, Aug 30, 2021 at 04:57:21PM +1000, David Gibson wrote:
> > On Sun, Aug 29, 2021 at 04:09:54AM +, Joseph wrote:
> > > Hi Mark, Cédric, Greg at the openbsd-ppc ML,
>
> >
> > So.. if you want to run OpenBSD on POWER10 you
On Mon, Aug 30, 2021 at 9:19 PM Philipp Tomsich
wrote:
>
> The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a
> orc.b instruction (equivalent to the orc.b pseudo-instruction built on
> gorci from pre-0.93 draft-B) is available, mainly targeting
> string-processing workloads.
>
> Thi
On Tue, Aug 31, 2021 at 1:27 AM Richard Henderson
wrote:
>
> On 8/30/21 3:12 AM, Alistair Francis wrote:
> > On Sat, Aug 21, 2021 at 3:43 AM Richard Henderson
> > wrote:
> >>
> >> Replace use of tcg_const_*, which makes a copy into a temp which must
> >> be freed, with direct use of the constant.
Linux kernel can return size of af_unix socket to be
one byte larger than sockaddr_un structure - adding
the trailing zero byte.
Signed-off-by: Michael Tokarev
Fixes: 4cfd970ec188558daa6214f26203fe553fb1e01f (first in 6.1.0)
Cc: qemu-sta...@nongnu.org
diff --git a/util/qemu-sockets.c b/util/qemu
On Thu, Aug 19, 2021 at 6:18 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target.c.inc | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-
31.08.2021 01:06, Michael Tokarev wrote:
...
And this is the value used to be returned in the getsockname/getpeername
calls.
So this has nothing to do with socket being abstract or not. We asked for
larger storage for the sockaddr structure, and the kernel was able to build
one for us, including
On Tue, Aug 24, 2021 at 09:48:35PM -0300, Daniel Henrique Barboza wrote:
> MEM_UNPLUG_ERROR is deprecated since the introduction of
> DEVICE_UNPLUG_GUEST_ERROR. Keep emitting both while the deprecation of
> MEM_UNPLUG_ERROR is pending.
>
> CC: Michael S. Tsirkin
> CC: Igor Mammedov
> Reviewed-by
On 8/30/21 12:24 PM, Mark Cave-Ayland wrote:
> The ADB is accessed using clock and data pins on q800 VIA1 port B and so can
> be
> moved to MOS6522Q800VIA1State.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c| 6 +-
> hw/misc/mac_via.c | 169 +++
31.08.2021 00:38, Michael Tokarev wrote:
...
@@ -1345,13 +1345,16 @@ socket_sockaddr_to_address_unix(struct sockaddr_storage
*sa,
SocketAddress *addr;
struct sockaddr_un *su = (struct sockaddr_un *)sa;
+ assert(salen >= sizeof(su->sun_family) + 1 &&
+ salen <= sizeof(str
On 8/30/21 12:24 PM, Mark Cave-Ayland wrote:
> The PRAM/RTC is accessed using clock and data pins on q800 VIA1 port B and so
> can be moved to MOS6522Q800VIA1State.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 135 +++---
> include/hw/mi
On 8/30/21 12:24 PM, Mark Cave-Ayland wrote:
> Now that q800 VIA1 and VIA2 are completely separate devices there is no need
> to
> add a specific device prefix to ensure that the IRQ lines remain separate.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c| 10 --
> hw/misc/
On 8/30/21 12:24 PM, Mark Cave-Ayland wrote:
> After this change mac_via_reset() is now empty and can be removed.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 22 --
> 1 file changed, 8 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Hi Richard,
On 8/30/21 8:24 AM, Richard Henderson wrote:
> Currently, we have support for optimizing redundant zero extensions,
> which I think was done with x86 and aarch64 in mind, which zero-extend
> all 32-bit operations into the 64-bit register.
>
> But targets like Alpha, MIPS, and RISC-V d
On 8/30/21 8:24 AM, Richard Henderson wrote:
> Pull the "op r, a, a => movi r, 0" optimization into a function,
> and use it in the outer opcode fold functions.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 41 -
> 1 file changed, 24 insert
On 8/30/21 8:24 AM, Richard Henderson wrote:
> This is the final entry in the main switch that was in a
> different form. After this, we have the option to convert
> the switch into a function dispatch table.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 27 ++---
On 8/30/21 8:24 AM, Richard Henderson wrote:
> Pull the "op r, a, 0 => movi r, 0" optimization into a function,
> and use it in the outer opcode fold functions.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 32 +++-
> 1 file changed, 15 insertions(+),
On 8/30/21 8:24 AM, Richard Henderson wrote:
> Pull the "op r, a, a => mov r, a" optimization into a function,
> and use it in the outer opcode fold functions.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 39 ---
> 1 file changed, 24 insertion
On Mon, Aug 30, 2021 at 11:05:35AM -0500, ebl...@redhat.com wrote:
> On Mon, Aug 30, 2021 at 03:56:16PM +, Raphael Norwitz wrote:
> > On Fri, Aug 27, 2021 at 01:51:48PM -0500, ebl...@redhat.com wrote:
> > > On Fri, Aug 27, 2021 at 04:50:35PM +, Raphael Norwitz wrote:
> > > > This change add
On Mon, 30 Aug 2021, Peter Maydell wrote:
On Mon, 30 Aug 2021 at 21:29, Programmingkid wrote:
I found out that there are two pc-bios folders. One in the root directory
and one in the build directory. QEMU is looking in the pc-bios folder
located inside the build folder. The qemu_vga.ndrv file i
On 8/30/21 8:24 AM, Richard Henderson wrote:
> Sign repetitions are perforce all identical, whether they are 1 or 0.
> Bitwise operations preserve the relative quantity of the repetitions.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 29 +
> 1 file ch
On 8/30/21 8:24 AM, Richard Henderson wrote:
> Rename to fold_addsub2.
> Use Int128 to implement the wider operation.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 64 +-
> 1 file changed, 43 insertions(+), 21 deletions(-)
Reviewed
On 8/18/21 9:18 PM, Richard Henderson wrote:
> Use the MemOpIdx directly, rather than the rearrangement
> of the same bits currently done by the trace infrastructure.
> Pass in enum qemu_plugin_mem_rw so that we are able to treat
> read-modify-write operations as a single operation.
>
> Signed-off
19.07.2021 16:01, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Commit 776b97d360 "qemu-sockets: add abstract UNIX domain socket
support" neglected to update socket_sockaddr_to_address_unix() and
copied the whole sun_path without taking "salen" into account.
Later, commit 3b14b4ec
On 8/30/21 11:38 PM, Philippe Mathieu-Daudé wrote:
> On 8/30/21 7:16 PM, Frédéric Pétrot wrote:
>> Adding the support for the 128-bit arithmetic and logic instructions.
>> Remember that all (i) instructions are now acting on 128-bit registers, that
>> a few others are added to cope with values that
On 8/30/21 7:16 PM, Frédéric Pétrot wrote:
> Adding the support for the 128-bit arithmetic and logic instructions.
> Remember that all (i) instructions are now acting on 128-bit registers, that
> a few others are added to cope with values that are held on 64 bits within
> the 128-bit registers, and
On 8/30/21 7:16 PM, Frédéric Pétrot wrote:
> Addition of the load(s) and store instructions of the 128-bit extension.
> These instructions have addresses on 128-bit but explicitly assume that the
> upper 64-bit of the address registers is null, and therefore can use the
> existing address translati
On 8/30/21 7:16 PM, Frédéric Pétrot wrote:
> Addition of the upper 64 bits of the 128-bit registers, along with
> the setter and getter for them and creation of the corresponding
> global tcg values.
>
> Signed-off-by: Frédéric Pétrot
> Co-authored-by: Fabien Portas
> ---
> slirp
On 8/18/21 9:19 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/riscv/tcg-target.c.inc | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
=)
Reviewed-by: Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Use the MemOpIdx directly, rather than the rearrangement
> of the same bits currently done by the trace infrastructure.
> Pass in enum qemu_plugin_mem_rw so that we are able to treat
> read-modify-write operations as a single operation.
>
> Signed-off
On 8/30/21 8:24 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 27 ---
> 1 file changed, 16 insertions(+), 11 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 8/30/21 6:02 PM, Thomas Huth wrote:
> On 30/08/2021 15.33, Philippe Mathieu-Daudé wrote:
>> Hi Thomas,
>>
>> On 8/25/21 1:00 PM, Thomas Huth wrote:
>>> From: Daniel P. Berrangé
>>>
>>> This splits the CI docs into one file talking about job setup and usage
>>> and another file describing provis
On Thu, Aug 26, 2021 at 10:40:47AM +0200, Philippe Mathieu-Daudé wrote:
> On 8/26/21 5:28 AM, Jason Wang wrote:
> > On Thu, Aug 26, 2021 at 6:43 AM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> When a ring queue size is modified, we need to call
> >> virtio_queue_update_rings() to re-init the memory
On Thu, Aug 26, 2021 at 05:16:03PM +0200, Philippe Mathieu-Daudé wrote:
> On 8/26/21 10:40 AM, Philippe Mathieu-Daudé wrote:
> > On 8/26/21 5:28 AM, Jason Wang wrote:
> >> On Thu, Aug 26, 2021 at 6:43 AM Philippe Mathieu-Daudé
> >> wrote:
> >>>
> >>> When a ring queue size is modified, we need to
On Mon, 30 Aug 2021 at 21:29, Programmingkid wrote:
> I found out that there are two pc-bios folders. One in the root directory
> and one in the build directory. QEMU is looking in the pc-bios folder
> located inside the build folder. The qemu_vga.ndrv file is only located
> in the root directory
On Mon, 30 Aug 2021 11:51:51 +0200
Christian Borntraeger wrote:
> On 27.08.21 12:50, Pierre Morel wrote:
> > Hello All,
> >
> >
> > This series presents a VIRTIO test device which receives data on its
> > input channel and sends back a simple checksum for the data it received
> > on its output
> On Aug 29, 2021, at 8:17 AM, Peter Maydell wrote:
>
> On Sun, 29 Aug 2021 at 11:18, Mark Cave-Ayland
> wrote:
>> What I don't understand is that the binary is installed by default in QEMU's
>> sharedir
>> so everything works out of the box with "make install". Do you have some
>> kind of
On Mon, 30 Aug 2021 at 20:37, Johannes S wrote:
> In my opinion we should use 'unsigned' data types here for the ioctl
> request in the ioctl wrappers or would you prefer to keep the ioctl
> wrapper definition as is today? What is you opinion?
I think I would vote for following the type used by t
On Sun, Aug 29, 2021 at 11:10 PM Peter Maydell wrote:
> It would be more helpful to readers to state the reason directly
> in the commit message, rather than requiring them to go and look
> up a comment in some other file.
Thanks for the tip, that makes sense. I will follow it next time.
> > Of
Adding the support for the 128-bit arithmetic and logic instructions.
Remember that all (i) instructions are now acting on 128-bit registers, that
a few others are added to cope with values that are held on 64 bits within
the 128-bit registers, and that the ones that cope with values on 32-bit
must
128-bit mult and div helpers may now use the compiler support
for 128-bit integers if it exists.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/cpu.h | 13 +++
target/riscv/m128_helper.c | 48 ++
2 files changed,
Addition of a 128-bit satp to support memory translation.
We propose two new virtual memory schemes for targets with 128-bit addresses.
These schemes, sv44 and sv54, are natural extensions of the sv39 and sv48
schemes, but with 16KB page tables.
The theoretical physically addressable space is 68 bi
Addition of the upper 64 bits of the 128-bit registers, along with
the setter and getter for them and creation of the corresponding
global tcg values.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
slirp| 2 +-
target/riscv/cpu.h | 3 +++
target/ris
Adding 128-bit support for a minimal subset of the csrs, so that it is
possible to boot and jump to and return from interrupts/exceptions using
the csrrw instruction.
The (partially handled) 128-bit csrs are the following:
csr_mhartid, csr_mstatus, csr_misa, csr_mtvec, csr_mscratch and csr_mepc.
We
This series of patches aims at adding partial 128-bit support to the riscv
target, following the (unratified) RV128I specification, Chapter 7 of
riscv-spec document dated 20191214.
It provides support for all user integer (I) instructions and for an M
extension which follows the definition of the 3
Addition of the load(s) and store instructions of the 128-bit extension.
These instructions have addresses on 128-bit but explicitly assume that the
upper 64-bit of the address registers is null, and therefore can use the
existing address translation mechanism.
128-bit memory access identification
Adding the support for the 128-bit (m) extension.
Division and remainder are helpers using a simple implementation of Knuth
algorithm D.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/helper.h | 8 +
target/riscv/insn32.decode |
Starting 128-bit extension support implies a few modifications in the
existing sources because checking for 32-bit is done by checking that
it is not 64-bit and vice-versa.
We now consider the 3 possible xlen values so as to allow correct
compilation for both existing targets while setting the comp
On 8/25/21 2:37 AM, David Gibson wrote:
On Tue, Aug 24, 2021 at 01:30:26PM -0300, Daniel Henrique Barboza wrote:
From: Gustavo Romero
Following up the rfebb implementation, this patch adds the EBB exception
support that are triggered by Performance Monitor alerts. This exception
occurs when
On Thu, Aug 26, 2021 at 09:43:59AM -0400, Peter Xu wrote:
> > > A simple state machine can track "has IOMMU" state. It has three states
> > > "no so far", "yes", and "no", and two events "add IOMMU" and "add device
> > > that needs to know". State diagram:
> > >
> > > n
On Mon, 30 Aug 2021 at 13:34, Peter Maydell wrote:
>
> # As noted, this does not actually cause problems on Linux, because
> # unlike FreeBSD, Linux knows what the f*ck it is doing, and just
> # ignores the upper bits exactly because of possible sign confusion.
>
> Whether that's still true a deca
On 8/30/21 9:12 AM, Matheus K. Ferst wrote:
On 24/08/2021 13:30, Daniel Henrique Barboza wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa
confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail
suspeito entre imediatamente em contato com o
On Mon, 30 Aug 2021 at 08:36, Greg Kurz wrote:
>
> On Fri, 27 Aug 2021 06:24:51 -0300
> Daniel Henrique Barboza wrote:
>
> > Signed-off-by: Daniel Henrique Barboza
> > ---
>
> We usually introduce the compat machine types for all archs in a
> single patch. One was already posted for 6.2 :
>
> ht
On 8/30/21 4:34 AM, Greg Kurz wrote:
On Fri, 27 Aug 2021 06:24:51 -0300
Daniel Henrique Barboza wrote:
Signed-off-by: Daniel Henrique Barboza
---
We usually introduce the compat machine types for all archs in a
single patch. One was already posted for 6.2 :
https://patchwork.ozlabs.org/
The code should check the opposite condition of res->iov because it will be null
if virtio_gpu_create_mapping_iov fails and actually this checking is not even
required because checking on ret covers all failing cases.
Signed-off-by: Dongwon Kim
---
hw/display/virtio-gpu.c | 2 +-
1 file changed,
On Mon, 30 Aug 2021 at 16:47, Eric Blake wrote:
>
> On Sun, Aug 29, 2021 at 10:09:19PM +0100, Peter Maydell wrote:
> > Of the various KVM_* ioctls we use via these functions, do
> > any actually have values that would result in invalid sign
> > extension here ? That is, is this fixing an existing
Hi!
I tried to run the microvm variant of qemu-system, and found out
there's very little information about it available.
In particular, I wasn't able to have a hdd in the virtual machine
using virtio-blk-device like this:
-drive file=foo,if=none,id=drv -device virtio-blk-device,drive=drv
What
On Fri, Aug 20, 2021 at 6:41 AM Jason Wang wrote:
>
>
> 在 2021/7/13 下午11:37, Andrew Melnychenko 写道:
> > Helper program. Loads eBPF RSS program and maps and passes them through
> > unix socket.
> > Libvirt may launch this helper and pass eBPF fds to qemu virtio-net.
>
>
> I wonder if this can be d
On Mon, Aug 30, 2021 at 11:14 AM Markus Armbruster wrote:
>
> Yuri Benditovich writes:
>
> > On Mon, Aug 30, 2021 at 9:10 AM Markus Armbruster wrote:
> >>
> >> Yuri Benditovich writes:
> >>
> >> > On Tue, Aug 24, 2021 at 9:41 AM Markus Armbruster
> >> > wrote:
> >> >>
> >> >> Andrew Melnichen
On 30/08/2021 17.30, Eric Blake wrote:
On Sun, Aug 29, 2021 at 07:32:10PM +0200, Thomas Huth wrote:
It's cumbersome to maintain the option help texts twice, once in the
"configure" script and once in meson_options.txt. So let's add some logic to
the configure script to read most of the help text
On 30/08/2021 17.06, Eric Blake wrote:
On Sun, Aug 29, 2021 at 07:32:09PM +0200, Thomas Huth wrote:
These trivial options can now be handled via the new generic code
that parses meson_options.txt
Signed-off-by: Thomas Huth
---
configure | 316 +
On 30/08/2021 15.33, Philippe Mathieu-Daudé wrote:
Hi Thomas,
On 8/25/21 1:00 PM, Thomas Huth wrote:
From: Daniel P. Berrangé
This splits the CI docs into one file talking about job setup and usage
and another file describing provisioning of custom runners.
Signed-off-by: Daniel P. Berrangé
On Mon, Aug 30, 2021 at 03:56:16PM +, Raphael Norwitz wrote:
> On Fri, Aug 27, 2021 at 01:51:48PM -0500, ebl...@redhat.com wrote:
> > On Fri, Aug 27, 2021 at 04:50:35PM +, Raphael Norwitz wrote:
> > > This change adds a command line option to print a line to standard out
> > > when the stor
On Mon, Aug 30, 2021 at 04:57:21PM +1000, David Gibson wrote:
> On Sun, Aug 29, 2021 at 04:09:54AM +, Joseph wrote:
> > Hi Mark, Cédric, Greg at the openbsd-ppc ML,
>
> So.. if you want to run OpenBSD on POWER10 you will definitely need
> PAPR support, because POWER10 won't support bare metal
On Fri, Aug 27, 2021 at 01:51:48PM -0500, ebl...@redhat.com wrote:
> On Fri, Aug 27, 2021 at 04:50:35PM +, Raphael Norwitz wrote:
> > This change adds a command line option to print a line to standard out
> > when the storage daemon has completed initialization and is ready to
> > serve client
Apparently commit 8d6cb100731c4d28535adbf2a3c2d1f29be3fef4 '9pfs: reduce
latency of Twalk' has introduced occasional crashes.
My first impression after looking at the backtrace: looks like the patch
itself is probably not causing this, but rather unmasked this issue (i.e.
increased the chance t
On Sun, Aug 29, 2021 at 10:09:19PM +0100, Peter Maydell wrote:
> On Thu, 5 Aug 2021 at 21:34, johannst wrote:
> >
> > Dear all,
> >
> > in my opinion the `type` argument in the kvm ioctl wrappers should be of
> > type unsigned. Please correct me if I am wrong.
>
> (Ccing Eric as our resident POSI
On Mon, 30 Aug 2021, David Gibson wrote:
On Sun, Aug 29, 2021 at 04:09:54AM +, Joseph wrote:
Hi Mark, Cédric, Greg at the openbsd-ppc ML,
It is great to talk to you. Thank you for taking on the conversation.
Right, OpenBSD implements powernv meaning it runs on bare metal on
Power9, that is
Ping.
On Fri, Aug 13, 2021 at 4:44 PM Doug Evans wrote:
> This patchset takes the original patch from Maxim,
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg569573.html
> and updates it.
>
> Option hostfwd is extended to support ipv6 addresses.
> Commands hostfwd_add, hostfwd_remove are
On Mon, 9 Aug 2021 at 11:40, Peter Maydell wrote:
>
> On Sat, 24 Jul 2021 at 10:00, Paolo Bonzini wrote:
> >
> > This new adaptor visitor takes a single field of the adaptee, and exposes it
> > with a different name.
> >
> > This will be used for QOM alias properties. Alias targets can of course
Coverity complains (CID 1460331, 1459482, 1459336, 1458895)
that we call curl_easy_setopt(), which can return an error value,
but we never check the return value.
Is it correct? Looking at the libcurl documentation, the function
does return an error status, and there's nothing that says it's
ok to
On 8/30/21 8:06 AM, Eric Blake wrote:
Does meson treat
-Dbrlapi=auto and the absence of any mention of brlapi identically?
I believe the default is right there in meson_options.txt:
option('brlapi', type : 'feature', value : 'auto',
description: 'brlapi character device driver')
with v
On Sun, Aug 29, 2021 at 07:32:10PM +0200, Thomas Huth wrote:
> It's cumbersome to maintain the option help texts twice, once in the
> "configure" script and once in meson_options.txt. So let's add some logic to
> the configure script to read most of the help texts from meson_options.txt.
>
> Signe
On 8/30/21 3:12 AM, Alistair Francis wrote:
On Sat, Aug 21, 2021 at 3:43 AM Richard Henderson
wrote:
Replace use of tcg_const_*, which makes a copy into a temp which must
be freed, with direct use of the constant. Reorg handling of $zero,
with different accessors for source and destination.
Philippe Mathieu-Daudé writes:
> There is already a section with various SEV commands / types,
> so move the SEV guest attestation together.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> qapi/misc-target.json | 81 +--
> 1 file changed, 40 insertions(
Markus Armbruster writes:
> Philippe Mathieu-Daudé writes:
>
>> Wrap long lines before 70 characters for legibility.
>>
>> Suggested-by: Markus Armbruster
>> Signed-off-by: Philippe Mathieu-Daudé
>
> Reviewed-by: Markus Armbruster
With the typo spotted by Dave fixed, of course.
>
>> ---
>>
Philippe Mathieu-Daudé writes:
> Wrap long lines before 70 characters for legibility.
>
> Suggested-by: Markus Armbruster
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Markus Armbruster
> ---
> Note: it would be nice if checkpatch enforce 70 char for json
> (or at least QAPI jso
On Sun, Aug 29, 2021 at 07:32:09PM +0200, Thomas Huth wrote:
> These trivial options can now be handled via the new generic code
> that parses meson_options.txt
>
> Signed-off-by: Thomas Huth
> ---
> configure | 316 +-
> meson_options.txt |
On Sun, Aug 29, 2021 at 07:32:08PM +0200, Thomas Huth wrote:
> To avoid double maintenance between the configure script and
> meson_options.txt, add some simple logic in the configure script
> to read the options from meson_options.txt.
>
> Signed-off-by: Thomas Huth
> ---
> configure | 24 +
On 8/30/21 9:18 AM, Philippe Mathieu-Daudé wrote:
>>
>> +AMD Secure Encrypted Virtualization (SEV)
>> +R: Connor Kuehl
>
> Is this patch still valid?
Thank you for championing it, but due to recent changes, no, it is
no longer valid.
Thank you,
Connor
On 6/16/21 10:43 PM, Philippe Mathieu-Daudé wrote:
> From: Connor Kuehl
>
> It may not be appropriate for me to take over as a maintainer at this time,
> but I would consider myself familiar with AMD SEV and what this code is
> meant to be doing as part of a VMM for launching SEV-protected guests
On Wed, Aug 25, 2021 at 2:22 AM Eugene Huang wrote:
> Signed-off-by: Eugene Huang
> ---
> ui/egl-helpers.c | 41 +
> 1 file changed, 37 insertions(+), 4 deletions(-)
>
> diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
> index 6d0cb2b5cb..ce0971422b 10064
From: Alistair Francis
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the external MIP bits.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/hw/intc/ibex_plic.h | 2 ++
hw/intc/ibe
From: Alistair Francis
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer and soft MIP bits.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: LIU Zhiwei
---
include/hw/intc/sifive_clint.h | 2 +
hw/
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