On 05/07/2021 21.21, Richard Zak wrote:
The configure script doesn't test for presence of TPM device or support. It
activates TPM support if not explicitly disabled, and disables TPM support
if explicitly enabled on Windows. With TPM support compiled in, it causes an
assertion failure on launch
On Tue, Jul 6, 2021 at 11:50 AM Kito Cheng wrote:
>
> Set I, M, A, F, D and C bit for hwcap if misa is set.
>
> V3 Changes:
> - Simplify logic of getting hwcap.
>
> V2 Changes:
> - Only set imafdc bits, sync with upstream linux kernel.
These changelogs should not be in the commit message, but sho
MSR is a 32-bit register in BookE and there is no mtmsrd instruction.
Cc: Christian Zigotzky
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f65d1e81ea..d1f482b0f3 100644
---
On 7/5/21 8:50 PM, Kito Cheng wrote:
Set I, M, A, F, D and C bit for hwcap if misa is set.
V3 Changes:
- Simplify logic of getting hwcap.
V2 Changes:
- Only set imafdc bits, sync with upstream linux kernel.
Signed-off-by: Kito Cheng
---
linux-user/elfload.c | 13 +
1 file change
Update the QEMU shipped u-boot.e500 image built from U-Boot mainline
v2021.07 release, which added eTSEC support to the QEMU ppce500 target,
via the following U-Boot series:
http://patchwork.ozlabs.org/project/uboot/list/?series=233875&state=*
The cross-compilation toolchain used to build the U
This adds eTSEC support to the PowerPC `ppce500` machine documentation.
Signed-off-by: Bin Meng
---
docs/system/ppc/ppce500.rst | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index 7a815c1881..afc58f60f5 10
On Mon, Jul 5, 2021 at 4:16 PM Bin Meng wrote:
>
> On Fri, Jul 2, 2021 at 1:20 PM Alistair Francis
> wrote:
>
> Could you add some commit message to explain this alias?
Yep, I'll add something.
>
> >
> > Signed-off-by: Alistair Francis
> > ---
> > include/hw/riscv/opentitan.h | 2 ++
> > hw/r
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Title:
unable to t
On 05.07.2021 20:46, Willian Rampazzo wrote:
Already upstream :)
Ok, thanks.
On Fri, Jun 25, 2021 at 2:39 AM Pavel Dovgalyuk
wrote:
This patch adds record/replay test which boots Linux
kernel on ppc64 platform. The test uses kernel binaries
taken from boot_linux_console test.
Signed-off-
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Title:
s390x guest
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Title:
virsh domfs
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Title:
Support for
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Title:
Qemu PPC64
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Title:
fstrim not
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Title:
qemu 4.2 do
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Title:
multiseat:
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Title:
formating v
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Title:
cannot run
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Title:
MacOS host
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Title:
Switching f
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Title:
Multiple (R
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Title:
"nr_entries
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Title:
[Feature Re
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Title:
powerpc-non
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Bug in qemu
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Title:
qemu-arm ha
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qemu-system
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Title:
Using qemu-
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Title:
qemu window
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Title:
cannot run
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Title:
Problems re
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Title:
TCG doesn't
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qemu-arm-st
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KVM Win 10
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Title:
file transf
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Title:
[ppc64le] q
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Title:
"semtimedop
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Title:
target_read
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Title:
it always c
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Title:
Missing 'cm
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Title:
VFIO passth
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Title:
Intermitten
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Title:
MIPS64EL em
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Title:
building pl
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USB host de
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make-check
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Title:
error: argu
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CGA Mode 6
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Title:
After insta
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Ti
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Title:
include
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include/qem
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Title:
Provide SMB
Hi team of qemu
I see the qemu6.0 has supported for raspberryPick 2B. but i want use it for
raspberrypi 3/3B/4B. So can you tell me about raspberrypi 3/3B/4B plan ?
| |
殷冬
|
|
邮箱：yindongb...@126.com
|
签名由 网易邮箱大师 定制
Set I, M, A, F, D and C bit for hwcap if misa is set.
V3 Changes:
- Simplify logic of getting hwcap.
V2 Changes:
- Only set imafdc bits, sync with upstream linux kernel.
Signed-off-by: Kito Cheng
---
linux-user/elfload.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/linux-
On 7/4/21 11:43 PM, Kito Cheng wrote:
+static uint32_t get_elf_hwcap(void)
+{
+RISCVCPU *cpu = RISCV_CPU(thread_cpu);
+uint32_t hwcap = 0;
+
+#define MISA_BIT(EXT) (1 << (EXT - 'A'))
+#define GET_EXT(EXT) \
+do { \
+
On Mon, 2021-07-05 at 20:47 -0400, shashi.mall...@linaro.org wrote:
> On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > shashi.mall...@linaro.org> wrote:
> > > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > > ITS
> >
在 2021/6/29 下午11:29, Laurent Vivier 写道:
When the card is plugged back, reset the partially_hotplugged flag to false
Bug: https://bugzilla.redhat.com/show_bug.cgi?id=1787194
Signed-off-by: Laurent Vivier
---
hw/net/virtio-net.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/virt
On Mon, Jul 05, 2021 at 11:31:13AM -0300, Bruno Piazera Larsen wrote:
>
> On 05/07/2021 01:24, David Gibson wrote:
>
> > > Changed hash32 address translation to use the supplied mmu_idx, instead
> > > of using what was stored in the msr, for parity purposes (radix64
> > > already uses that).
>
>
> On Jul 5, 2021, at 4:07 PM, Paolo Bonzini wrote:
>
> Well, you're not using $ICON at all but I can clean that up myself. Thanks
> for testing.
>
> Paolo
>
Please send me the cleaned up patch for testing once you complete it. Thank you.
> Il lun 5 lug 2021, 21:53 John Arbuckle ha scrit
On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
> > translation which triggers an LPI via INT command as well as write
> > to GIT
Add new file to target/hexagon/meson.build
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/decode_ext_mmvec.h | 24
target/hexagon/decode.c | 24 +++-
target/hexagon/mmvec/decode_ext_mmvec.c | 235
target/hexagon/meson.build
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/vector_add_int.c | 61 ++
tests/tcg/hexagon/Makefile.target | 3 ++
2 files changed, 64 insertions(+)
create mode 100644 tests/tcg/hexagon/vector_add_int.c
diff --git a/tests/tcg/hexagon/vector_add_int.c
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_regs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h
index f291911..e1b3149 100644
--- a/target/hexagon/hex_regs.h
+++ b/target/hexagon/hex_regs.h
@@ -76,6 +76,7 @@ enum {
/* Use
Functions to support scatter/gather
Add new file to target/hexagon/meson.build
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.h | 1 +
target/hexagon/mmvec/system_ext_mmvec.h | 35 ++
target/hexagon/arch.c | 9 +++
target/hexagon/mmvec/syst
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 54
target/hexagon/genptr.c| 15
target/hexagon/translate.c | 199 +
3 files changed, 268 insertions(+)
diff --git a/target/hexagon/translate.h b/target/hexagon/tran
Tests for
packet semantics
vector loads (aligned and unaligned)
vector stores (aligned and unaligned)
vector masked stores
vector operations
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.c | 331 ++
tests/tcg/hexagon/Mak
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_dectree_import.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/hexagon/gen_dectree_import.c
b/target/hexagon/gen_dectree_import.c
index 5b7ecfc..2374030 100644
--- a/target/hexagon/gen_dectree_import.c
+++ b/target/
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_histogram_input.h | 717
tests/tcg/hexagon/hvx_histogram_row.h | 24 ++
tests/tcg/hexagon/hvx_histogram.c | 88
tests/tcg/hexagon/Makefile.target | 5 +
tests/tcg/hexagon/hvx_histogram_
Signed-off-by: Taylor Simpson
---
target/hexagon/gdbstub.c | 66
1 file changed, 66 insertions(+)
diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c
index 9c8c04c..b804e97 100644
--- a/target/hexagon/gdbstub.c
+++ b/target/hexagon/gd
Signed-off-by: Taylor Simpson
---
target/hexagon/decode.c | 4 +
target/hexagon/imported/allextenc.def| 20 +
target/hexagon/imported/encode.def | 1 +
target/hexagon/imported/mmvec/encode_ext.def | 794 +++
4 files changed, 819
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/scatter_gather.c | 1011
tests/tcg/hexagon/Makefile.target |2 +
2 files changed, 1013 insertions(+)
create mode 100644 tests/tcg/hexagon/scatter_gather.c
diff --git a/tests/tcg/hexagon/scatter_gather.
macros to interface with the generator
macros referenced in instruction semantics
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 22 ++
target/hexagon/mmvec/macros.h | 478 ++
2 files changed, 500 insertions(+)
create mode 100644 targe
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_helper_funcs.py | 111 ++--
target/hexagon/gen_helper_protos.py | 16 ++-
target/hexagon/gen_tcg_funcs.py | 254 ++--
3 files changed, 359 insertions(+), 22 deletions(-)
diff --git a/target/hex
Signed-off-by: Taylor Simpson
---
target/hexagon/attribs_def.h.inc | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 3815509..4138a7a 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexa
This series adds support for the Hexagon Vector eXtensions (HVX)
These instructions are documented here
https://developer.qualcomm.com/downloads/qualcomm-hexagon-v66-hvx-programmer-s-reference-manual
Hexagon HVX is a wide vector engine with 128 byte vectors.
See patch 01 Hexagon HVX README for m
Imported from the Hexagon architecture library
imported/allext_macros.def Top level macro include for all extensions
imported/macros.def Scalar core macros (some HVX here)
imported/mmvec/macros.defHVX macro definitions
The macro definition files specify instru
Add HVX support to the semantics generator
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_semantics.c | 33 +
target/hexagon/hex_common.py | 9 -
2 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/gen_semantics.c b/targe
Signed-off-by: Taylor Simpson
---
target/hexagon/README | 83 ++-
1 file changed, 82 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/README b/target/hexagon/README
index b0b2435..9a57802 100644
--- a/target/hexagon/README
+++ b/target/hexa
Commit vector stores (masked and scatter/gather)
Log vector register writes
Add the execution counters to the debug log
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 1 +
target/hexagon/op_helper.c | 51 --
2 files changed, 50 inserti
> -Original Message-
> From: Philippe Mathieu-Daudé On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Sunday, July 4, 2021 12:38 PM
> To: qemu-devel@nongnu.org
> Cc: Richard Henderson ; Jiaxun Yang
> ; Laurent Vivier ; Aleksandar
> Rikalo ; Taylor Simpson
> ; Philippe Mathieu-Daudé ;
> Aurel
> -Original Message-
> From: Philippe Mathieu-Daudé On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Sunday, July 4, 2021 12:38 PM
> To: qemu-devel@nongnu.org
> Cc: Richard Henderson ; Jiaxun Yang
> ; Laurent Vivier ; Aleksandar
> Rikalo ; Taylor Simpson
> ; Philippe Mathieu-Daudé ;
> Aurel
From: Philippe Mathieu-Daudé
Per the DP83932C datasheet from July 1995:
4.0 SONIC Registers
4.1 THE CAM UNIT
The Content Addressable Memory (CAM) consists of sixteen
48-bit entries for complete address filtering of network
packets. Each entry corresponds to a 48-bit destination
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 44a1955015..cc7c001edb 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -820,8 +82
From: Philippe Mathieu-Daudé
Instead of accessing N registers via a single address_space API
call using a temporary buffer (stored in the device state) and
updating each register, move the address_space call in the
register put/get. The load/store and word size checks are moved
to put/get too. Th
Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" set
.impl.min_access_size
and .impl.max_access_size to 4 to try and fix the Linux jazzsonic driver which
uses
32-bit accesses.
The problem with forcing the register access to 32-bit in this way is that
since the
dp8393x uses 16-bit registe
(was: [RFC PATCH 0/6] dp8393x: Housekeeping)
This is an updated version of Phil's patchset previously posted at
https://lists.gnu.org/archive/html/qemu-devel/2021-07/msg00440.html which
I've tested locally on Linux/m68k, MacOS and NetBSD/arc.
Signed-off-by: Mark Cave-Ayland
Changes since RFC:
On Mon, Jul 05, 2021 at 10:41:55PM +0100, Daniel P. Berrangé wrote:
> On Mon, Jul 05, 2021 at 09:27:56PM +0100, Alex Bennée wrote:
> >
> > Daniel P. Berrangé writes:
> >
> > > This is the fully expanded list of build pre-requisites QEMU can
> > > conceivably use in any scenario.
> > >
> > > Revi
On Mon, Jul 05, 2021 at 09:27:56PM +0100, Alex Bennée wrote:
>
> Daniel P. Berrangé writes:
>
> > This is the fully expanded list of build pre-requisites QEMU can
> > conceivably use in any scenario.
> >
> > Reviewed-by: Philippe Mathieu-Daudé
> > Signed-off-by: Daniel P. Berrangé
> > ---
> >
On 7/5/21 9:33 PM, Mark Cave-Ayland wrote:
> On 05/07/2021 08:52, Mark Cave-Ayland wrote:
>
>> I think the problem is because of the interaction of
>> .impl.max_access_size = 2 and the it_shift property specifying a
>> stride of 4 bytes: when the 4 byte access is split into 2 x 2 byte
>> accesses
On Mon, Jul 5, 2021 at 6:20 PM Philippe Mathieu-Daudé wrote:
>
> On 7/5/21 11:10 PM, Willian Rampazzo wrote:
> > Hi Eric,
> >
> > On Mon, Jul 5, 2021 at 4:55 AM Eric Auger wrote:
> >>
> >> Hi Wainer,
> >>
> >> On 7/1/21 1:22 AM, Wainer dos Santos Moschetta wrote:
> >>> Hi,
> >>>
> >>> On 6/29/21
On 7/5/21 3:44 AM, Finn Thain wrote:
> On Sun, 4 Jul 2021, Mark Cave-Ayland wrote:
>
>> Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that all
>> accesses
>> to the registers were 32-bit
>
> As I said, that assumption was not made there.
>
> If commit 3fe9a838ec is deficient
On 7/5/21 11:10 PM, Willian Rampazzo wrote:
> Hi Eric,
>
> On Mon, Jul 5, 2021 at 4:55 AM Eric Auger wrote:
>>
>> Hi Wainer,
>>
>> On 7/1/21 1:22 AM, Wainer dos Santos Moschetta wrote:
>>> Hi,
>>>
>>> On 6/29/21 5:17 PM, Eric Auger wrote:
Hi Cleber, all,
On 6/29/21 4:36 PM, Eric Au
On Tue, Jun 29, 2021 at 11:36 AM Eric Auger wrote:
>
> From: Wainer dos Santos Moschetta
>
> As the KNOWN_DISTROS grows, more loosely methods will be created in
> the avocado_qemu/__init__.py file.
>
> Let's refactor the code so that KNOWN_DISTROS and related methods are
> packaged in a class
>
>
On Tue, Jun 29, 2021 at 11:36 AM Eric Auger wrote:
>
> Add Intel IOMMU functional tests based on fedora 31.
> Different configs are checked:
> - strict
> - caching mode, strict
> - passthrough.
>
> Signed-off-by: Eric Auger
> Acked-by: Peter Xu
> ---
> tests/acceptance/intel_iommu.py | 115
Hi Eric,
On Mon, Jul 5, 2021 at 4:55 AM Eric Auger wrote:
>
> Hi Wainer,
>
> On 7/1/21 1:22 AM, Wainer dos Santos Moschetta wrote:
> > Hi,
> >
> > On 6/29/21 5:17 PM, Eric Auger wrote:
> >> Hi Cleber, all,
> >>
> >> On 6/29/21 4:36 PM, Eric Auger wrote:
> >>> This series adds ARM SMMU and Intel I
On Tue, Jun 29, 2021 at 11:36 AM Eric Auger wrote:
>
> Add new tests checking the good behavior of the SMMUv3 protecting
> 2 virtio pci devices (block and net). We check the guest boots and
> we are able to install a package. Different guest configs are tested:
> standard, passthrough an strict=0.
Hi Eric,
On Mon, Jul 5, 2021 at 5:00 AM Eric Auger wrote:
>
> Hi Wainer,
>
> On 7/1/21 8:13 PM, Wainer dos Santos Moschetta wrote:
> > Hi,
> >
> > On 6/29/21 11:36 AM, Eric Auger wrote:
> >> Add new tests checking the good behavior of the SMMUv3 protecting
> >> 2 virtio pci devices (block and net
For SIGILL, SIGFPE and SIGTRAP the PSW must point after the
instruction, and at the instruction for other signals. Currently under
qemu-user for SIGFILL and SIGFPE it points at the instruction.
Fix by advancing psw.addr for these signals.
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/319
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