The loop is performing a simple boolean test for the existence
of a BP_CPU breakpoint at EIP. Plus it gets the iteration wrong,
if we happen to have a BP_GDB breakpoint at the same address.
We have a function for this: cpu_breakpoint_test.
Signed-off-by: Richard Henderson
---
target/i386/tcg/s
Prepare for receiving it as a pointer input.
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 84 +-
1 file changed, 43 insertions(+), 41 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 20c5062730..66e9882422 1
I've reached a point where *all* targets must use the translator loop.
Do that.
r~
Richard Henderson (3):
target/avr: Add DisasContextBase to DisasContext
target/avr: Change ctx to DisasContext* in gen_intermediate_code
target/avr: Convert to TranslatorOps
target/avr/translate.c | 288 +
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 238 +++--
1 file changed, 132 insertions(+), 106 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 66e9882422..72117bf3b9 100644
--- a/target/avr/translate.c
+++ b/tar
Migrate the bstate, tb and singlestep_enabled fields
from DisasContext into the base.
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 58 +-
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/t
Direct assignments to env during translation do not work.
As it happens, the only way we can get here is if env->pc
is already set to dc->pc. We will trap on the first insn
we execute anywhere on the page.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 3 ++-
1 file changed, 2
Migrate the is_jmp, tb and singlestep_enabled fields
from DisasContext into the base.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 51 +---
1 file changed, 27 insertions(+), 24 deletions(-)
diff --git a/target/nios2/translate.c b/target/nio
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 129 +--
1 file changed, 68 insertions(+), 61 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 31653b7912..e2c8151193 100644
--- a/target/nios2/translate.c
+++ b
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index ce4a4c40aa..3f4027ff1b 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -753,7
We do not need to copy this into DisasContext.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 388fae93a2..39538e1870 100644
--- a/target/nios2/t
The only semantic of DISAS_TB_JUMP is that we've done goto_tb,
which is the same as DISAS_NORETURN -- we've exited the tb.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/nios2/translate.c b/target/n
We do not need to copy this into DisasContext.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 73 +++-
1 file changed, 34 insertions(+), 39 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 39538e1870..6bdd38
I've reached a point where *all* targets must use the translator loop.
Do that, plus some other obvious cleanups.
r~
Richard Henderson (7):
target/nios2: Replace DISAS_TB_JUMP with DISAS_NORETURN
target/nios2: Use global cpu_env
target/nios2: Use global cpu_R
target/nios2: Add DisasCo
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Title:
-device doe
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** Changed in: qemu
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Title:
Reading sec
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Title:
Nested VMX
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Title:
qemu user c
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Title:
Qemu hangs
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Title:
Initrd not
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Title:
Listing the
This function should have been updated for vector types
when they were introduced.
Fixes: d2fd745fe8b
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/367
Cc: qemu-sta...@nongnu.org
Tested-by: Stefan Weil
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c
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Title:
qemu-guest-
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Title:
add '--targ
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Title:
Mouse leave
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Title:
amdgpu pass
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Title:
slight scre
s/pull-tcg-20210619-2
for you to fetch changes up to 1c9638667b7068539dc5783c9428d588b14162ea:
util/oslib-win32: Fix fatal assertion in qemu_try_memalign (2021-06-19
14:51:51 -0700)
TCI cleanup and re-encoding
Fixes for #367 and
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Title:
SVM instruc
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Title:
Failed to e
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Title:
qemu-ga fsf
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Title:
qemu 3.1/i3
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Title:
qemu can't
Indirect jumps can use this to avoid returning to the main loop.
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index e4cbc35ebd..8a8d62f11b 100644
--- a/target/cris/translate.c
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Title:
drive-backu
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 19 ++-
target/cris/translate_v10.c.inc | 6 +++---
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 8c24053f5e..3515c21b7b 100644
--- a/
This is better than branch around assignment.
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 3515c21b7b..e4cbc35ebd 100644
--- a/target/cris/translate
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Title:
VM running
Signed-off-by: Richard Henderson
---
target/cris/helper.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/cris/helper.h b/target/cris/helper.h
index 20d21c4358..3abf608682 100644
--- a/target/cris/helper.h
+++ b/target/cris/helper.h
@@ -1,4 +1,4 @@
-DEF_HELPER_2(raise_e
After we've raised the exception, we have left the TB.
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 5 +++--
target/cris/translate_v10.c.inc | 3 ++-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 2
The only semantic of DISAS_TB_JUMP is that we've done goto_tb,
which is the same as DISAS_NORETURN -- we've exited the tb.
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/cris/translate.c b/target/cris
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 320 ++--
1 file changed, 177 insertions(+), 143 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 24dbae6d58..8c24053f5e 100644
--- a/target/cris/translate.c
+++ b/
Migrate the is_jmp, tb and singlestep_enabled fields
from DisasContext into the base.
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 49 +
target/cris/translate_v10.c.inc | 4 +--
2 files changed, 27 insertions(+), 26 deletions(-)
diff --
I've reached a point where *all* targets must use the translator loop.
Do that, plus some other obvious cleanups.
r~
Richard Henderson (9):
target/cris: Add DisasContextBase to DisasContext
target/cris: Replace DISAS_TB_JUMP with DISAS_NORETURN
target/cris: Mark exceptions as DISAS_NORE
This value is unused.
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index f8b574b0b6..24dbae6d58 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -55,7 +55,6
The Last Branch Recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors which records a running trace of the most
recent branches taken by the processor in the LBR stack. This option
indicates the LBR format to enable for guest perf.
The LBR feature is enabled if below cond
The DEFINE_PROP_UINT64_CHECKMASK maro applies certain mask check agaist
user-supplied property value, reject the value if it violates the bitmask.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
hw/core/qdev-properties.c| 19 +++
include/hw/
Excerpts from David Gibson's message of June 19, 2021 7:26 pm:
> On Tue, Jun 15, 2021 at 02:41:07PM +1000, Nicholas Piggin wrote:
>> There are several new L1D cache flush bits added to the hcall which reflect
>> hardware security features for speculative cache access issues.
>>
>> These behaviours
Bah. Somehow I overwrote a minor fix for
tcg: Allocate sufficient storage in temp_allocate_frame
Will update and repost.
r~
On Sat, Jun 19, 2021 at 10:45:17AM +0200, Philippe Mathieu-Daudé wrote:
> On 6/18/21 1:37 PM, Igor Mammedov wrote:
> > On Wed, 16 Jun 2021 22:43:24 +0200
> > Philippe Mathieu-Daudé wrote:
> >
> >> pc_madt_cpu_entry() is specific to QEMU 'PC' machines,
> >> move it to acpi-pc.c.
> >>
> >> Signed-o
19.06.2021 15:21, Vladimir Sementsov-Ogievskiy wrote:
14.06.2021 11:17, Emanuele Giuseppe Esposito wrote:
On 14/06/2021 10:11, Emanuele Giuseppe Esposito wrote:
This serie of patches bring thread safety to the smaller APIs used by
block-copy, namely ratelimit, progressmeter, co-shared-resourc
On Wed, May 19, 2021 at 4:26 PM Peter Lieven wrote:
>
> librbd supports 1 byte alignment for all aio operations.
>
> Currently, there is no API call to query limits from the ceph backend.
> So drop the bdrv_refresh_limits completely until there is such an API call.
>
> Signed-off-by: Peter Lieven
14.06.2021 10:33, Emanuele Giuseppe Esposito wrote:
By adding acquire/release pairs, we ensure that .ret and .error_is_read
fields are written by block_copy_dirty_clusters before .finished is true.
And that they are read by API user after .finished is true.
The atomic here are necessary beca
On Wed, May 19, 2021 at 4:29 PM Peter Lieven wrote:
>
> Signed-off-by: Peter Lieven
> ---
> block/rbd.c | 18 +++---
> 1 file changed, 7 insertions(+), 11 deletions(-)
>
> diff --git a/block/rbd.c b/block/rbd.c
> index 6b1cbe1d75..b4caea4f1b 100644
> --- a/block/rbd.c
> +++ b/block/r
On Wed, May 19, 2021 at 4:26 PM Peter Lieven wrote:
>
> in case the image size changed we should adjust our internally stored size as
> well.
>
> Signed-off-by: Peter Lieven
> ---
> block/rbd.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/block/rbd.c b/block/rbd.c
> index b4caea4f1b
OSS-Fuzz confirms this is fixed: https://bugs.chromium.org/p/oss-
fuzz/issues/detail?id=30574#c4
** Changed in: qemu
Status: Confirmed => Fix Committed
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On Thu, Jun 17, 2021 at 6:05 PM Or Ozeri wrote:
>
> Starting from ceph Pacific, RBD has built-in support for image-level
> encryption.
> Currently supported formats are LUKS version 1 and 2.
>
> There are 2 new relevant librbd APIs for controlling encryption, both expect
> an
> open image contex
Make the PF flag behave like real hardware by always running the
periodic timer without regard to the setting of the PIE bit, so
that the PF will be set when the period expires even if an interrupt
will not be raised. This behavior is documented on page 16 of the
MC146818A advance information data
14.06.2021 10:33, Emanuele Giuseppe Esposito wrote:
Add a CoMutex to protect concurrent access of block-copy
data structures.
This mutex also protects .copy_bitmap, because its thread-safe
API does not prevent it from assigning two tasks to the same
bitmap region.
.finished, .cancelled and read
14.06.2021 10:33, Emanuele Giuseppe Esposito wrote:
--- a/block/block-copy.c
+++ b/block/block-copy.c
@@ -52,29 +52,35 @@ typedef struct BlockCopyCallState {
/* Coroutine where async block-copy is running */
Coroutine *co;
-/* To reference all call states from BlockCopyState */
Ping. Cc paolo, ed.
This is the last unreviewed patch in this series, and the one that sparked the work in the
first place.
r~
On 5/26/21 9:13 PM, Richard Henderson wrote:
The FSR and MXCSR DE flags have the semantics of the new flag.
We get to remove a big fixme in update_mxcsr_from_sse_st
14.06.2021 10:33, Emanuele Giuseppe Esposito wrote:
@@ -158,8 +183,9 @@ static BlockCopyTask *block_copy_task_create(BlockCopyState
*s,
int64_t offset, int64_t bytes)
{
BlockCopyTask *task;
-int64_t max_chunk = MIN_NON_ZERO(s->copy_size,
From: Alessandro Di Federico
This commit moves into a separate file routines used to manipulate
TCGCond. These will be employed by the idef-parser.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
Message-Id: <20210619093713.1845446-2-ale.q...@rev.ng>
Signed-off-by: Richard
We had a single ATOMIC_MMU_LOOKUP macro that probed for
read+write on all atomic ops. This is incorrect for
plain atomic load and atomic store.
For user-only, we rely on the host page permissions.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/390
Reviewed-by: Alex Bennée
Signed-off-by
Assume that we'll have fewer temps allocated after
restarting with a fewer number of instructions.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 47cc66f159..
These macros are only used in one place. By expanding,
we get to apply some common-subexpression elimination
and create some local variables.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci.c | 165
The longest test at the moment seems to be a (slower)
aarch64 host, for which test-mmap takes 64 seconds.
Tested-by: Philippe Mathieu-Daudé
Acked-by: Alex Bennée
Reviewed-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
configure | 3 ++
We can share this code between 32-bit and 64-bit loads and stores.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci.c | 183 +-
1 file changed, 71 insertions(+), 112 deletions(
From: Stefan Weil
The function is called with alignment == 0 which caused an assertion.
Use the code from oslib-posix.c to fix that regression.
Fixes: ed6f53f9ca9
Signed-off-by: Stefan Weil
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210611105846.347954-1...@weilnetz.de>
Signed-off-by:
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 12 +--
tcg/tci.c| 44
tcg/tci/tcg-target.c.inc | 9
3 files changed, 59 insertions(+)
This reverts commit dc09f047eddec8f4a1991c4f5f4a428d7aa3f2c0.
For tcg, tracepoints are expanded inline in tcg opcodes.
Using a helper which generates a second tracepoint is incorrect.
For system mode, the extraction and re-packing of MemOp and mmu_idx
lost the alignment information from MemOp. S
We should not be aligning the offset in temp_allocate_frame,
because the odd offset produces an aligned address in the end.
Instead, pass the logical offset into tcg_set_frame and add
the stack bias last.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Hender
When this opcode is not available in the backend, tcg middle-end
will expand this as a series of 5 opcodes. So implementing this
saves bytecode space.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 4 ++--
19.06.2021 18:23, Vladimir Sementsov-Ogievskiy wrote:
typedef struct BlockCopyTask {
AioTask task;
+ /*
+ * IN parameters. Initialized in block_copy_task_create()
+ * and never changed.
+ */
That's just not true for method field :(
I think, we just need to document that
We already had the 32-bit versions for a 32-bit host; expand this
to 64-bit hosts as well. The 64-bit opcodes are new.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 8
tcg/tci.c|
We already had mulu2_i32 for a 32-bit host; expand this to 64-bit
hosts as well. The muls2_i32 and the 64-bit opcodes are new.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 8
tcg/tci.c
Inline it into its one caller, tci_write_reg64.
Drop the asserts that are redundant with tcg_read_r.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff -
This removes all of the problems with unaligned accesses
to the bytecode stream.
With an 8-bit opcode at the bottom, we have 24 bits remaining,
which are generally split into 6 4-bit slots. This fits well
with the maximum length opcodes, e.g. INDEX_op_add2_i32, which
have 6 register operands.
We
This function should have been updated for vector types
when they were introduced.
Fixes: d2fd745fe8b
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/367
Cc: qemu-sta...@nongnu.org
Tested-by: Stefan Weil
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c
This operation is critical to staying within the interpretation
loop longer, which avoids the overhead of setup and teardown for
many TBs.
The check in tcg_prologue_init is disabled because TCI does
want to use NULL to indicate exit, as opposed to branching to
a real epilogue.
Tested-by: Philippe
The encoding planned for tci does not have enough room for
brcond2, with 4 registers and a condition as input as well
as the label. Resolve the condition into TCG_REG_TMP, and
relax brcond to one register plus a label, considering the
condition to always be reg != 0.
Tested-by: Philippe Mathieu-D
As the only call-clobbered regs for TCI, these should
receive the least priority.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tci/
Wrap guest memory operations for tci like we do for cpu_ld*_data.
We cannot actually use the cpu_ldst.h interface without duplicating
the memory trace operations performed within, which will already
have been expanded into the tcg opcode stream.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Phi
The current setting is much too pessimistic. Indicating only
the one or two registers that are actually assigned after a
call should avoid unnecessary movement between the register
array and the stack array.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ri
These were already present in tcg-target.c.inc,
but not in the interpreter.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 20 ++--
tcg/tci.c| 40 +
We're going to change how to look up the call flags from a TCGop,
so extract it as a helper.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 5 +
tcg/optimize.c | 3 ++-
tcg/tcg.c | 14 ++
Add libffi as a build requirement for TCI.
Add libffi to the dockerfiles to satisfy that requirement.
Construct an ffi_cif structure for each unique typemask.
Record the result in a separate hash table for later lookup;
this allows helper_table to stay const.
Tested-by: Philippe Mathieu-Daudé
Re
We're about to adjust the offset range on host memory ops,
and the format of branches. Both will require a temporary.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 1 +
tcg/tci/tcg-target.c.inc | 1 +
2 fi
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 8
tcg/tci.c| 42
tcg/tci/tcg-target.c.inc | 32 ++
3 files change
This requires adjusting where arguments are stored.
Place them on the stack at left-aligned positions.
Adjust the stack frame to be at entirely positive offsets.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h
As noted by qemu-plugins.h, plugins can neither read nor write
guest registers.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-helpers.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tc
This will give us both flags and typemask for use later.
We also fix a dumping bug, wherein calls generated for plugins
fail tcg_find_helper and print (null) instead of either a name
or the raw function pointer.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by
We will shortly be interested in distinguishing pointers
from integers in the helper's declaration, as well as a
true void return. We currently have two parallel 1 bit
fields; merge them and expand to a 3 bit field.
Our current maximum is 7 helper arguments, plus the return
makes 8 * 3 = 24 bits
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 5 +
tcg/tcg.c | 5 ++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h
index 6ab8910210..92c91dc
Let the compiler decide on inlining.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.
s/pull-tcg-20210619
for you to fetch changes up to 8169ec35eb766a12ad0ae898119060fde148ab61:
util/oslib-win32: Fix fatal assertion in qemu_try_memalign (2021-06-19
11:09:11 -0700)
TCI cleanup and re-encoding
Fixes for #367 and
As noted by qemu-plugins.h, enum qemu_plugin_cb_flags is
currently unused -- plugins can neither read nor write
guest registers.
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-helpers.h | 1 -
include/qemu/plugin.h | 1 -
accel/tcg/plugin-gen.c
On 6/17/21 7:43 PM, Philippe Mathieu-Daudé wrote:
> Fixes and cleanup accumulated during the last month.
> Nothing particularly exciting :/
>
> Please review,
>
> Phil.
>
> Philippe Mathieu-Daudé (9):
> target/mips: Do not abort on invalid instruction
> target/mips: Fix more TCG temporary le
On 6/19/21 10:48 AM, Philippe Mathieu-Daudé wrote:
+case INDEX_op_tci_movi:
+tci_args_ri(insn, &r0, &i1);
+info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "",
Missing space in format: "%s, 0x%"
Squashed, thanks.
r~
On 6/17/21 7:46 PM, Philippe Mathieu-Daudé wrote:
> Merge MSA32 & MSA64.
>
> Philippe Mathieu-Daudé (2):
> target/mips: Remove pointless gen_msa()
> target/mips: Merge msa32/msa64 decodetree definitions
>
> target/mips/tcg/{msa32.decode => msa.decode} | 8 +---
> target/mips/tcg/msa64.d
On 5/29/21 6:54 PM, Philippe Mathieu-Daudé wrote:
> Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
> Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":
>
> If the Module/ASE is not implemented, executing such an instruction
> must cause a Reserved Instructio
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