Re: [PATCH 15/55] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations

On 6/7/21 6:57 PM, Peter Maydell wrote: > Currently the ARM SVE helper code defines locally some utility > functions for swapping 16-bit halfwords within 32-bit or 64-bit > values and for swapping 32-bit words within 64-bit values, > parallel to the byte-swapping bswap16/32/64 functions. > > We wa

Re: [PATCH 31/55] include/qemu/int128.h: Add function to create Int128 from int64_t

On 6/7/21 6:57 PM, Peter Maydell wrote: > int128_make64() creates an Int128 from an unsigned 64 bit value; add > a function int128_makes64() creating an Int128 from a signed 64 bit > value. > > Signed-off-by: Peter Maydell > --- > include/qemu/int128.h | 10 ++ > 1 file changed, 10 inser

Re: [RFC PATCH] scripts/checkpatch: roll diff tweaking into checkpatch itself

On 6/7/21 7:18 PM, Alex Bennée wrote: > Rather than relying on external tweaks lets just do it inside > checkpatch's direct commitish handling which is QEMU specific code > anyway. > > Suggested-by: Daniel P. Berrangé > Signed-off-by: Alex Bennée > --- > .gitlab-ci.d/static_checks.yml | 3 --- >

Re: [PATCH] docs/interop/live-block-operations: Do not hard-code the QEMU binary name

On 6/7/21 7:23 PM, Thomas Huth wrote: > In downstream, we want to use a different name for the QEMU binary, > and some people might also use the docs for non-x86 binaries, that's > why we already created the |qemu_system| placeholder in the past. > Use it now in the live-block-operations doc, too.

Re: [PATCH] docs/tools/virtiofsd.rst: Do not hard-code the QEMU binary name

On 6/7/21 7:42 PM, Thomas Huth wrote: > In downstream, we want to use a different name for the QEMU binary, > and some people might also use the docs for non-x86 binaries, that's > why we already created the |qemu_system| placeholder in the past. > Use it now in the virtiofsd doc, too. > > Signed-

Re: [PATCH v6 4/4] Jobs based on custom runners: add job definitions for QEMU's machines

Hi Alex, Stefan, On 6/8/21 5:14 AM, Cleber Rosa wrote: > The QEMU project has two machines (aarch64 and s390x) that can be used > for jobs that do build and run tests. AFAIK there is more hardware available to the project, so I'm wondering what happened to the rest, is it a deliberate choice to s

[RFC PATCH v3 4/4] plugins/cache: Added FIFO and LRU eviction policies.

Implemented FIFO and LRU eviction policies. Now one of the three eviction policies can be chosen as an argument. On not specifying an argument, LRU is used by default. Signed-off-by: Mahmoud Mandour --- contrib/plugins/cache.c | 205 +--- 1 file changed, 192 i

[RFC PATCH v3 3/4] plugins/cache: Enabled cache parameterization

Made both icache and dcache configurable through plugin arguments. Signed-off-by: Mahmoud Mandour --- contrib/plugins/cache.c | 44 +++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c index 715

[RFC PATCH v3 1/4] plugins/api: expose symbol lookup to plugins

From: Alex Bennée This is a quality of life helper for plugins so they don't need to re-implement symbol lookup when dumping an address. The strings are constant so don't need to be duplicated. One minor tweak is to return NULL instead of a zero length string to show lookup failed. Signed-off-by

[RFC PATCH v3 2/4] plugins: Added a new cache modelling plugin.

Added a cache modelling plugin that uses a static configuration used in many of the commercial microprocessors and uses random eviction policy. The purpose of the plugin is to identify the most cache-thrashing instructions for both instruction cache and data cache. Signed-off-by: Mahmoud Mandour

[RFC PATCH v3 0/4] Cache TCG plugin & symbol-resolution API

This RFC series introduces a new cache TCG plugin that models separate L1 data cache and L1 instruction cache and uses one shared cache for all the cores. It also includes a commit by Alex that adds an API call that resolves the symbol of an insn. The original RFC patch posted by Alex Bennée incl

Re: [PATCH 10/55] target/arm: Add framework for MVE decode

On 6/7/21 9:57 AM, Peter Maydell wrote: Add the framework for decoding MVE insns, with the necessary new files and the meson.build rules, but no actual content yet. Signed-off-by: Peter Maydell --- target/arm/translate-a32.h | 1 + target/arm/mve.decode | 20 targe

Re: [PATCH 09/55] target/arm: Implement MVE LETP insn

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE LETP insn. This is like the existing LE loop-end insn, but it must perform an FPU-enabled check, and on loop-exit it resets LTPSIZE to 4. To accommodate the requirement to do something on loop-exit, we drop the use of condlabel and inste

Re: [PATCH v7 06/10] vhost:add support for configure interrupt

On Thu, Jun 3, 2021 at 2:28 PM Jason Wang wrote: > > > 在 2021/6/2 上午11:47, Cindy Lu 写道: > > Add configure notifier support in vhost and virtio driver > > When backend support VIRTIO_NET_F_STATUS, > > > So config interrupt is the basic facility of the virtio device. We need > to make the code not s

[PATCH v6 4/4] Jobs based on custom runners: add job definitions for QEMU's machines

The QEMU project has two machines (aarch64 and s390x) that can be used for jobs that do build and run tests. This introduces those jobs, which are a mapping of custom scripts used for the same purpose. Signed-off-by: Cleber Rosa --- .gitlab-ci.d/custom-runners.yml | 208

[PATCH v6 3/4] Jobs based on custom runners: docs and gitlab-runner setup playbook

To have the jobs dispatched to custom runners, gitlab-runner must be installed, active as a service and properly configured. The variables file and playbook introduced here should help with those steps. The playbook introduced here covers the Linux distributions and has been primarily tested on O

[PATCH v6 1/4] Jobs based on custom runners: documentation and configuration placeholder

As described in the included documentation, the "custom runner" jobs extend the GitLab CI jobs already in place. One of their primary goals of catching and preventing regressions on a wider number of host systems than the ones provided by GitLab's shared runners. This sets the stage in which othe

[PATCH v6 2/4] Jobs based on custom runners: build environment docs and playbook

To run basic jobs on custom runners, the environment needs to be properly set up. The most common requirement is having the right packages installed. The playbook introduced here covers the QEMU's project s390x and aarch64 machines. At the time this is being proposed, those machines have already

[PATCH v6 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI)

TL;DR: this should allow the QEMU maintainer to push to the staging branch, and have custom jobs running on the project's aarch64 and s390x machines. Jobs in this version are allowed to fail, to allow for the inclusion of the novel machines/jobs without CI disruption. Simple usage looks like:

Re: [PATCH 08/55] target/arm: Implement MVE DLSTP

On 6/7/21 9:57 AM, Peter Maydell wrote: +{ + # This is DLSTP + DLS 0 0 size:2 rn:4 1110 0001 + LCTP 0 000 1110 0001 +} Same comment with LCTP being the more specific encoding. Either way, Reviewed-by: Richard H

Re: [PATCH] netdev: add more commands to preconfig mode

在 2021/6/7 下午10:22, Daniel P. Berrangé 写道: On Tue, May 11, 2021 at 11:39:55AM -0400, Paolo Bonzini wrote: Creating and destroying network backend does not require a fully constructed machine. Allow the related monitor commands to run before machine initialization has concluded. Signed-off-by

Re: [PATCH 2/2] vhost-vdpa: remove the unused vhost_vdpa_get_acked_features()

在 2021/6/6 上午1:19, Gautam Dawar 写道: No user for this helper, let's remove it. [GD>>] These patches seem unrelated to me. Do you think they should be part of one patch series? It doesn't harm. I've queued this patch. Thanks Signed-off-by: Jason Wang --- include/net/vhost-vdpa.h |

Re: [PATCH 1/2] vhost-vdpa: don't initialize backend_features

在 2021/6/4 下午5:10, Gautam Dawar 写道: Hi Jason, -Original Message- From: Jason Wang Sent: Wednesday, June 2, 2021 2:18 PM To: Gautam Dawar ; m...@redhat.com; qemu-devel@nongnu.org Cc: l...@redhat.com; qemu-sta...@nongnu.org Subject: Re: [PATCH 1/2] vhost-vdpa: don't initialize backend_f

Re: [PATCH 07/55] target/arm: Implement MVE WLSTP insn

On 6/7/21 9:57 AM, Peter Maydell wrote: +WLS 0 100 rn:4 1100 . .. 1 imm=%lob_imm size=4 +{ + # This is WLSTP + WLS 0 0 size:2 rn:4 1100 . .. 1 imm=%lob_imm + LE 0 0 f:1 0 1100 . .. 1 imm

[PULL 29/32] target/riscv: rvb: address calculation

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20210505160620.15723-15-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 + target/riscv/translate.c| 32

[PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line

From: Kito Cheng B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20210505160620.15723-17-frank.ch...@sifive.com Signed-off-by: A

[PULL 27/32] target/riscv: rvb: generalized reverse

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20210505160620.15723-13-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 4 ++ target/riscv/bitmanip_he

[PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20210505160620.15723-16-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 3 +++ target/riscv/translate.c| 6 +

[PULL 25/32] target/riscv: rvb: shift ones

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-11-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 8 target/riscv/t

[PULL 22/32] target/riscv: rvb: sign-extend instructions

From: Kito Cheng Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Frank Chang Message-id: 20210505160620.15723-8-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 3 +++ target/riscv/ins

[PULL 24/32] target/riscv: rvb: single-bit instructions

From: Frank Chang Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-10-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 17 + target/riscv

[PULL 32/32] target/riscv: rvb: add b-ext version cpu option

From: Frank Chang Default b-ext version is v0.93. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-18-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +++ target/riscv/cpu.c | 23 +++ 2 files chan

[PULL 20/32] target/riscv: rvb: pack two words into one register

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-6-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 target/riscv/tr

[PULL 21/32] target/riscv: rvb: min/max instructions

From: Kito Cheng Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Frank Chang Message-id: 20210505160620.15723-7-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 4 target/riscv/in

[PULL 28/32] target/riscv: rvb: generalized or-combine

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20210505160620.15723-14-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 target/riscv/bitmanip_

[PULL 18/32] target/riscv: rvb: count bits set

From: Frank Chang Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Frank Chang Message-id: 20210505160620.15723-4-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/tra

[PULL 19/32] target/riscv: rvb: logic-with-negate

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-5-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 3 +++ target/riscv/ins

[PULL 26/32] target/riscv: rvb: rotate (left/right)

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-12-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 target/riscv/t

[PULL 16/32] target/riscv: reformat @sh format encoding for B-extension

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-2-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 10 +- 1 file changed, 5 inse

[PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz.

From: LIU Zhiwei Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz is still zero(as we don't use this field), simd_desc will trigger an assert. Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation. Here we pass the value to maxsz and oprsz to bypass the assert. Signe

[PULL 17/32] target/riscv: rvb: count leading/trailing zeros

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-3-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/insn3

[PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration

From: Bin Meng riscv_excp_names[] and riscv_intr_names[] are only referenced by target/riscv/cpu.c locally. Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20210514052435.2203156-1-bmeng...@gmail.com Signed-off-by: Alistair Francis --- t

[PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp

From: Changbin Du This dumps the CSR mscratch/sscratch/satp and meanwhile aligns the output of CSR mtval/stval. Signed-off-by: Changbin Du Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20210519155738.20486-1-changbin...@gmail.com Signed-off-by: Alistair Francis --- target/

[PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation

From: Philippe Mathieu-Daudé Physical Memory Protection is a system feature. Avoid polluting the user-mode emulation by its definitions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20210516205333.696094-1-f4...@amsat.org Signed-off-by:

[PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions

From: Frank Chang Add gen_shifti() and gen_shiftiw() helper functions to reuse the same interfaces for immediate shift instructions. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-9-frank.ch...@sifive.com Signed-off-by:

[PULL 10/32] docs/system: Move the RISC-V -bios information to removed

QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt and sifive_u machines. This patch moves that change from the deprecated.rst file to the removed-features.rst file and the target-riscv.rst. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 4f1c261e7f69045ab8

[PULL 14/32] target/riscv/pmp: Add assert for ePMP operations

Although we construct epmp_operation in such a way that it can only be between 0 and 15 Coverity complains that we don't handle the other possible cases. To fix Coverity and make it easier for humans to read add a default case to the switch statement that calls g_assert_not_reached(). Fixes: CID 1

[PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage

From: Bin Meng Update the 'sifive_u' machine documentation to mention the '-dtb' option that can be used to pass a custom DTB to QEMU. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210430071302.1489082-6-bmeng...@gmail.com Signed-off-by: Alistair Francis --- docs/system

[PULL 07/32] hw/riscv: Use macros for BIOS image names

From: Bin Meng The OpenSBI BIOS image names are used by many RISC-V machines. Let's define macros for them. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210430071302.1489082-7-bmeng...@gmail.com Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 5 + hw/

[PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot

From: Bin Meng At present the Microchip Icicle Kit machine only supports using '-bios' to load the HSS, and does not support '-kernel' for direct kernel booting just like other RISC-V machines do. One has to use U-Boot which is chain-loaded by HSS, to load a kernel for testing. This is not so con

[PULL 09/32] target/riscv: fix wfi exception behavior

From: Jose Martins The wfi exception trigger behavior should take into account user mode, hstatus.vtw, and the fact the an wfi might raise different types of exceptions depending on various factors: If supervisor mode is not present: - an illegal instruction exception should be generated if use

[PULL 02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper

From: Bin Meng Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the compatible strings for the SiFive test device node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210430071302.1489082-2-bmeng...@gmai

[PULL 04/32] hw/riscv: Support the official PLIC DT bindings

From: Bin Meng The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the compatible string in the upstream Linux kernel. "riscv,plic0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 2021043

[PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices

From: Bin Meng The supported device bullet list has an additional space before each entry, which makes a wrong indentation level. Correct it. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210430071302.1489082-5-bmeng...@gmail.com Signed-off-by: Alistair Francis --- docs

[PULL 03/32] hw/riscv: Support the official CLINT DT bindings

From: Bin Meng Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bi

[PULL 00/32] riscv-to-apply queue

The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca: Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07 15:45:48 +0100) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-risc

[PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper

From: Bin Meng Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the clock name for the ethernet controller node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210430071302.1489082-1-bmeng...@gmail.com S

Re: [PATCH 06/55] target/arm: Implement MVE LCTP

On 6/7/21 9:57 AM, Peter Maydell wrote: Implement the MVE LCTP instruction. We put its decode and implementation with the other low-overhead-branch insns because although it is only present if MVE is implemented it is logically in the same group as the other LOB insns. Signed-off-by: Peter Mayd

Re: [PATCH 05/55] target/arm: Let vfp_access_check() handle late NOCP checks

On 6/7/21 9:57 AM, Peter Maydell wrote: In commit a3494d4671797c we reworked the M-profile handling of its checks for when the NOCP exception should be raised because the FPU is disabled, so that (in line with the architecture) the NOCP check is done early over a large range of the encoding space

[PATCH v1 1/5] ui/gtk: Create a common release_dmabuf helper

Since the texture release mechanism is same for both gtk-egl and gtk-glarea, move the helper from gtk-egl to common gtk code so that it can be shared by both gtk backends. Cc: Gerd Hoffmann Signed-off-by: Vivek Kasireddy --- include/ui/gtk.h | 2 -- ui/gtk-egl.c | 8 ui/gtk.c

[PATCH v1 3/5] ui/egl: Add egl helpers to help with synchronization

These egl helpers would be used for creating and waiting on a sync object. Cc: Gerd Hoffmann Signed-off-by: Vivek Kasireddy --- include/ui/console.h | 2 ++ include/ui/egl-helpers.h | 3 +++ ui/egl-helpers.c | 44 ui/gtk.c |

[PATCH v1 2/5] ui: Add a helper to wait on a dmabuf sync object

This will be called by virtio-gpu in the subsequent patches. Cc: Gerd Hoffmann Signed-off-by: Vivek Kasireddy --- include/ui/console.h | 5 + ui/console.c | 10 ++ 2 files changed, 15 insertions(+) diff --git a/include/ui/console.h b/include/ui/console.h index b30b63976a..

[PATCH v1 4/5] ui: Create sync objects only for blobs

For now, create sync objects only for dmabufs that are blobs. Cc: Gerd Hoffmann Signed-off-by: Vivek Kasireddy --- hw/display/virtio-gpu-udmabuf.c | 2 ++ include/ui/console.h| 1 + include/ui/egl-helpers.h| 1 + ui/gtk-egl.c| 10 ++ ui/gtk-gl-

[PATCH v1 5/5] virtio-gpu: Make resource_flush wait on the sync object for blobs

To make sure that the Guest would not use the backing storage associated with a blob resource before or at the same time when the Host does a blit with it, resource_flush needs to wait on the sync object associated with the blob. Doing this would prevent tearing/flickering or other issues when usin

[PATCH v1 0/5] virtio-gpu: Add implicit (and default) sync mechanism for blobs

When the Guest and Host are using Blob resources, there is a chance that they may use the underlying storage associated with a Blob at the same time leading to glitches such as flickering or tearing. To prevent these from happening, the Host needs to ensure that it waits until its Blit is completed

Re: [PATCH 04/55] target/arm: Add handling for PSR.ECI/ICI

On 6/7/21 9:57 AM, Peter Maydell wrote: +void clear_eci_state(DisasContext *s) +{ +/* + * Clear any ECI/ICI state: used when a load multiple/store + * multiple insn executes. + */ +if (s->eci) { +TCGv_i32 tmp = tcg_temp_new_i32(); +tcg_gen_movi_i32(tmp, 0); t

Re: [PATCH qemu v20] spapr: Implement Open Firmware client interface

On Mon, 7 Jun 2021, David Gibson wrote: On Fri, Jun 04, 2021 at 03:59:22PM +0200, BALATON Zoltan wrote: On Fri, 4 Jun 2021, David Gibson wrote: On Wed, Jun 02, 2021 at 02:29:29PM +0200, BALATON Zoltan wrote: On Wed, 2 Jun 2021, David Gibson wrote: On Thu, May 27, 2021 at 02:42:39PM +0200, BAL

[PATCH] softfloat: Fix tp init in float32_exp2

Typo in the conversion to FloatParts64. Fixes: 572c4d862ff2 Fixes: Coverity CID 1457457 Signed-off-by: Richard Henderson --- fpu/softfloat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 1cb162882b..4d0160fe9c 100644 --- a/fpu/softflo

Re: [PULL 25/29] softfloat: Convert float32_exp2 to FloatParts

On 6/7/21 2:07 PM, Peter Maydell wrote: +FloatParts64 xp, xnp, tp, rp; Coverity points out that we declare tp here without initializing it... ... +float64_unpack_canonical(&xnp, float64_ln2, status); +xp = *parts_mul(&xp, &tp, status); ...and then here we pass &tp to parts_mul()

Re: [PATCH qemu v20] spapr: Implement Open Firmware client interface

On Mon, 7 Jun 2021, David Gibson wrote: On Mon, Jun 07, 2021 at 12:21:21AM +0200, BALATON Zoltan wrote: On Fri, 4 Jun 2021, David Gibson wrote: On Wed, Jun 02, 2021 at 02:29:29PM +0200, BALATON Zoltan wrote: On Wed, 2 Jun 2021, David Gibson wrote: On Thu, May 27, 2021 at 02:42:39PM +0200, BAL

Re: [PATCH] qemu-{img,nbd}: Don't report zeroed cluster as a hole

On Mon, Jun 07, 2021 at 04:22:27PM -0500, Eric Blake wrote: [replying to myself] > > Here is simpler reproducer: > > > > # Create a qcow2 image with a raw backing file: > > $ qemu-img create base.raw $((4*64*1024)) > > $ qemu-img create -f qcow2 -b base.raw -F raw top.qcow2 > > > >

Re: [PATCH v3 0/4] target/i386/cpu: introduce new CPU models for x86-64 ABI levels

On Mon, Jun 07, 2021 at 02:58:39PM +0100, Daniel P. Berrangé wrote: > This series is motivated by this blog that describes how RHEL-9 > will recommend use of the x86-64-v2 microarchitectural ABI level: > > > https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-t

Re: [PATCH] qemu-{img,nbd}: Don't report zeroed cluster as a hole

On Mon, Jun 07, 2021 at 11:22:04PM +0300, Nir Soffer wrote: > When zeroing a cluster in an image with backing file, qemu-img and > qemu-nbd reported the area as a hole. This does not affect the guest > since the area is read as zero, but breaks code trying to reconstruct > the image chain based on

Re: [PATCH 03/55] target/arm: Handle VPR semantics in existing code

On 6/7/21 9:57 AM, Peter Maydell wrote: @@ -410,16 +415,19 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; if (ts) { -/* Clear s0 to s31 and the FPSCR */ +/* Clear s0 to s31 and the FPSCR and VPR */

Re: [PULL 25/29] softfloat: Convert float32_exp2 to FloatParts

On Thu, 3 Jun 2021 at 22:58, Richard Henderson wrote: > > Keep the intermediate results in FloatParts instead of > converting back and forth between float64. Use muladd > instead of separate mul+add. > > Reviewed-by: Alex Bennée > Signed-off-by: Richard Henderson > --- > fpu/softfloat.c | 53 +

Re: [RFC PATCH] target/ppc: fix address translation bug for hash table mmus

On 6/7/21 12:29 PM, Bruno Piazera Larsen wrote: I just tried sending mmu_idx all the way down, but I ran into a very weird bug of gcc. If we have to add one more parameter that GCC can't just optimize away we get at least a slow down of 5x for the first test of check-acceptance (could be more,

Re: [PATCH v3 0/7] acpi: Error Record Serialization Table, ERST, support for QEMU

Igor, Thanks for the information/feedback. I am working to implement all your suggestions; from my perspective, there were two big changes requested, and the use of hostmem-file was the first, and the conversion to PCI the second. V3 was the hostmem-file, and hopefully all changes then in v4. Re

Re: [PATCH 03/11] softfloat: Introduce float_flag_inorm_denormal

On 6/7/21 10:19 AM, Alex Bennée wrote: If you've got a better ordering of operations for this, do tell. What I really want is to know which instructions translate into the if (s->flush_inputs_to_zero) and verifying that is only checked once. Maybe I'm just suspicious of compilers ability to opt

[PATCH] qemu-{img,nbd}: Don't report zeroed cluster as a hole

When zeroing a cluster in an image with backing file, qemu-img and qemu-nbd reported the area as a hole. This does not affect the guest since the area is read as zero, but breaks code trying to reconstruct the image chain based on qemu-img map or qemu-nbd block status response. Here is simpler rep

[PATCH 40/42] scripts/qmp-shell: move to python/qemu/qmp/qmp_shell.py

The script will be unavailable for a commit or two, which will help preserve development history attached to the new file. A forwarder will be added shortly afterwards. With qmp_shell in the python qemu.qmp package, now it is fully type checked, linted, etc. via the Python CI. It will be quite a b

[PATCH 41/42] python: add qmp-shell entry point

now 'qmp-shell' should be available from the command line when installing the python package. Signed-off-by: John Snow --- python/setup.cfg | 1 + 1 file changed, 1 insertion(+) diff --git a/python/setup.cfg b/python/setup.cfg index 7f3c59d74e..85cecbb41b 100644 --- a/python/setup.cfg +++ b/pyt

[PATCH 42/42] scripts/qmp-shell: add redirection shim

qmp-shell has a new home, add a redirect for a little while as the dust settles. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 11 +++ 1 file changed, 11 insertions(+) create mode 100755 scripts/qmp/qmp-shell diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell new file mo

Re: [Stratos-dev] [PATCH 0/5] virtio: Add vhost-user based RNG service

On Fri, 4 Jun 2021 at 07:36, Srivatsa Vaddagiri wrote: > > * Mathieu Poirier via Stratos-dev > [2021-06-01 20:03:14]: > > > Hi all, > > > > This sets adds a vhost-user based random number generator (RNG), > > similar to what has been done for i2c and virtiofsd. In fact > > the implementation fo

Re: [PATCH v3 3/4] scripts: helper to generate x86_64 CPU ABI compat info

On Mon, Jun 07, 2021 at 02:11:44PM -0300, Eduardo Habkost wrote: > On Mon, Jun 07, 2021 at 02:58:42PM +0100, Daniel P. Berrangé wrote: > [...] > > +# Assumes externally launched process such as > > +# > > +# qemu-system-x86_64 -qmp unix:/tmp/qmp,server,nowait -display none > > -accel kvm > > +#

[PATCH 39/42] scripts/qmp-shell: add docstrings

Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 39 ++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell index 1a8a4ba18a..15aedb80c2 100755 --- a/scripts/qmp/qmp-shell +++ b/scripts/qmp/qmp-shell

[PATCH 22/42] scripts/qmp-shell: move the REPL functionality into QMPShell

Instead of doing this in main, move it into the class itself. (This makes it easier to put into the qemu.qmp package later by removing as much as we can from the main() function.) Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-)

[PATCH 38/42] scripts/qmp-shell: make QMPShellError inherit QMPError

In preparation for moving qmp-shell into the qemu.qmp package, make QMPShellError inherit from QMPError so that all custom errors in this package all derive from QMPError. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scrip

[PATCH 36/42] scripts/qmp-shell: convert usage comment to docstring

The nice usage comment should be a docstring instead of a comment, so that it's visible from other python tooling. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 128 -- 1 file changed, 72 insertions(+), 56 deletions(-) diff --git a/scripts/qmp/qmp-

[PATCH 30/42] python/qmp: return generic type from context manager

__enter__ can be invoked from a subclass, so it needs a more flexible type. Signed-off-by: John Snow --- python/qemu/qmp/__init__.py | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/python/qemu/qmp/__init__.py b/python/qemu/qmp/__init__.py index ba0d2281d6..376954cb6d 1006

[PATCH 35/42] scripts/qmp-shell: Remove too-broad-exception

We are only anticipating QMPShellErrors here, for syntax we weren't able to understand. Other errors, if any, should be allowed to percolate upwards. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/scripts/qmp/qmp

[PATCH 13/42] scripts/qmp-shell: rename one and two-letter variables

A bit of churn and housekeeping for pylint, flake8 et al. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell index 8d84467b53..afb4b0c544 100755 --- a/scri

[PATCH 29/42] scripts/qmp-shell: unprivatize 'pretty' property

Similar to verbose, there's no reason this needs to be hidden. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell index b465c7f9e2..f14fe211cc 100755 --- a/scripts/qmp/qmp-s

[PATCH 32/42] scripts/qmp-shell: use logging to show warnings

A perfect candidate is non-fatal shell history messages. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell index ec028d662e..0199a13a34 100755 --- a/scripts/qmp/qmp-shell

[PATCH 16/42] scripts/qmp-shell: use isinstance() instead of type()

A bit more idiomatic, and quiets some linter warnings. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell index bf7a49dfc1..970f43dd00 100755 --- a/scripts/qmp/qmp-shell +++ b/sc

[PATCH 33/42] scripts/qmp-shell: remove TODO

We still want to revamp qmp-shell again, but there's much more to the idea than the comment now intuits. Remove it. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 2 -- 1 file changed, 2 deletions(-) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell index 0199a13a34..3c32b576a3 1

[PATCH 37/42] scripts/qmp-shell: remove double-underscores

They're not needed; single underscore is enough to express intent that these methods are "internal". double underscore is used as a weak name mangling, but that isn't beneficial for us here. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 52 +-- 1 fi

[PATCH 23/42] scripts/qmp-shell: Fix "FuzzyJSON" parser

I'm not sure when this regressed (Or maybe if it was ever working right to begin with?), but the Python AST requires you to change "Names" to "Constants" in order to truly convert `false` to `False`. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 20 ++-- 1 file changed, 10

[PATCH 17/42] scripts/qmp-shell: use argparse

Use argparse instead of an open-coded CLI parser, for consistency with everything else. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 82 +-- 1 file changed, 32 insertions(+), 50 deletions(-) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-she

[PATCH 09/42] scripts/qmp-shell: declare verbose in __init__

Linters get angry when we don't define state at init time. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell index 3066e37ae5..4027454324 100755 --- a/scripts/qmp/qmp-shell +++ b/scripts/qmp/qmp-sh

[PATCH 18/42] scripts/qmp-shell: Add pretty attribute to HMP shell

It's less useful, but it makes the initialization methods LSP consistent, which quiets a mypy complaint. Signed-off-by: John Snow --- scripts/qmp/qmp-shell | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/scripts/qmp/qmp-shell b/scripts/qmp/qmp-shell index 5317dcd5

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