03.05.2021 14:05, Kevin Wolf wrote:
Like other error paths, this one needs to call tran_finalize() and clean
up the BlockReopenQueue, too.
Fixes: CID 1452772
Fixes: 72373e40fbc7e4218061a8211384db362d3e7348
Signed-off-by: Kevin Wolf
---
block.c | 2 +-
1 file changed, 1 insertion(+), 1 deleti
03.05.2021 18:51, Alberto Garcia wrote:
On Mon 03 May 2021 01:33:57 PM CEST, Vladimir Sementsov-Ogievskiy
wrote:
@@ -2918,12 +2918,18 @@ BdrvChild *bdrv_root_attach_child(BlockDriverState
*child_bs,
child_role, perm, shared_perm, opaque,
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/112
** Changed in: qemu
Status: Confirmed => Expired
** Bug
+CC Danpb
> >>> Marc-André, I'd like your opinion for this one, in particular the use of
> >>> g_source_remove().
> >>>
> >>
> >> My opinion isn't really worth much, my review would have a bit more value.
> >>
> >> GSource has indeed some peculiar lifetime management, that I got wrong in
> >> the
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/116
** Changed in: qemu
Status: Triaged => Expired
** Bug w
From: Richard Henderson
Introduce 3 helper macros to elide arguments that we cannot supply.
This reduces the repetition required to get the job done.
Signed-off-by: Richard Henderson
Message-Id: <20210501022923.1179736-2-richard.hender...@linaro.org>
Signed-off-by: David Gibson
---
target/ppc
From: Peter Maydell
The h_int_reset() function resets the XIVE interrupt controller via
device_legacy_reset(). We know that the interrupt controller does
not have a qbus of its own, so the new device_cold_reset() function
(which resets both the device and its child buses) is equivalent here
to d
From: Peter Maydell
The pnv_psi.c code uses device_legacy_reset() for two purposes:
* to reset itself from its qemu_register_reset() handler
* to reset a XiveSource object it has
Neither it nor the XiveSource have any qbuses, so the new
device_cold_reset() function (which resets both the devic
From: "Bruno Larsen (billionai)"
Since vscr is not an spr, its initialization was removed from the
spr registration functions, and moved to the relevant init_procs.
We may look into adding vscr to the reset path instead of the init
path (as suggested by David Gibson), but this looked like a good
From: Nicholas Piggin
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
Message-Id: <20210501072436.145444-3-npig...@gmail.com>
[dwg
From: Peter Maydell
The spapr_vio_quiesce_one() function resets the TCE table object
(TYPE_SPAPR_TCE_TABLE) via device_legacy_reset(). We know that
objects of that type do not have a qbus of their own, so the new
device_cold_reset() function (which resets both the device and its
child buses) is
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/113
** Changed in: qemu
Status: New => Expired
** Bug watch
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/114
** Changed in: qemu
Status: New => Expired
** Bug watch
From: Nicholas Piggin
The AIL logic is becoming unmanageable spread all over powerpc_excp(),
and it is slated to get even worse with POWER10 support.
Move it all to a new helper function.
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
Message-Id: <20
From: Bin Meng
This adds detailed documentation for PowerPC `ppce500` machine,
including the following information:
- Supported devices
- Hardware configuration information
- Boot options
- Running Linux kernel
- Running U-Boot
Signed-off-by: Bin Meng
Signed-off-by: David Gibson
---
docs/sys
From: "Bruno Larsen (billionai)"
code motion to remove opcode callback table from
translate_init.c.inc to translate.c in preparation to remove
the #include from translate.c. Also created
destroy_ppc_opcodes and removed that logic from ppc_cpu_unrealize
Signed-off-by: Bruno Larsen (billionai)
M
From: Daniel Henrique Barboza
At this moment, PAPR does not provide a way to report errors during a
device removal operation. This led the pSeries machine to implement
extra mechanisms to try to fallback and recover from an error that might
have happened during the hotunplug in the guest side. Th
From: Daniel Henrique Barboza
Up to this patch, 'max_cpus' value is hardcoded to 1024 (commit
6244bb7e5811). In theory this patch would simply bump it to 2048, since
it's the default NR_CPUS kernel setting for ppc64 servers nowadays, but
the whole mechanic of MachineClass:max_cpus is flawed for t
From: "Bruno Larsen (billionai)"
All the code related to gdb has been moved from translate_init.c.inc
file to the gdbstub.c file, where it makes more sense.
Version 4 fixes the omission of internal.h in gdbstub, mentioned in
<87sg3d2gf5@linux.ibm.com>, and the extra blank line.
Signed-off-b
From: Nicholas Piggin
This must have slipped through the cracks between adding POWER10 support
and scv support.
Signed-off-by: Nicholas Piggin
Message-Id: <20210415054227.1793812-3-npig...@gmail.com>
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
target/ppc/translate_init.c.in
From: Nicholas Piggin
ISA v3.0 radix guest execution has a quirk in AIL behaviour such that
the LPCR[AIL] value can apply to hypervisor interrupts.
This affects machines that emulate HV=1 mode (i.e., powernv9).
Signed-off-by: Nicholas Piggin
Message-Id: <20210415054227.1793812-2-npig...@gmail.
From: Daniel Henrique Barboza
Certain SMP topologies stress, e.g. 1 thread/core, 2048 cores and
1 socket, stress the current maximum size of the pSeries FDT:
Calling ibm,client-architecture-support...qemu-system-ppc64: error
creating device tree: (fdt_setprop(fdt, offset,
"ibm,processor-segment-
From: Vaibhav Jain
Add support for H_SCM_HEALTH hcall described at [1] for spapr
nvdimms. This enables guest to detect the 'unarmed' status of a
specific spapr nvdimm identified by its DRC and if its unarmed, mark
the region backed by the nvdimm as read-only.
The patch adds h_scm_health() to han
From: Richard Henderson
We elide values when registering sprs, we might as well
save space in the array as well.
Signed-off-by: Richard Henderson
Message-Id: <20210501022923.1179736-3-richard.hender...@linaro.org>
Signed-off-by: David Gibson
---
target/ppc/cpu.h | 12
1 file chan
From: Alexey Kardashevskiy
SLOF instantiates RTAS since
744a928ccee9 ("spapr: Stop providing RTAS blob")
so the max address applies to the FDT only.
This renames the macro and fixes up the comment.
This should not cause any behavioral change.
Signed-off-by: Alexey Kardashevskiy
Message-Id: <2
From: Bin Meng
Currently building ppce500 u-boot image results in
modified: roms/u-boot (untracked content)
As roms/u-boot/.gitignore indicates, update the build directory
name to build-e500 to eliminate this message.
Signed-off-by: Bin Meng
Signed-off-by: David Gibson
---
roms/Makefile
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/115
** Changed in: qemu
Status: Confirmed => Expired
** Bug
From: BALATON Zoltan
To allow reusing ISA bridge emulation for vt8231_isa move the device
state of vt82c686b_isa emulation in an abstract via_isa class. This
change breaks migration back compatibility but this is not an issue
for Fuloong2E machine which is not versioned or migration supported.
S
From: BALATON Zoltan
The VT8231 south bridge is very similar to VT82C686B but there are
some differences in register addresses and functionality, e.g. the
VT8231 only has one serial port. This commit adds VT8231_SUPERIO
subclass based on the abstract VIA_SUPERIO class to emulate the
superio part
From: Ravi Bangoria
Power10 is introducing second DAWR. Use real register names (with
suffix 0) from ISA for current macros and variables used by Qemu.
One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel
uapi header and thus not changed in kernel as well as Qemu.
Signed-off-by: Ra
From: BALATON Zoltan
The Marvell Discovery II aka. MV64361 is a PowerPC system controller
chip that is used on the pegasos2 PPC board. This adds emulation of it
that models the device enough to boot guests on this board. The
mv643xx.h header with register definitions is taken from Linux 4.15.10
o
From: BALATON Zoltan
Add emulation of VT8231 south bridge ISA part based on the similar
VT82C686B but implemented in a separate subclass that holds the
differences while reusing parts that can be shared.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
<10abc9f898
From: BALATON Zoltan
Collect superio functionality and its controlling config registers
handling in an abstract VIA_SUPERIO class that is a subclass of
ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
abstract class.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
From: Richard Henderson
Nothing within the translator -- or anywhere else for that
matter -- checks MSR_SA or MSR_AP on the 602. This may be
a mistake. However, for the moment, we need not record these
bits in hflags.
This allows us to simplify HFLAGS_VSX computation by moving
it to overlap wi
From: BALATON Zoltan
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II,
a PowerPC board based on the Marvell MV64361 system controller and the
VIA VT8231 integrated south bridge/superio chips. It can run Linux,
AmigaOS and a wide range of MorphOS versions. Currently a firmware
From: Richard Henderson
We weren't recording MSR_GS in hflags, which means that BookE
memory accesses were essentially random vs Guest State.
Instead of adding this bit directly, record the completed mmu
indexes instead. This makes it obvious that we are recording
exactly the information that w
From: Richard Henderson
In save_user_regs, there are two bugs where we OR in a bit number
instead of the bit, clobbering the low bits of MSR. However:
The MSR_VR and MSR_SPE bits control the availability of the insns.
If the bits were not already set in MSR, then any attempt to access
those reg
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-Id: <20210315184615.1985590-16-richard.hender...@linaro.org>
Signed-off-by: David Gibson
---
hw/ppc/spapr_rtas.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 8a79f9c628..6e
From: Richard Henderson
Verify that hflags was updated correctly whenever we change
cpu state that is used by hflags.
Signed-off-by: Richard Henderson
Message-Id: <20210323184340.619757-11-richard.hender...@linaro.org>
Signed-off-by: David Gibson
---
target/ppc/cpu.h | 5 +
targe
From: Richard Henderson
It will be stored in tb->flags, which is also uint32_t,
so let's use the correct size.
Reviewed-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
Message-Id: <20210323184340.619757-4-richard.hender...@linaro.org>
Signed-off-by: David Gibso
From: Richard Henderson
Copying flags directly from msr has drawbacks: (1) msr bits
mean different things per cpu, (2) msr has 64 bits on 64 cpus
while tb->flags has only 32 bits.
Create a enum to define these bits. Document the origin of each bit
and validate those bits that must match MSR. T
From: Richard Henderson
In ppc_store_msr we call hreg_compute_hflags, which itself
calls hreg_compute_mem_idx. Rely on ppc_store_msr to update
everything required by the msr update.
Signed-off-by: Richard Henderson
Message-Id: <20210315184615.1985590-5-richard.hender...@linaro.org>
Reviewed-by
From: Richard Henderson
Because these bits were not in hflags, the code generated
for single-stepping on BookE was essentially random.
Recompute hflags when storing to dbcr0.
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
Message-Id: <20210323184340.619757-5-richard.hender...@linar
From: Richard Henderson
Perform the test against FSCR_SCV at runtime, in the helper.
This means we can remove the incorrect set against SCV in
ppc_tr_init_disas_context and do not need to add an HFLAGS bit.
Signed-off-by: Richard Henderson
Message-Id: <20210323184340.619757-6-richard.hender...
From: Richard Henderson
Extract post_load_update_msr to share between cpu_load_old
and cpu_post_load in updating the msr.
Suggested-by: Cédric Le Goater
Signed-off-by: Richard Henderson
Message-Id: <20210323184340.619757-2-richard.hender...@linaro.org>
Signed-off-by: David Gibson
---
target/
From: Richard Henderson
Move the functions to a new file, helper_regs.c.
Note int_helper.c was relying on helper_regs.h to
indirectly include qemu/log.h.
Signed-off-by: Richard Henderson
Message-Id: <20210315184615.1985590-2-richard.hender...@linaro.org>
Reviewed-by: Cédric Le Goater
Signed-o
From: Richard Henderson
Because this bit was not in hflags, the privilege check
for tlb instructions was essentially random.
Recompute hflags when storing to LPCR.
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
Message-Id: <20210323184340.619757-7-richard.hender...@linaro.org>
Sign
From: Richard Henderson
We have eliminated all normal uses of hflags_nmsr. We need
not even compute it except when we want to migrate. Rename
the field to emphasize this.
Remove the fixme comment for migrating access_type. This value
is only ever used with the current executing instruction, a
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-Id: <20210315184615.1985590-15-richard.hender...@linaro.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index bd2b
The following changes since commit 15106f7dc3290ff3254611f265849a314a93eb0e:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502' into
staging (2021-05-02 16:23:05 +0100)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.1-2021050
From: Richard Henderson
As per hreg_compute_hflags:
We 'forget' FE0 & FE1: we'll never generate imprecise exceptions
remove the hflags marker from the respective comments.
Signed-off-by: Richard Henderson
Message-Id: <20210315184615.1985590-7-richard.hender...@linaro.org>
Reviewed-by: Cédri
From: Richard Henderson
Match cpu_post_load in using ppc_store_msr to set all of
the cpu state implied by the value of msr. Do not restore
hflags or hflags_nmsr, as we recompute them in ppc_store_msr.
Signed-off-by: Richard Henderson
Message-Id: <20210315184615.1985590-4-richard.hender...@lina
From: Richard Henderson
Keep all hflags computation in one place, as this will be
especially important later.
Introduce a new POWERPC_FLAG_HID0_LE bit to indicate when
LE should be taken from HID0. This appears to be set if
and only if POWERPC_FLAG_RTC_CLK is set, but we're not
short of bits an
From: Philippe Mathieu-Daudé
On Mac99 and newer machines, the Uninorth PCI host bridge maps
the PCI hole region at 2GiB, so the RAM area beside 2GiB is not
accessible by the CPU. Restrict the memory to 2GiB to avoid
problems such the one reported in the buglink.
Buglink: https://bugs.launchpad.n
> > The proposal that "sync-dax=unsafe" for non-PPC architectures, is a
> > fundamental misrepresentation of how this is supposed to work. Rather
> > than make "sync-dax" a first class citizen of the device-description
> > interface I'm proposing that you make this a separate device-type.
> > This
On 03/05/2021 18.55, Peter Maydell wrote:
In rtc-test.c we know that s is non-NULL because qtest_start()
will return a non-NULL value, and we assume this when we
pass s to qtest_irq_intercept_in(). So we can drop the
initial assignment of NULL and the "if (s)" condition at
the end of the function
On 5/4/21 1:11 AM, Dan Williams wrote:
On Mon, May 3, 2021 at 7:06 AM Shivaprasad G Bhat wrote:
.
The proposal that "sync-dax=unsafe" for non-PPC architectures, is a
fundamental misrepresentation of how this is supposed to work. Rather
than make "sync-dax" a first class citizen of th
On Tue, May 4, 2021 at 6:34 AM Alistair Francis
wrote:
>
> QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
> and sifive_u machines. This patch moves that change from the
> deprecated.rst file to the removed-features.rst file and the
> target-riscv.rst.
>
> Signed-off-by: Ali
On Mon, May 03, 2021 at 01:23:47PM -0500, Eric Blake wrote:
> On 4/28/21 10:48 PM, Shivaprasad G Bhat wrote:
> > The subsequent patches add definitions which tend to
> > get the compilation to cyclic dependency. So, prepare
> > with forward declarations, move the defitions and clean up.
>
> defini
On 4/27/21 3:00 AM, Markus Armbruster wrote:
John Snow writes:
On 4/25/21 3:59 AM, Markus Armbruster wrote:
John Snow writes:
When the token can be None, we can't use 'x in "abc"' style membership
tests to group types of tokens together, because 'None in "abc"' is a
TypeError.
Easy enough
On Mon, May 03, 2021, Paolo Bonzini wrote:
> On 30/04/21 08:24, Yang Zhong wrote:
> > +void pc_machine_init_sgx_epc(PCMachineState *pcms)
> > +{
> > +SGXEPCState *sgx_epc;
> > +X86MachineState *x86ms = X86_MACHINE(pcms);
> > +
> > +sgx_epc = g_malloc0(sizeof(*sgx_epc));
> > +pcms->s
On Mon, May 03, 2021 at 04:18:47PM +0100, Peter Maydell wrote:
> The h_int_reset() function resets the XIVE interrupt controller via
> device_legacy_reset(). We know that the interrupt controller does
> not have a qbus of its own, so the new device_cold_reset() function
> (which resets both the de
On Mon, May 03, 2021 at 05:15:38PM -0300, Bruno Piazera Larsen wrote:
>
> On 03/05/2021 01:54, David Gibson wrote:
> > On Fri, Apr 30, 2021 at 04:35:28PM -0300, Bruno Larsen (billionai) wrote:
> > > Moved all SPR read/write callback, and some related functions, to a
> > > new file specific for it.
On Mon, May 03, 2021 at 04:18:49PM +0100, Peter Maydell wrote:
> The pnv_psi.c code uses device_legacy_reset() for two purposes:
> * to reset itself from its qemu_register_reset() handler
> * to reset a XiveSource object it has
>
> Neither it nor the XiveSource have any qbuses, so the new
> devi
On Mon, May 03, 2021 at 04:18:48PM +0100, Peter Maydell wrote:
> The spapr_vio_quiesce_one() function resets the TCE table object
> (TYPE_SPAPR_TCE_TABLE) via device_legacy_reset(). We know that
> objects of that type do not have a qbus of their own, so the new
> device_cold_reset() function (whic
On Mon, May 03, 2021 at 10:58:33PM +1000, Nicholas Piggin wrote:
> There are several new bits added to the hcall which reflect new issues
> found and new hardware mitigations.
>
> This adds the link stack flush behaviour, link stack flush accelerated
> instruction capability, and several L1D flush
On 4/30/21 9:45 AM, Max Reitz wrote:
>> + ``data_file_raw``
>> +If this option is set to ``on``, QEMU will always keep the external
>> +data file consistent as a standalone read-only raw image. It does
>> +this by forwarding updates through to the raw image in addition to
>> +updat
On 5/3/21 6:30 AM, Thomas Huth wrote:
We've started migrating the bug tickets from Launchpad to GitLab, so
it does not make too much sense anymore that users open new tickets
in the old system. Let's direct them now to the GitLab tracker instead.
Signed-off-by: Thomas Huth
Reviewed-by: John S
This moved wait_for_console_pattern() to ConsoleMixIn.
By far this change required the most adaptations on tests.
Notice that:
1) Some tests from boot_linux_console.py were using the
wait_for_console_pattern()
from the avocado_qemu package rather than the overloaded method on the
Linux
This moved the last remaining _console_interaction() to ConsoleMixIn.
None tests call it directly, so only the other methods in ConsoleMixIn
needed to be adapted.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/avocado_qemu/__init__.py | 57 +++
1 file change
It was the time of exec_command_and_wait_for_pattern() to find a new
home at ConsoleMixIn. This time various tests needed to be adapted.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/avocado_qemu/__init__.py | 29 +++---
tests/acceptance/boot_linux_console.py | 107
The avocado_qemu package provides the following methods to interact with the
guest via console, which are mainly used on the acceptance boot tests:
exec_command(), exec_command_and_wait_for_pattern(),
wait_for_console_pattern(),
interrupt_interactive_console_until_pattern()
Those methods are l
This created the ConsoleMixIn class to wrap the methods related with console
interaction with the guest that currently are loose in the avocado_qemu
package. It should be used as a mixin on the test classes.
At this point only the interrupt_interactive_console_until_pattern() was moved
to ConsoleM
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/ppc/insn32.decode | 2 ++
> target/ppc/insn64.decode | 11 +++
> target/ppc/translate/fixedpoint-impl.c.inc | 5 +
> 3 files changed, 18 insertions(+)
>
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> scripts/decodetree.py | 50 ---
> 1 file changed, 23 insertions(+), 27 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Form a hex constant of the appropriate insnwidth.
> Begin using f-strings on changed lines.
>
> Signed-off-by: Richard Henderson
> ---
> scripts/decodetree.py | 66 +--
> 1 file changed, 38 insertions(+), 28 d
The ReplayKernelBase class uses the wait_for_console_pattern from its
parent LinuxKernelTest class, thus it doesn't need to import that method
from avocado_qemu.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/replay_kernel.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/te
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion
This moved exec_command() to ConsoleMixIn class.
Only the multiprocess.py file were touched by that change, so its tests
were adapted.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/avocado_qemu/__init__.py | 22 ++
tests/acceptance/multiprocess.py
This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure w
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/ppc/helper.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 4/30/21 3:15 AM, Richard Henderson wrote:
> These will be used by the decodetree trans_* functions
> to early-exit when the instruction set is not enabled.
>
> Signed-off-by: Richard Henderson
> ---
> target/ppc/translate.c | 26 ++
> 1 file changed, 26 insertions(+)
On Tue, May 4, 2021 at 1:13 AM Paolo Bonzini wrote:
>
> On 03/05/21 09:12, Alistair Francis wrote:
> >> deprecated.rst is mainly thought for the things that only have been marked
> >> as deprecated, but not changed yet. Once it's done, the items normally get
> >> moved to docs/system/removed-featu
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/translate.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/translate.c b/tar
QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
and sifive_u machines. This patch moves that change from the
deprecated.rst file to the removed-features.rst file and the
target-riscv.rst.
Signed-off-by: Alistair Francis
---
docs/system/deprecated.rst | 19 ---
This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 6 --
target/riscv/csr.c
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 6 --
target/riscv/cpu.c | 6 +-
2 files changed, 5 insertions(+), 7 deletions(-)
"Lucas Mateus Castro (alqotel)" writes:
> After the feedback from v1 I reworked the patch with suggested ideas and
> this version has less duplicated code and is overall simpler.
>
> This patch series is still a WIP, there are still 2 main problems I am
> trying to solve, I'll mention them in the
The Sun4uMachine class inherit from LinuxKernelTest to effectively only use
the KERNEL_COMMON_COMMAND_LINE attribute. This change remove that unneeded
dependency, making Sun4uMachine self-content.
I took the occasion to delint the code: the unused os import was
removed, imports were reordered, and
From: Emmanuel Blot
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot
Reviewed-by: Alistair Francis
Message-id: 20210421133236.11323-1-emmanuel.b...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 10 --
target/riscv/csr.c | 12 ++--
target/riscv/translate.c | 19 +--
From: Alexander Wagner
The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".
[1]
https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
Signed-off-b
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 11 ---
target/riscv/cpu_helper.c | 24 +++-
2 files cha
From: Emmanuel Blot
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot
Reviewed-by: Alistair Francis
Message-id: fb9e
From: Frank Chang
ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-id: 20210419060302.14075-1-frank.
From: Frank Chang
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
In
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.fran...@wdc.com
---
target/riscv/pmp.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e1f5776316..78203291de 1
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/targe
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.fran...@wdc.com
---
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