Hi Cedric,
On 4/21/21 12:01 PM, Cédric Le Goater wrote:
On 4/21/21 8:20 AM, Ravi Bangoria wrote:
Hi David,
On 4/19/21 10:23 AM, David Gibson wrote:
On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
As per the PAPR, bit 0 of byte 64 in pa-features property indicates
availability
On 4/21/21 15:27, David Gibson wrote:
On Tue, Apr 20, 2021 at 07:16:35PM +1000, Alexey Kardashevskiy wrote:
On 20/04/2021 13:14, David Gibson wrote:
Overall, looking good. I'm pretty much happy to take it into 6.1. I
do have quite a few comments below, but they're basically all just
pol
The QEMU project is currently considering to move its bug tracking to another
system. For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting older bugs to "Incomplete" now.
If you still think this bug report here is valid, then please switch the
The QEMU project is currently considering to move its bug tracking to another
system. For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting older bugs to "Incomplete" now.
If you still think this bug report here is valid, then please switch the
The QEMU project is currently considering to move its bug tracking to another
system. For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting older bugs to "Incomplete" now.
If you still think this bug report here is valid, then please switch the
The QEMU project is currently considering to move its bug tracking to another
system. For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting older bugs to "Incomplete" now.
If you still think this bug report here is valid, then please switch the
On 4/21/21 8:20 AM, Ravi Bangoria wrote:
> Hi David,
>
> On 4/19/21 10:23 AM, David Gibson wrote:
>> On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
>>> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
>>> availability of 2nd DAWR registers. i.e. If this bit is se
The QEMU project is currently considering to move its bug tracking to another
system. For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting older bugs to "Incomplete" now.
If you still think this bug report here is valid, then please switch the
Hi, Eduardo, thanks for your comments!
On 4/21/2021 12:34 AM, Eduardo Habkost wrote:
Hello,
Thanks for the patch. Comments below:
On Tue, Apr 20, 2021 at 05:37:36PM +0800, Chenyi Qiang wrote:
Virtual Machines can exploit bus locks to degrade the performance of
system. To address this kind o
Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
CPUX86State.xmm_regs[] has already been extended to 512bit to support
AVX512.
Also, other qemu level supports for AVX512 registers are there for
years.
But in x86_cpu_dump_state(), still only dump XMM registers no matter
YMM/ZMM
Hi David,
On 4/19/21 10:23 AM, David Gibson wrote:
On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
As per the PAPR, bit 0 of byte 64 in pa-features property indicates
availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
DAWR is present, otherwise not. Use KVM_CAP_PPC_
On 4/20/21 8:28 PM, Peter Xu wrote:
> On Sat, Apr 17, 2021 at 12:30:18PM +0200, Philippe Mathieu-Daudé wrote:
>> The RAM container is exposed as an AddressSpace.
>
> I didn't see where did ram_container got exposed as an address space.
>
> I see it's added as one subregion of get_system_memory(),
On Tue, Apr 20, 2021 at 07:16:35PM +1000, Alexey Kardashevskiy wrote:
>
>
> On 20/04/2021 13:14, David Gibson wrote:
> >
> > Overall, looking good. I'm pretty much happy to take it into 6.1. I
> > do have quite a few comments below, but they're basically all just
> > polish.
> >
> > On Wed, M
On Apr 16 07:28, Klaus Jensen wrote:
On Apr 16 09:22, Gollu Appalanaidu wrote:
Use lower case hexadecimal format for the constants and in
comments use the same format as used in Spec. ("h")
Signed-off-by: Gollu Appalanaidu
---
-v3: Add Suggestions (Philippe)
Describe the NVMe subsystem
On Tue, Apr 20, 2021 at 03:06:18PM +0530, Vaibhav Jain wrote:
> Thanks for looking into this patch David,
>
> David Gibson writes:
>
> > On Thu, Apr 15, 2021 at 01:23:43PM +0530, Vaibhav Jain wrote:
> >> Add support for H_SCM_PERFORMANCE_STATS described at [1] for
> >> spapr nvdimms. This enable
On Tue, Apr 20, 2021 at 01:51:00PM -0300, Daniel Henrique Barboza wrote:
> At this moment, PAPR does not provide a way to report errors during a
> device removal operation. This led the pSeries machine to implement
> extra mechanisms to try to fallback and recover from an error that might
> have ha
On Tue, Apr 20, 2021 at 07:02:36PM +, Bruno Piazera Larsen wrote:
> > > What I was doing was to only register the spr once, and use the
> > > accel-specific functions to set the relevant attributes, so spr_common
> > > wouldn't need to where (and if) spr_read_* exists or not.
> > > Would this w
On Apr 21 00:52, Gollu Appalanaidu wrote:
nvme_map_addr_pmr function arguments not aligned, fix that.
Signed-off-by: Gollu Appalanaidu
---
hw/block/nvme.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 624a1431d0..63ceeb47bd 100644
---
Progress printing had been added here:
https://gitlab.com/qemu-project/qemu/-/commit/6b837bc4a4d
So I think it should be fine to close this ticket now.
** Changed in: qemu
Status: New => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which i
nvme_map_addr_pmr function arguments not aligned, fix that.
Signed-off-by: Gollu Appalanaidu
---
hw/block/nvme.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 624a1431d0..63ceeb47bd 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 23 ++
target/riscv/translate.
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 24
target/riscv/translate.c| 6 ++
3 files change
From: Frank Chang
Default b-ext version is v0.93.
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8464a152d14..b76c3c07c5f 100644
--- a/tar
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/bitmanip_helper.c | 31 +
target/riscv/helper.h | 2 ++
target/riscv/insn32-64.decode | 2 ++
target/riscv/insn32.decode | 2
From: Kito Cheng
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 4
target/riscv/cpu.h | 2 ++
2 files change
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvb.c.inc | 48 +
target/riscv/tra
From: Kito Cheng
Signed-off-by: Kito Cheng
Reviewed-by: Richard Henderson
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 12
2 files changed, 14 insertions(+)
diff --git a/target/riscv/insn32.decode b/tar
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/bitmanip_helper.c | 71 +
target/riscv/helper.h | 7 +++
target/riscv/insn32-64.decode | 2 +
target/riscv/insn32.decode | 2
From: Frank Chang
Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
interfaces for immediate shift instructions.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 54 ++---
target/riscv/translate.c
From: Kito Cheng
Signed-off-by: Kito Cheng
Reviewed-by: Richard Henderson
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvb.c.inc | 24
2 files changed, 28 insertions(+)
diff --git a/target/riscv/insn3
From: Frank Chang
Signed-off-by: Kito Cheng
Reviewed-by: Richard Henderson
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvb.c.inc | 12
target/riscv/translate.c
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 36 +
target/riscv/tra
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 30 +++
target/riscv/translate.c
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++
2 files changed, 22 insertions(+)
diff --git a/target/riscv/insn32.deco
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 8 +++
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvb.c.inc | 90 +
target/riscv/tra
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.de
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 7 +++-
target/riscv/insn_trans/trans_rvb.c.inc | 47 +
target/riscv/tr
From: Frank Chang
This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and
Zbs subset instructions. Some Zbp instructions are also implemented as
they have similar behavior with their Zba-, Zbb- and Zbs-family
instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
Specific
On Tue, Apr 20, 2021 at 06:27:38PM +, Lucas Mateus Martins Araujo e Castro
wrote:
>
>
>
>
>
> >> spapr_hcall.c:
> >> function h_enter call ppc_hash64_hpte_page_shift_noslb,
> >> ppc_hash64_map_hptes and ppc_hash64_unmap_hptes
> >> function remove_h
在 2021/3/24 9:18, Hyman Huang 写道:
cc th...@redhat.com and berra...@redhat.com
Please review, thanks
在 2021/3/20 1:04, huang...@chinatelecom.cn 写道:
From: Hyman
Guestperf tool does not cover the multifd-enabled migration
currently, it is worth supporting so that developers can
analysis the
On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote:
@@ -14809,14 +14811,15 @@ static void gen_pool32axf(CPUMIPSState *env,
DisasContext *ctx, int rt, int rs)
}
break;
case 0x05:
+if (!check_cp0_enabled(ctx)) {
+break;
+}
switch (mino
On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote:
Enhanced Virtual Address (EVA) instructions are restricted
to Kernel execution mode, thus not available on user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
RFC because I'd rather not use such #ifdef'ry again.
TODO: have the compiler eli
在 2021/4/15 1:23, huang...@chinatelecom.cn 写道:
From: Hyman Huang(黄勇)
introduce optional sample-pages argument in calc-dirty-rate,
making sample page count per GB configurable so that more
accurate dirtyrate can be calculated.
Signed-off-by: Hyman Huang(黄勇)
---
migration/dirtyrate.c | 32
On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote:
We already check for CP0 enabled at the beginning of gen_cp0(),
no need to check it again after.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 2 --
1 file changed, 2 deletions(-)
Having noticed the default case for th
On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote:
To avoid callers to emit dead code if check_cp0_enabled()
raise an exception, let it return a boolean value, whether
CP0 is enabled or not.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 7 +
On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote:
The nanoMIPS P.LS.E0 pool contains the EVA instructions,
which are privileged. Simplify by moving the CP0 check
at the top of the pool swich case.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 16 +---
1 file
On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote:
We already check for CP0 enabled at the beginning of gen_cp0(),
no need to check it again after.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 4/20/21 10:54 AM, Philippe Mathieu-Daudé wrote:
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the mis
On 4/17/21 9:18 AM, Markus Armbruster wrote:
John Snow writes:
On 4/14/21 11:04 AM, Markus Armbruster wrote:
John Snow writes:
Thanks for taking this on. I realize it's a slog.
(Update: much later: AUUUGH WHY DID I DECIDE TO WRITE DOCS. MY HUBRIS)
LOL!
Signed-off-by: John Snow
-
在 2021/3/10 0:55, Philippe Mathieu-Daudé 写道:
On 3/9/21 5:00 PM, huang...@chinatelecom.cn wrote:
From: Hyman
The test aborts and error message as the following be throwed:
"No such file or directory: '/var/tmp/qemu-migrate-{pid}.migrate",
when the unix socket migration test nearly done. The r
Fix building with Clang.
At the moment Clang does not define _CALL_SYSV as GCC does. From
clang/lib/Basic/Targets/PPC.cpp in getTargetDefines()..
// FIXME: The following are not yet generated here by Clang, but are
//generated by GCC:
//
// _SOFT_FLOAT_
// __RECIP_PRECISION_
Fix building with Clang.
At the moment Clang does not define _CALL_SYSV as GCC does. From
clang/lib/Basic/Targets/PPC.cpp in getTargetDefines()..
// FIXME: The following are not yet generated here by Clang, but are
//generated by GCC:
//
// _SOFT_FLOAT_
// __RECIP_PRECISION_
On Tue, Apr 20, 2021 at 9:03 PM Vivek Goyal wrote:
> On Tue, Apr 20, 2021 at 05:46:36PM +0200, Mahmoud Mandour wrote:
> > Replaced the allocation and deallocation of fuse_req structs
> > using calloc()/free() call pairs to a GLib's g_try_new0()
> > and g_free().
>
> Hi,
>
> What's the context of
On Tue, Apr 20, 2021 at 6:01 PM Alexander Wagner
wrote:
>
> The IBEX documentation [1] specifies the reset vector to be "the most
> significant 3 bytes of the boot address and the reset value (0x80) as
> the least significant byte".
>
> [1]
> https://github.com/lowRISC/ibex/blob/master/doc/03_ref
On 4/20/21 6:06 PM, Aleksandar Rikalo wrote:
> Hi Philippe,
>
>> The plan is to drop the nanoMIPS disassembler because it is broken
>> since more than 2 years and nobody ever cared to fix it after
>> Stefan's attempt in Nov 2018:
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg576504.ht
Thanks to Stefan for the help -- IRL we debugged this to the following assert
failure:
assert(QSIMPLEQ_EMPTY(&ctx->bh_slice_list));
This has been resolved upstream in
https://github.com/qemu/qemu/commit/c81219a7dd36a815bd85beed9932fc973d4f5d51
** Changed in: qemu
Status: New => Confi
The wfi exception trigger behavior should take into account user mode,
hstatus.vtw, and the fact the an wfi might raise different types of
exceptions depending on various factors:
If supervisor mode is not present:
- an illegal instruction exception should be generated if user mode
executes and w
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fifth release candidate for the QEMU 6.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-6.0.0-rc4.tar.xz
http://downlo
On Sun, Apr 18, 2021 at 07:57:08AM +0200, Philippe Mathieu-Daudé wrote:
> Since commit 2cdfcf272d ("memory: assign MemoryRegionOps to all
> regions"), all newly created regions are assigned with
> unassigned_mem_ops (which might be then overwritten).
>
> When using aliased container regions, and t
On Tue, Apr 20, 2021 at 11:10:26AM +0200, Philippe Mathieu-Daudé wrote:
> On 4/20/21 9:00 AM, Mark Cave-Ayland wrote:
> > On 19/04/2021 21:58, Philippe Mathieu-Daudé wrote:
> >
> >> Hi Mark,
> >>
> >> On 4/19/21 10:13 PM, Mark Cave-Ayland wrote:
> >>> On 17/04/2021 15:02, Philippe Mathieu-Daudé wr
On Apr 19 16:18, Gollu Appalanaidu wrote:
Currently IO Command Set Profile feaure is supported, but
feature support flag not set and this feature is changable
add support for that.
Remove filling default value of feature in CQE CDW0 with zero,
since it fallbacks to default case and it is zero in
On Apr 16 12:52, Gollu Appalanaidu wrote:
Currently in compare command metadata aio read blk_aio_preadv return
value ignored, consider it and complete the block accounting.
Signed-off-by: Gollu Appalanaidu
---
hw/block/nvme.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/bl
On Apr 16 17:29, Gollu Appalanaidu wrote:
Currently LBAF formats are being intialized based on metadata
size if and only if nvme-ns "ms" parameter is non-zero value.
Since FormatNVM command being supported device parameter "ms"
may not be the criteria to initialize the supported LBAFs.
Signed-of
Enhanced Virtual Address (EVA) instructions are restricted
to Kernel execution mode, thus not available on user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
RFC because I'd rather not use such #ifdef'ry again.
TODO: have the compiler elide this code.
target/mips/translate.c | 14 +++
To avoid callers to emit dead code if check_cp0_enabled()
raise an exception, let it return a boolean value, whether
CP0 is enabled or not.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 7 ++-
target/mips/translate.c | 4 +++-
2 files ch
If CP0 is disabled, it is pointless to emit more code,
since the 'coprocessor unusable' exception will be raised.
Use the returned value from check_cp0_enabled() to return
early.
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 144 +
The nanoMIPS P.LS.E0 pool contains the EVA instructions,
which are privileged. Simplify by moving the CP0 check
at the top of the pool swich case.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 16 +---
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git
We already check for CP0 enabled at the beginning of gen_cp0(),
no need to check it again after.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5dad75cdf37..9acca6ef045
Address the following remark from Richard:
(1) check_cp0_enabled must return a boolean, so that the
caller can avoid emitting dead code after the
exception is emitted.
https://www.mail-archive.com/qemu-devel@nongnu.org/msg800114.html
Based-on: <20210420175426.1875746-1-f4...@amsat.org
On Sat, Apr 17, 2021 at 12:30:17PM +0200, Philippe Mathieu-Daudé wrote:
> AddressSpace are physical address view and shouldn't be using
> non-zero base address. The correct way to map a MR used as AS
> root is to use a MR alias.
Today when I rethink this, I figured another way (maybe easier?) to f
On Tue, Apr 20, 2021 at 05:46:36PM +0200, Mahmoud Mandour wrote:
> Replaced the allocation and deallocation of fuse_req structs
> using calloc()/free() call pairs to a GLib's g_try_new0()
> and g_free().
Hi,
What's the context of these patches. I see all of them are switching
to glib functions. W
> > What I was doing was to only register the spr once, and use the
> > accel-specific functions to set the relevant attributes, so spr_common
> > wouldn't need to where (and if) spr_read_* exists or not.
> > Would this work?
> >
> > Just ignoring the read and write functions means we still need
>
On Mon, Apr 19, 2021 at 05:11:42PM +0200, Greg Kurz wrote:
> Honor the expected behavior of syncfs() to synchronously flush all
> data and metadata on linux systems. Like the ->sync_fs() superblock
> operation in the linux kernel, FUSE_SYNCFS has a 'wait' argument that
> tells whether the server sh
On Sat, Apr 17, 2021 at 12:30:18PM +0200, Philippe Mathieu-Daudé wrote:
> The RAM container is exposed as an AddressSpace.
I didn't see where did ram_container got exposed as an address space.
I see it's added as one subregion of get_system_memory(), which looks okay?
--
Peter Xu
>> spapr_hcall.c:
>> function h_enter call ppc_hash64_hpte_page_shift_noslb,
>> ppc_hash64_map_hptes and ppc_hash64_unmap_hptes
>> function remove_hpte call ppc_hash64_map_hptes, ppc_hash64_unmap_hptes
>> and ppc_hash64_tlb_flush_hpte
>> function h
Signed-off-by: serge-sans-paille
---
docs/devel/control-flow-integrity.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/devel/control-flow-integrity.rst
b/docs/devel/control-flow-integrity.rst
index d89d707..e6b73a4 100644
--- a/docs/devel/control-flow-integrity.r
On 4/17/21 6:52 AM, Markus Armbruster wrote:
John Snow writes:
On 4/16/21 8:44 AM, Markus Armbruster wrote:
John Snow writes:
It will be an eventual thing, though: I think we need to agree on a
style guide document and in that same series, fix up the instances of
defying that guide. I thin
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson
Signed-off-
On Thu, Apr 15, 2021 at 08:14:30PM +0100, Dr. David Alan Gilbert wrote:
> * Paolo Bonzini (pbonz...@redhat.com) wrote:
> > On 06/04/21 13:42, Vitaly Kuznetsov wrote:
> > > older machine types are still available (I disable it for <= 5.1 but we
> > > can consider disabling it for 5.2 too). The featu
my patches went in, ultimately, and my focus was since shifted
elsewhere. I just tried this by *manually* adding some extra data to a
bitmap by hand.
qemu-img create -f qcow2 foo.qcow2 64m
qemu-img bitmap --add foo.qcow2 mybitmap
This creates a bitmap extension header like this (starting at 0x1f
Sorry, that formatted *terribly*... please see the attachment for a raw
text version with arbitrarily long columns that looks nicer. :(
** Attachment added: "Raw text for comment #7 with better formatting (?)"
https://bugs.launchpad.net/qemu/+bug/1808928/+attachment/5490362/+files/bztemp
--
On Mon, Apr 19, 2021 at 09:27:47PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> This series consists of various clean up patches.
>
> The final patch moves nvme emulation from hw/block to hw/nvme.
Series looks good to me.
Reviewed-by: Keith Busch
Hello,
Quick update about this work:
- the hotunplug timeout was reverted in the pSeries machine for 6.0.0.
This means that we have no use for a DEVICE_NOT_DELETED event or similar.
I'll drop it for the next version of the series.
- there is a good chance that the pSeries kernel will introduce
On Tue, Apr 20, 2021 at 07:19:40PM +0300, Valeriy Vdovin wrote:
[...]
> +##
> +# @query-cpu-model-cpuid:
> +#
> +# Returns description of a virtual CPU model, created by QEMU after cpu
> +# initialization routines. The resulting information is a reflection of a
> parsed
> +# '-cpu' command line op
20.04.2021 19:19, Valeriy Vdovin wrote:
Introducing new qapi method 'query-cpu-model-cpuid'. This method can be used to
get virtualized cpu model info generated by QEMU during VM initialization in
the form of cpuid representation.
[..]
+CpuModelCpuidDescription *qmp_query_cpu_model_cpuid(Err
"Matheus K. Ferst" writes:
> On 20/04/2021 09:20, Alex Bennée wrote:
>> David Gibson writes:
>>
>>> On Mon, Apr 19, 2021 at 10:33:07PM -0300, matheus.fe...@eldorado.org.br
>>> wrote:
From: Matheus Ferst
A newer compiler is needed to build tests for Power10 instructions. As
>>
20.04.2021 18:04, Kevin Wolf wrote:
Am 20.04.2021 um 16:31 hat Vladimir Sementsov-Ogievskiy geschrieben:
15.04.2021 18:22, Kevin Wolf wrote:
In order to avoid RMW cycles, is_allocated_sectors() treats zeroed areas
like non-zero data if the end of the checked area isn't aligned. This
can improve
At this moment, PAPR does not provide a way to report errors during a
device removal operation. This led the pSeries machine to implement
extra mechanisms to try to fallback and recover from an error that might
have happened during the hotunplug in the guest side. This started to
change a bit with
Changes from v1:
- added more context in the commit message
- added David's R-b
v1 link: https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg03145.html
Hi,
This is the QEMU side of a kernel change being proposed in [1],
where an attempt to implement a CPU hotunplug error report
mechanism wa
On 4/20/21 6:06 PM, Aleksandar Rikalo wrote:
> Hi Philippe,
>
>> The plan is to drop the nanoMIPS disassembler because it is broken
>> since more than 2 years and nobody ever cared to fix it after Stefan's
>> attempt in Nov 2018:
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg576504.html
Patchew URL:
https://patchew.org/QEMU/20210420161940.24306-1-valeriy.vdo...@virtuozzo.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210420161940.24306-1-valeriy.vdo...@virtuozzo.com
Subject: [PATCH v6] qapi: in
Introducing new qapi method 'query-cpu-model-cpuid'. This method can be used to
get virtualized cpu model info generated by QEMU during VM initialization in
the form of cpuid representation.
Diving into more details about virtual cpu generation: QEMU first parses '-cpu'
command line option. From t
Hello,
Thanks for the patch. Comments below:
On Tue, Apr 20, 2021 at 05:37:36PM +0800, Chenyi Qiang wrote:
> Virtual Machines can exploit bus locks to degrade the performance of
> system. To address this kind of performance DOS attack, bus lock VM exit
> is introduced in KVM and it will report t
@smoser : fixed-size VHD images don't have a header, and there is AFAIK
currently no way for probing a footer in the QEMU code, so relying on
the extension seems to be the only way right now, as far as I can tell.
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** Tags added: block
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https://bugs.launchpad.net/bugs/304636
Title:
-hda FAT:. limited to 504MBytes
Status in QEMU:
Confirmed
Status in qemu package in Ubuntu:
Won't Fix
Bug desc
Hi Philippe,
> The plan is to drop the nanoMIPS disassembler because it is broken
> since more than 2 years and nobody ever cared to fix it after Stefan's
> attempt in Nov 2018:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg576504.html
> So it is certainly unused. Unused unmaintained cod
Changed the allocations of some local variables to GLib's allocation
functions, such as g_try_malloc0(), and annotated those variables
as g_autofree. Subsequently, I was able to remove the calls to free().
Signed-off-by: Mahmoud Mandour
Reviewed-by: Stefan Hajnoczi
---
tools/virtiofsd/passthrou
Changed the allocations of fv_VuDev structs, VuDev structs, and
fv_QueueInfo strcuts from using calloc()/realloc() & free() to using
the equivalent functions from GLib.
In instances, removed the pair of allocation and assertion for
non-NULL checking with a GLib function that aborts on error.
Remo
Replaced the allocation of local variables from malloc() to
GLib allocation functions.
In one instance, dropped the usage to an assert after a malloc()
call and used g_malloc() instead.
Signed-off-by: Mahmoud Mandour
Reviewed-by: Stefan Hajnoczi
---
tools/virtiofsd/fuse_virtio.c | 9 -
Replaced (re)allocation of lo_map_elem structs from realloc() to
GLib's g_try_realloc_n() and replaced the respective free() call
with a g_free().
Signed-off-by: Mahmoud Mandour
Reviewed-by: Stefan Hajnoczi
---
tools/virtiofsd/passthrough_ll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deleti
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