On 2021/3/26 21:18, Tarun Gupta wrote:
> Document interfaces used for VFIO device migration. Added flow of state
> changes
> during live migration with VFIO device. Tested by building docs with the new
> vfio-migration.rst file.
>
> v3:
> - Add introductory line about VM migration in general.
> -
On Fri, Mar 26, 2021 at 8:54 PM BALATON Zoltan wrote:
>
> On Fri, 26 Mar 2021, Howard Spoelstra wrote:
> > On Fri, Mar 26, 2021 at 10:00 AM Bin Meng wrote:
> >>
> >> On Fri, Mar 26, 2021 at 4:49 PM Jason Wang wrote:
> >>>
> >>>
> >>> 在 2021/3/26 下午4:21, BALATON Zoltan 写道:
> On Fri, 26 Mar 2
Many files include hw/irq.h without needing it. Remove the superfluous
include statements.
Signed-off-by: Thomas Huth
---
hw/arm/msf2-soc.c | 1 -
hw/i386/kvm/ioapic.c| 1 -
hw/i386/xen/xen_platform.c | 1 -
hw/m68k/q800.c | 1 -
hw/m68k/virt.c | 1 -
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1886793
Title:
"go install
Hi all,
Recently, I did some tests on SMMU nested mode. Here is
a question about the translation granule size supported by
vSMMU.
There is such a code in SMMUv3_init_regs():
/* 4K and 64K granule support */
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
s->idr[5] = FIELD_DP32(s
The kernel allows a NULL msg in recvfrom so that he size of the next
message may be queried before allocating a correctly sized buffer. This
change allows the syscall translator to pass along the NULL msg pointer
instead of returning early with EFAULT.
Signed-off-by: Zach Reizner
---
v2:
- retur
OpenBSD added support for tap(4) 10 releases ago.
Remove the special casing for older releases.
Signed-off-by: Brad Smith
diff --git a/net/tap-bsd.c b/net/tap-bsd.c
index 77aaf674b1..59dfcdfae0 100644
--- a/net/tap-bsd.c
+++ b/net/tap-bsd.c
@@ -35,10 +35,6 @@
#include
#endif
-#if defined(
On 3/26/21 3:27 PM, Peter Maydell wrote:
> On Tue, 23 Mar 2021 at 16:14, Philippe Mathieu-Daudé wrote:
>>
>> We want to remove the bcm2835_fb_reset() call in bcm2835_fb_realize()
>> but doing triggers:
>>
>> hw/display/bcm2835_fb.c:131:13: runtime error: store to null pointer of
>> type 'uint32
On 3/26/21 1:27 AM, Philippe Mathieu-Daudé wrote:
> Instead of using a device specific feature for mapping the
> flash memory multiple times over a wider region, use the
> generic memory_region_add_subregion_aliased() helper.
>
> There is no change in the memory layout.
- before:
(qemu) info m
Patchew URL: https://patchew.org/QEMU/cover.1616794852.git.lukasstra...@web.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: cover.1616794852.git.lukasstra...@web.de
Subject: [PATCH v5 0/4] yank: Add chardev tests and
Add tests for yank with the chardev-change case.
Signed-off-by: Lukas Straub
Reviewed-by: Marc-André Lureau
Tested-by: Li Zhang
---
MAINTAINERS| 1 +
tests/unit/meson.build | 3 +-
tests/unit/test-yank.c | 200 +
3 files changed, 203 inse
Always pass the id to chardev_new, since it is needed to register
the yank instance for the chardev. Also, after checking that
nothing calls chardev_new with id=NULL, assert() that id!=NULL.
This fixes a crash when using chardev-change to change a chardev
to chardev-socket, which attempts to regis
When changing from chardev-socket (which supports yank) to
chardev-socket again, it fails, because the new chardev attempts
to register a new yank instance. This in turn fails, as there
still is the yank instance from the current chardev. Also,
the old chardev shouldn't unregister the yank instance
Move object_property_try_add_child out of chardev_new into it's
callers. This is a preparation for the next patches to fix yank
with the chardev-change case.
Signed-off-by: Lukas Straub
Reviewed-by: Marc-André Lureau
Tested-by: Li Zhang
---
chardev/char.c | 42 -
Hello Everyone,
These patches increase test coverage for yank, add tests and fix bugs and
crashes in yank in combination with chardev-change.
Please Review.
Regards,
Lukas Straub
Changes:
-v5:
-test: fix memory leak
-v4:
-test: fix CharChangeTestConfig structs on stack going out of scope
-tes
Hi Jason,
On 3/26/21 12:24 AM, Jason Wang wrote:
>
> 在 2021/3/26 下午1:44, Dongli Zhang 写道:
>> The virtio device/driver (e.g., vhost-scsi or vhost-net) may hang due to
>> the loss of doorbell kick, e.g.,
>>
>> https://urldefense.com/v3/__https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg0171
Hi Lukas
On Fri, Mar 26, 2021 at 11:48 AM Lukas Straub wrote:
> Add tests for yank with the chardev-change case.
>
> Signed-off-by: Lukas Straub
> ---
> MAINTAINERS| 1 +
> tests/unit/meson.build | 3 +-
> tests/unit/test-yank.c | 199 +
Lukas Straub writes:
> On Fri, 26 Mar 2021 17:52:40 +
> Peter Maydell wrote:
>
>> On Fri, 26 Mar 2021 at 17:34, Lukas Straub wrote:
>> >
>> > The following changes since commit
>> > 5ca634afcf83215a9a54ca6e66032325b5ffb5f6:
>> >
>> > Merge remote-tracking branch 'remotes/philmd/tags/sdmm
Hi
On Sat, Mar 27, 2021 at 12:56 AM Markus Armbruster
wrote:
> Lukas Straub writes:
>
> > On Fri, 26 Mar 2021 17:52:40 +
> > Peter Maydell wrote:
> >
> >> On Fri, 26 Mar 2021 at 17:34, Lukas Straub wrote:
> >> >
> >> > The following changes since commit
> 5ca634afcf83215a9a54ca6e66032325b
Finally, after all the preparations, when we have the whole
infrastructure of inflight-write-counters prepared in previous commits,
let's fix the following bug:
1. Start write to qcow2. Assume guest cluster G and corresponding host
cluster is H.
2. The write requests come to the point of data
We have a bug in qcow2: assume we've started data write into host
cluster A. s->lock is unlocked. During the write the refcount of
cluster A may become zero, cluster may be reallocated for other needs,
and our in-flight write become a use-after-free.
To fix the bug let's do the following. Or bette
Here refcount of cluster at @cluster_offset reached 0, so we "free"
that cluster. Not a cluster at @offset. The thing that save us from the
bug is that L2 tables and refblocks are discarded one by one. Still,
let's be precise.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2-refcount.
Simple test:
- start writing to allocated cluster A
- discard this cluster
- write to another unallocated cluster B (it's allocated in same place
where A was allocated)
- continue writing to A
For now last action pollutes cluster B which is a bug fixed by the
following commit.
For now, add
Hi all!
It's an alternative lock-less solution to
[PATCH v4 0/3] qcow2: fix parallel rewrite and discard (rw-lock)
It's an updated version of what was don in
[PATCH v3 0/6] qcow2: compressed write cache
I've split the logic into several patches, add a lot more comments and
documentation, I h
We are going to change the concept of "free host cluster", so let's
clarify it now and add a helper, which we will modify later.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2-refcount.c | 31 +--
1 file changed, 25 insertions(+), 6 deletions(-)
diff --g
static const struct masks ast2600_masks = {
-.src = 0x7fff,
-.dest = 0x7ff8,
-.len = 0x0fff,
+.src = 0x7fff,
+.dest= 0x7ff8,
+.len = 0x0fff,
};
Apologies for that - Need to proof-read my patches better,
even if it'
On 3/26/21 10:19 AM, Markus Armbruster wrote:
When I look at docs/qemu-qmp-ref.7 with less -R, I see
ReplicationMode (Enum)
An enumeration of replication modes.
Values
primary
Primary mode, the vm's state will be sent to secondary QEMU.
secondary
Pointer Authentication is an AARCH64-only ARMv8.3 optional
extension, whose cpu properties can be separated out in its own module.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h | 3 --
target/arm/tcg/cpu-pauth.h | 34
target/arm/cpu.c | 4 +--
tar
modules under tcg/ are only built for CONFIG_TCG anyway.
Signed-off-by: Claudio Fontana
---
target/arm/tcg/vfp_helper.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c
index 521719f327..0cc6c85270 100644
--- a/target/arm/tcg/vfp_
aarch64_sve_narrow_vq and aarch64_sve_change_el are SVE-related
functions only used for TCG, so we can put them in the
tcg-sve.c module.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h | 7 ---
target/arm/tcg/tcg-sve.h | 7 +++
linux-user/syscall.c | 4
make them canonical for the module name.
Signed-off-by: Claudio Fontana
---
target/arm/tcg/tcg-sve.h | 4 ++--
linux-user/syscall.c | 2 +-
target/arm/cpu-exceptions-aa64.c | 2 +-
target/arm/tcg/cpregs.c | 2 +-
target/arm/tcg/helper-a64.c | 2 +-
target/arm/tc
On Fri, 26 Mar 2021, Howard Spoelstra wrote:
On Fri, Mar 26, 2021 at 10:00 AM Bin Meng wrote:
On Fri, Mar 26, 2021 at 4:49 PM Jason Wang wrote:
在 2021/3/26 下午4:21, BALATON Zoltan 写道:
On Fri, 26 Mar 2021, Howard Spoelstra wrote:
On Fri, Mar 26, 2021 at 2:50 AM Bin Meng wrote:
Hi Howard
extract the exception handling code from cpu-sysemu,
and split it into general arm code and an AArch64-specific part.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-exceptions-aa64.h | 32 +
target/arm/cpu.h | 4 -
target/arm/arch_dump.c | 1 +
target/arm/cpu-ex
Signed-off-by: Claudio Fontana
---
target/arm/helper-a64.h | 2 ++
target/arm/helper.h | 1 -
target/arm/tcg/helper.c | 14 ++
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index c139fa81f9..342f55d577 100644
---
On 26.03.21 16:17, Eric Blake wrote:
On 3/26/21 9:55 AM, Max Reitz wrote:
Three test cases:
(1) Adding a qcow2 (metadata) file to an existing data file, see whether
we can read the existing data through the qcow2 image.
(2) Append data to the data file, grow the qcow2 image accordingly, see
this will allow us to restrict more code to TARGET_AARCH64
Signed-off-by: Claudio Fontana
---
target/arm/arch_dump.c | 12 +++-
target/arm/cpu.c | 1 -
target/arm/cpu64.c | 4
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm/arch_dump.c b/target
use a canonical module prefix followed by the get_zcr_len_for_el()
method name. Also rename the static internal auxiliary function,
where the module prefix is not necessary.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sve.h | 2 +-
target/arm/arch_dump.c | 2 +-
target/arm/cpu-sve.c
extract the SVE-related cpu object properties and functions,
and move them to a separate module.
Disentangle SVE from pauth that is a separate, TCG-only feature.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sve.h | 37
target/arm/cpu.h | 14 +-
target/arm/cpu-sve.c |
We have a bug in qcow2: assume we've started data write into host
cluster A. s->lock is unlocked. During the write the refcount of
cluster A may become zero, cluster may be reallocated for other needs,
and our in-flight write become a use-after-free. More details will be
in the further commit which
when TARGET_AARCH64 is not defined, it is helpful to make
is_aa64() and arm_el_is_aa64 macros defined to "false".
This way we can make more code TARGET_AARCH64-only.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h| 37 -
target/arm/cpu-mmu-sys
now that we handled the dependency between HELPER(), cpregs defs
and functions in tcg/,
we can make sve_zcr_len_for_el TARGET_AARCH64-only,
and move it to the cpu-sve module.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sve.h| 3 +++
target/arm/cpu.h| 4 ++--
target/arm/arch_
move init, realizefn and reset code into it.
Signed-off-by: Claudio Fontana
---
target/arm/internals.h | 1 -
target/arm/cpu-sysemu.c| 32 --
target/arm/cpu.c | 48 ++
target/arm/kvm/kvm-cpu.c | 128 +
target/arm/kvm
we need to be careful not to use
if (tcg_enabled())
here, because of the VMSTATE definitions in machine.c,
which are only protected by CONFIG_TCG, and thus
it would break the --enable-tcg --enable-kvm build.
Signed-off-by: Claudio Fontana
---
target/arm/tcg/tcg-cpu.h| 1 +
target/arm/
move init, realizefn and reset code into it.
Signed-off-by: Claudio Fontana
Cc: Paolo Bonzini
---
target/arm/tcg/tcg-cpu.h| 4 ++-
target/arm/cpu.c| 44 ++
target/arm/tcg/sysemu/tcg-cpu.c | 27
target/arm/tcg/tcg-cpu-models.c | 1
the functions used in machine.c are now protected via
if (kvm_enabled()), so the stub is not needed.
Signed-off-by: Claudio Fontana
---
target/arm/kvm-stub.c | 24
1 file changed, 24 deletions(-)
delete mode 100644 target/arm/kvm-stub.c
diff --git a/target/arm/kvm-stub
The QEMU PSCI implementation is not used for KVM,
we do not need the kvm constants header.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/arm-powerctl.h | 2 --
target/arm/psci.c | 1 -
2 files changed, 3 deletions(-)
diff --git a/target/arm/arm-powerctl.h
Complement the Aspeed HACE support with Scatter-Gather hash support for
sha256 and sha512. Scatter-Gather is only supported on AST2600-series.
Signed-off-by: Klaus Heinrich Kiwi
---
docs/system/arm/aspeed.rst | 2 +-
hw/misc/aspeed_hace.c | 126 +++--
2 fil
On Fri, Mar 26, 2021 at 3:21 AM ChangLimin wrote:
> >On Thu, Mar 25, 2021 at 8:07 AM ChangLimin
> wrote:
> >>On Wed, Mar 24, 2021 at 4:52 PM Max Reitz wrote:
> >>On 22.03.21 10:25, ChangLimin wrote:
> >>> For Linux 5.10/5.11, qemu write zeros to a multipath device using
> >>> ioctl(fd, BLKZEROO
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
Cc: Philippe Mathieu-Daudé
This reverts commit 6e937ba7f8fb90d66cb3781f7fed32fb4239556a
This change breaks quickly at startup, as all interfaces in boards
are checked in vl.c in select_machine():
{
GSList *machines = object_class_get_list(TYPE_MACHINE, false);
}
In order to restrict v8M IDAU to TCG,
we need to first disa
and adapt the code including the header references,
and trace-events / trace.h
Signed-off-by: Claudio Fontana
---
meson.build | 2 +-
target/arm/cpu.h | 2 +-
target/arm/{ => kvm}/kvm-consts.h | 0
target/arm/{ => kvm}/kvm_arm.h| 0
target/arm/kvm/trace
it is needed just once, so just move the CONFIG_TCG check in place.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-mmu.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu-mmu.c b/target/arm/cpu-mmu.c
index c6ac90a61e..9969bc9d30 100644
--- a/target/ar
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
---
target/arm/{cpu_tcg.c => tcg/tcg-cpu-models.c} | 9 +
target/arm/meson.build | 4
target/arm/tcg/meson.build
There might be more than just KVM and TCG in the future,
so where appropriate, replace broad "else" statements
with the appropriate if (accel_enabled()) check.
Also invert some checks for !kvm_enabled() or !tcg_enabled()
where it seems appropriate to do so.
Note that to make qtest happy we need t
These operations are supported on AST2600 series of machines.
Signed-off-by: Klaus Heinrich Kiwi
---
Changes since V2:
* Fixed spurious comment removing conditional
Changes since V1:
* Use address_space_ldl_le() to load single addresses instead of
address_space_map()
* Updated documenta
cpu.c,
cpu32.c,
cpu64.c,
tcg/sysemu/tcg-cpu.c,
all need a good cleanup when it comes to included header files.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.c| 8 ++--
target/arm/cpu32.c | 14 --
target/arm/cpu64.c | 6 --
targ
XXX Someone who really understands which properties should be added
where should review this attentively.
What goes into cpu leaf class initialization?
What goes into arm_post_init / accel_cpu?
What goes into arm_cpu_finalize_features / aarch64_cpu_finalize_features?
Should there be shift of more
cpu-sysemu.c:
we need this sysemu code for KVM too, so we move the code to
cpu-sysemu.c. There will be further split later on in dedicated
exception modules for 32 and 64bit.
tcg/sysemu/tcg-cpu.c:
the TCG-specific code we put in tcg/sysemu/, in preparation
for the addition of the tcg-cpu accel-c
test is TCG-only.
Signed-off-by: Claudio Fontana
Cc: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index e020c83d2a..bd7b85909c 100644
--- a/tests/qtest/bios-ta
all the features in arm_cpu_finalize_features are actually
TARGET_AARCH64-only, since KVM is now only supported on 64bit.
Therefore move the function to cpu64, and rename it to
aarch64_cpu_finalize_features.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h | 3 +-
target/arm/kvm/kvm
before refactoring the exception code, fix the style of the
functions being moved.
Signed-off-by: Claudio Fontana
---
target/arm/tcg/helper.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index aaa307daca.
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
Cc: Philippe Mathieu-Daudé
provide helper functions there to initialize 32bit models,
and export the a15 cpu model.
We still need to keep around a15 until we sort out the board configurations.
cpu.c will continue to contain the common parts between
32 and 64.
Note that we need to build cpu32 also for TARGET_AARCH64,
becau
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-common.c | 42 +
target/arm/tcg/helper.c | 41
2 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/target/arm/cpu-common.
restrict zcr_el1, zcr_el2, zcr_no_el2, zcr_el3 reginfo,
and the related SVE functions to TARGET_AARCH64.
Signed-off-by: Claudio Fontana
---
target/arm/tcg/cpregs.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index
it is required by arch-dump.c and cpu.c, so apparently
we need this for KVM too
Signed-off-by: Claudio Fontana
---
target/arm/cpu-common.c | 43 +
target/arm/tcg/helper.c | 33 ---
2 files changed, 43 insertions(+), 33 deletions
before moving over sve_exception_el from the helper code,
cleanup the style.
Signed-off-by: Claudio Fontana
---
target/arm/tcg/helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 5ec8f9c005..e4f18bcaa7 1006
put the KVM-specific and TCG-specific functionality
in the respective subdirectories kvm/ and tcg/
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sve.h | 2 +-
target/arm/kvm/kvm-sve.h | 30 +++
target/arm/tcg/tcg-sve.h | 24 ++
target/arm/cpu-sve.c | 166 +
move the TCGCPUOps interface to tcg/tcg-cpu.c
in preparation for the addition of the TCG accel-cpu class.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h | 1 -
target/arm/internals.h | 5 -
target/arm/tcg/tcg-cpu.h | 6 +
target/arm/cpu-sysemu.c| 4 +
target/arm/
this function is used for kvm too, add it to the
cpu-common module.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-common.c | 15 +++
target/arm/tcg/helper.c | 11 ---
2 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu-common.c b/target/arm/cpu
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-mmu.c| 95 +
target/arm/tcg/helper.c | 95 -
2 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/target/arm/cpu-mmu.c
Signed-off-by: Claudio Fontana
---
target/arm/cpu.c | 4
target/arm/kvm/kvm-cpu.c | 1 +
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5a76461e5b..5e0f6bd01d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -778,10 +778
After this patch it is possible to build only kvm:
./configure --disable-tcg --enable-kvm
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-sysemu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/
in preparation of the creation of a new cpregs module,
fix the style for the to-be-exported code.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h| 54 ---
target/arm/tcg/helper.c | 313 ++--
2 files changed, 241 insertions(+), 126 deletions(-)
cpu-vfp.c: vfp_get_fpsr and vfp_set_fpsr are needed also for KVM,
so create a new cpu-vfp.c
tcg/cpu-vfp.c: vfp_get_fpscr_from_host and vv are TCG-only, so we
move the implementation to tcg/cpu-vfp.c
Signed-off-by: Claudio Fontana
---
target/arm/cpu-vfp.h| 29 +
Expand current Aspeed HACE testsuite to also include Scatter-Gather of
sha256 and sha512 operations.
Signed-off-by: Klaus Heinrich Kiwi
---
tests/qtest/aspeed_hace-test.c | 156 +++--
1 file changed, 147 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/aspeed_h
Skip the test_device_intro_concrete for now for ARM KVM-only build,
as on ARM we currently build devices for ARM that are not
compatible with a KVM-only build.
We can remove this workaround when we fix this in KConfig etc,
and we only list and build machines that are compatible with KVM
for KVM-on
the armv7m one should go away with proper
configuration changes (only enabling possible boards for KVM).
Signed-off-by: Claudio Fontana
---
target/arm/tcg/helper-stubs.c | 21 +
target/arm/tcg/meson.build| 3 +++
2 files changed, 24 insertions(+)
create mode 100644 targ
this should go away once the configuration and hw/arm is clean
Signed-off-by: Claudio Fontana
---
hw/arm/boot.c | 5 -
target/arm/arm-powerctl.c | 8 +---
target/arm/tcg/helper-stubs.c | 5 +
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/arm/b
we will need this for KVM too, especially for Nested support.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-common.c | 68 +
target/arm/tcg/helper.c | 68 -
2 files changed, 68 insertions(+), 68 deletions(-)
dif
sve_tests_sve_max_vq_8,
sve_tests_sve_off,
test_query_cpu_model_expansion
all require TCG to run. Skip them for KVM-only builds.
Signed-off-by: Claudio Fontana
---
tests/qtest/arm-cpu-features.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/arm-cpu-features.c
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-common.c | 41 +
target/arm/tcg/helper.c | 29 -
target/arm/meson.build | 1 +
3 files changed, 42 insertions(+), 29 deletions(-)
create mode 10
we need as a result to move switch_mode too,
so we put an implementation into cpu_user and cpu_sysemu.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h| 2 +
target/arm/cpu-common.c | 192 +++
target/arm/cpu-sysemu.c | 30 ++
target/arm/cpu-user.
we need this for KVM too.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-sysemu.c | 62 +++
target/arm/cpu-user.c | 5
target/arm/tcg/helper.c | 64 -
3 files changed, 67 insert
before exporting some functionality from helper.c into a new module,
fix the comment style of those functions.
Signed-off-by: Claudio Fontana
---
target/arm/tcg/helper.c | 152 ++--
1 file changed, 101 insertions(+), 51 deletions(-)
diff --git a/target/arm/tc
move sysemu-only parts of debug_helper to sysemu/
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/debug_helper.c| 27 ---
target/arm/tcg/sysemu/debug_helper.c | 33
target/arm/tcg/sysemu/meson.build|
and arm_phys_excp_target_el since it is tied up inside the
same #ifdef block.
aarch64_sync_32_to_64 and aarch64_sync_64_to_32 are
mixed in with the TCG helpers, but they shouldn't, as they
are needed for KVM too.
kvm_arch_get_registers()
{
if (!is_a64(env)) {
aarch64_sync_64_to_32(env
move work is needed later on to split things into
tcg-specific portions and kvm-specific portions of this
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/internals.h | 8 ++-
target/arm/cpu-sysemu.c | 105
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/tlb_helper.h| 17 ++
target/arm/tcg/sysemu/tlb_helper.c | 83 ++
target/arm/tcg/tlb_helper.c| 96 ++
target/arm/tcg/user/tlb_helper.c | 31 ++
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
meson.build | 1 +
target/arm/{ => tcg}/op_addsub.h | 0
target/arm/tcg/trace.h | 1 +
target/arm/{ => tcg}/vec_internal.h | 0
target/arm/{ => tcg}/crypto_
of note, cpreg lists were previously initialized by TCG first,
and then thrown away and replaced with the data coming from KVM.
Now we just initialize once, either for TCG or for KVM.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 32 ++
We do not move psci.c to tcg/ because we expect other
hypervisors to use it (waiting for HVF enablement).
Signed-off-by: Claudio Fontana
Cc: Alexander Graf
---
target/arm/meson.build | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 01
allocation_tag_mem has a different implementation for
user-only and sysemu, so move the two implementations into
the dedicated subdirs.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/mte_helper.h| 53
target/arm/tcg/mte_helper.c| 191 +
Here a new version of the series that enables kvm-only builds.
The goal here is to enable the KVM-only build, but there is
some additional cleanup too.
In this iteration I mostly fixed existing issues, and added an attempt
to put more content in cpu-sve. More splitting still required
for both cpu
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
target/arm/tcg/meson.build | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 0bd4e9d954..3b4146d079 100644
--- a/targe
Signed-off-by: Claudio Fontana
---
target/arm/tcg/meson.build| 3 +++
target/arm/tcg/sysemu/meson.build | 2 ++
target/arm/tcg/user/meson.build | 2 ++
3 files changed, 7 insertions(+)
create mode 100644 target/arm/tcg/sysemu/meson.build
create mode 100644 target/arm/tcg/user/meson.bu
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
target/arm/{ => tcg}/translate-a64.h | 0
target/arm/{ => tcg}/translate.h | 0
target/arm/{ => tcg}/a32-uncond.decode| 0
target/arm/{ => tcg}/a32.decode | 0
target/arm/{
Expand current Aspeed HACE testsuite to also include Scatter-Gather of
sha256 and sha512 operations.
Signed-off-by: Klaus Heinrich Kiwi
---
tests/qtest/aspeed_hace-test.c | 156 +++--
1 file changed, 147 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/aspeed_h
On 3/26/2021 4:30 PM, Klaus Heinrich Kiwi wrote:
Complement the Aspeed HACE support with Scatter-Gather hash support for
+
+/*
+ * Set status bits to indicate completion. Testing shows hardware sets
+ * these irrespective of HASH_IRQ_EN.
+ */
+//if (!rc) {
+s->re
Complement the Aspeed HACE support with Scatter-Gather hash support for
sha256 and sha512. Scatter-Gather is only supported on AST2600-series.
Signed-off-by: Klaus Heinrich Kiwi
---
docs/system/arm/aspeed.rst | 2 +-
hw/misc/aspeed_hace.c | 126 +++--
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