Le 10/03/2021 à 00:06, Greg Kurz a écrit :
> On Tue, 9 Mar 2021 21:52:40 +0100
> Laurent Vivier wrote:
>
>> Le 22/02/2021 à 12:28, Greg Kurz a écrit :
>>> This is just an oversight.
>>>
>>> Fixes: f518be3aa35b ("target/ppc: Remove "compat" property of server class
>>> POWER CPUs")
>>> Cc: gr...@
Hi Alex,
On 2021/3/10 7:17, Alex Williamson wrote:
On Thu, 4 Mar 2021 21:34:46 +0800
Kunkun Jiang wrote:
The cpu_physical_memory_set_dirty_lebitmap() can quickly deal with
the dirty pages of memory by bitmap-traveling, regardless of whether
the bitmap is aligned correctly or not.
cpu_physica
Hi Philippe,
On Sat, Feb 20, 2021 at 4:58 PM Bin Meng wrote:
>
> From: Bin Meng
>
> At present the sd_erase() does not erase the requested range of card
> data to 0xFFs. Let's make the erase operation actually happen.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - fix the skip erase
The main tests directory still looks very crowded, and it's not
clear which files are part of a unit tests and which belong to
a different test subsystem. Let's clean up the mess and move the
unit tests to a separate directory.
Signed-off-by: Thomas Huth
---
MAINTAINERS
On 10/03/2021 07.12, Alexander Bulekov wrote:
I noticed that with a sufficiently small timeout, the fuzzer fork-server
sometimes locks up. On closer inspection, the issue appeared to be
caused by entering our SIGALRM handler, while libfuzzer is in it's crash
handlers. Because libfuzzer relies on
I noticed that with a sufficiently small timeout, the fuzzer fork-server
sometimes locks up. On closer inspection, the issue appeared to be
caused by entering our SIGALRM handler, while libfuzzer is in it's crash
handlers. Because libfuzzer relies on pipe communication with an
external child proces
I posted a reproducer for a different bug. Here are the correct
reproducer and stacktrace:
/*
* Autogenerated Fuzzer Test Case
*/
#include "qemu/osdep.h"
#include "libqos/libqtest.h"
/*
* cat << EOF | ./qemu-system-i386 -display none -machine accel=qtest \
* -m 512M -machine q35 -nodefaults
On Wed, Mar 10, 2021 at 11:36 AM Dylan Jhong wrote:
>
> This provides a RISC-V Board based on Andes's AE350 specification.
> The following machine is implemented:
>
> - 'andes_ae350'; PLIC, PLICSW, PLMT, 16550a UART, VirtIO MMIO, device-tree
Is this a virtual target because virtio is added? Or do
On Wed, Mar 10, 2021 at 11:34 AM Dylan Jhong wrote:
>
> Andes PLIC (Platform-Level Interrupt Controller) device provides an
> interrupt controller functionality based on Andes's PLIC specification.
>
> The Andes PLIC can handle either external interrupts (PLIC)
> or interprocessor interrupts (PLIC
Thomas Huth writes:
> We should say now when it was removed, not when it was deprecated.
>
> Signed-off-by: Thomas Huth
> ---
> docs/system/removed-features.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/docs/system/removed-features.rst
> b/docs/system/removed
On 09/03/2021 23.27, Philippe Mathieu-Daudé wrote:
ping?
I guess we really need someone who could act as a maintainer for the
tests/acceptance directory, who could pick up patches and send pull requests
if nobody else is picking up these patches...
Cleber, Wainer, Willian, any volunteers?
We should say now when it was removed, not when it was deprecated.
Signed-off-by: Thomas Huth
---
docs/system/removed-features.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/removed-features.rst b/docs/system/removed-features.rst
index f8db76d0b5..13f9dd3
On 10/03/2021 13:40, David Gibson wrote:
On Wed, Mar 10, 2021 at 12:55:07PM +1100, Alexey Kardashevskiy wrote:
On 10/03/2021 01:00, BALATON Zoltan wrote:
On Tue, 9 Mar 2021, Alexey Kardashevskiy wrote:
On 09/03/2021 16:29, David Gibson wrote:
+struct ClientArchitectureSupportClass {
+
Hi David,
On Wed, Mar 10, 2021 at 12:10 PM David Gibson
wrote:
>
> The following changes since commit b2ae1009d7cca2701e17eae55ae2d44fd22c942a:
>
> Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210307'
> into staging (2021-03-09 13:50:35 +)
>
> are available in the Git r
ui/cocoa does not receive NSEventTypeFlagsChanged when it is not active,
and the modifier state can be desynchronized in such a situation.
[NSEvent -modifierFlags] tells whether a modifier is *not* pressed, so
check it whenever receiving an event and clear the modifier if it is not
pressed.
Note
On Tue, Mar 09, 2021 at 06:28:44PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 09/03/2021 16:29, David Gibson wrote:
>
>
> > > > > +struct ClientArchitectureSupportClass {
> > > > > +InterfaceClass parent;
> > > > > +target_ulong (*cas)(CPUState *cs, target_ulong vec);
> > > > > +vo
From: Daniel Henrique Barboza
Recent changes allowed the pSeries machine to rollback the hotunplug
process for the DIMM when the guest kernel signals, via a
reconfiguration of the DR connector, that it's not going to release the
LMBs.
Let's also warn QAPI listerners about it. One place to do it
From: Daniel Henrique Barboza
Hotunplug for all other devices are warning the user when the hotunplug
is already in progress. Do the same for PCI devices in
spapr_pci_unplug_request().
Signed-off-by: Daniel Henrique Barboza
Message-Id: <20210226163301.419727-5-danielhb...@gmail.com>
Reviewed-by
From: Daniel Henrique Barboza
We are asserting the existence of the first DRC LMB after sending unplug
requests to all LMBs of the DIMM, where every DRC is being asserted
inside the loop. This means that the first DRC is being asserted twice.
Remove the duplicated assert.
Signed-off-by: Daniel
From: Daniel Henrique Barboza
The pSeries machine is using QEMUTimer internals to return the timeout
in seconds for a timer object, in hw/ppc/spapr.c, function
spapr_drc_unplug_timeout_remaining_sec().
Create a helper in qemu-timer.c to retrieve the deadline for a QEMUTimer
object, in ms, to avo
From: Vitaly Cheptsov
Failing to guard SPR access with gen_io_start/gen_stop_exception
causes "Bad icount read" exceptions when running VMs with
e500mc and e500v2 CPUs with an icount parameter.
Cc: David Gibson
Cc: Greg Kurz
Cc: Paolo Bonzini
Signed-off-by: Vitaly Cheptsov
Message-Id: <20210
From: Bin Meng
The eTSEC node should provide an empty property in the
eTSEC node, otherwise of_translate_address() in the Linux kernel
fails to get the eTSEC register base, reporting:
OF: ** translation for device /platform@f/ethernet@0/queue-group **
OF: bus is default (na=1, ns=1)
From: Cédric Le Goater
This moves the current documentation in files specific to each
platform family. PowerNV machine is updated, the other machines need
to be done.
Signed-off-by: Cédric Le Goater
Message-Id: <20210222133956.156001-1-...@kaod.org>
Reviewed-by: Greg Kurz
[dwg: Trivial capital
From: Daniel Henrique Barboza
Both CPU hotunplug and PC_DIMM unplug reports an user warning,
mentioning that the hotunplug is in progress, if consecutive
'device_del' are issued in quick succession.
Do the same for PHBs in spapr_phb_unplug_request().
Signed-off-by: Daniel Henrique Barboza
Mess
From: Daniel Henrique Barboza
Handling errors in memory hotunplug in the pSeries machine is more
complex than any other device type, because there are all the
complications that other devices has, and more.
For instance, determining a timeout for a DIMM hotunplug must consider
if it's a Hash-MMU
From: Daniel Henrique Barboza
There is a reliable way to make a CPU hotunplug fail in the pseries
machine. Hotplug a CPU A, then offline all other CPUs inside the guest
but A. When trying to hotunplug A the guest kernel will refuse to do it,
because A is now the last online CPU of the guest. PAPR
From: Daniel Henrique Barboza
When moving a physical DRC to "Available", drc_isolate_physical() will
move the DRC state to STATE_PHYSICAL_POWERON and, if the DRC is marked
for unplug, call spapr_drc_detach(). For physical DRCs,
drck->empty_state is STATE_PHYSICAL_POWERON, meaning that we're sure
From: Peter Maydell
We no longer need to include sm501_template.h multiple times, so
we can simply inline its contents into sm501.c.
Signed-off-by: Peter Maydell
Message-Id: <20210212180653.27588-4-peter.mayd...@linaro.org>
Acked-by: BALATON Zoltan
Signed-off-by: David Gibson
---
hw/display/
From: Peter Maydell
Now that we only include sm501_template.h for the DEPTH==32 case, we
can expand out the uses of the BPP, PIXEL_TYPE and PIXEL_NAME macros
in that header.
Signed-off-by: Peter Maydell
Message-Id: <20210212180653.27588-3-peter.mayd...@linaro.org>
Acked-by: BALATON Zoltan
Sign
From: Bin Meng
"qemu-common.h" should be included to provide the forward declaration
of qemu_hexdump() when HEX_DUMP is on.
Signed-off-by: Bin Meng
Message-Id: <20210228050431.24647-1-bmeng...@gmail.com>
Signed-off-by: David Gibson
---
hw/net/fsl_etsec/etsec.c | 1 +
hw/net/fsl_etsec/rings.c
From: Daniel Henrique Barboza
spapr_drc_detach() is not the best name for what the function does. The
function does not detach the DRC, it makes an uncommited attempt to do
it. It'll mark the DRC as pending unplug, via the 'unplug_request'
flag, and only if the DRC state is drck->empty_state it
From: Peter Maydell
For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel RGB. Remove the legacy dead
code from the sm501 display device which was handling the
possibility that the console surface was some other format.
Signed-off-by: Peter Maydell
From: Daniel Henrique Barboza
drc_isolate_logical() is used to move the DRC from the "Configured" to
the "Available" state, erroring out if the DRC is in the unexpected
"Unisolate" state and doing nothing (with RTAS_OUT_SUCCESS) if the DRC
is already in "Available" or in "Unusable" state.
When m
From: Fabiano Rosas
The commit d03b174a83 (target/ppc: simplify bcdadd/sub functions)
meant to simplify some of the code but it inadvertently altered the
way the CR6 field is set after the operation has overflowed.
The CR6 bits are set based on the *unbounded* result of the operation,
so we need
From: Daniel Henrique Barboza
The LoPAR spec provides no way for the guest kernel to report failure of
hotplug/hotunplug events. This wouldn't be bad if those operations were
granted to always succeed, but that's far for the reality.
What ends up happening is that, in the case of a failed hotunp
The following changes since commit b2ae1009d7cca2701e17eae55ae2d44fd22c942a:
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210307' into
staging (2021-03-09 13:50:35 +)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-2021031
On Wed, Mar 10, 2021 at 12:55:07PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 10/03/2021 01:00, BALATON Zoltan wrote:
> > On Tue, 9 Mar 2021, Alexey Kardashevskiy wrote:
> > > On 09/03/2021 16:29, David Gibson wrote:
> > > > > > > +struct ClientArchitectureSupportClass {
> > > > > > > + Inter
The PAPR platform which describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration between the firmware and the hypervisor.
Since the beginning, the runtime component of the firmware (RTAS) has
been implemented as a 2
This provides a RISC-V Board based on Andes's AE350 specification.
The following machine is implemented:
- 'andes_ae350'; PLIC, PLICSW, PLMT, 16550a UART, VirtIO MMIO, device-tree
Signed-off-by: Dylan Jhong
Signed-off-by: Ruinland ChuanTzu Tsai
---
default-configs/devices/riscv32-softmmu.mak |
Andes PLMT (Platform-Level Machine Timer) device provides an
timer functionality and issues timer interrupts.
The Andes PLMT is implemented based on Andes's PLMT specification.
Signed-off-by: Dylan Jhong
Signed-off-by: Ruinland ChuanTzu Tsai
---
hw/timer/Kconfig | 3 +
hw/timer/
Andes PLIC (Platform-Level Interrupt Controller) device provides an
interrupt controller functionality based on Andes's PLIC specification.
The Andes PLIC can handle either external interrupts (PLIC)
or interprocessor interrupts (PLICSW).
While Andes PLIC spec includes vector interrupt and interr
The following patches support Andes's Linux BSP booting on
qemu using 'andes_ae350' machine.
This patchset has implemented the basic components of AE350 platform,
which are
1. PLIC(external interrupts),
2. PLICSW(interprocessor interrupts),
3. PLMT(timer interrupts),
4. UART(16550a),
2021年3月9日(火) 22:10 BALATON Zoltan :
>
> On Tue, 9 Mar 2021, Akihiko Odaki wrote:
> > The first argument of the executable was used to get its path, but it is
> > not reliable because the executer can specify any arbitrary string. Use the
> > interfaces provided by QEMU and the platform to get those
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II,
a PowerPC board based on the Marvell MV64361 system controller and the
VIA VT8231 integrated south bridge/superio chips. It can run Linux,
AmigaOS and a wide range of MorphOS versions. Currently a firmware ROM
image is needed to
The Marvell Discovery II aka. MV64361 is a PowerPC system controller
chip that is used on the pegasos2 PPC board. This adds emulation of it
that models the device enough to boot guests on this board. The
mv643xx.h header with register definitions is taken from Linux 4.15.10
only fixing white space
Collect superio functionality and its controlling config registers
handling in an abstract VIA_SUPERIO class that is a subclass of
ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
abstract class.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 242
In VIA super south bridge the io ranges of superio components
(parallel and serial ports and FDC) can be controlled by superio
config registers to set their base address and enable/disable them.
This is not easy to implement in QEMU because ISA emulation is only
designed to set io base address once
The VT8231 south bridge is very similar to VT82C686B but there are
some differences in register addresses and functionality, e.g. the
VT8231 only has one serial port. This commit adds VT8231_SUPERIO
subclass based on the abstract VIA_SUPERIO class to emulate the
superio part of VT8231.
Signed-off-
From: Philippe Mathieu-Daudé
TYPE_VIA_PM calls apm_init() in via_pm_realize(), so
requires APM to be selected.
Reported-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: BALATON Zoltan
---
hw/isa/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/isa/Kconfig
Add emulation of VT8231 south bridge ISA part based on the similar
VT82C686B but implemented in a separate subclass that holds the
differences while reusing parts that can be shared.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 84 +++
Hello,
This is adding a new PPC board called pegasos2. More info on it can be
found at:
https://osdn.net/projects/qmiga/wiki/SubprojectPegasos2
Currently it needs a firmware ROM image that I cannot include due to
original copyright holder (bPlan) did not release it under a free
licence but I hav
To allow reusing ISA bridge emulation for vt8231_isa move the device
state of vt82c686b_isa emulation in an abstract via_isa class. This
change breaks migration back compatibility but this is not an issue
for Fuloong2E machine which is not versioned or migration supported.
Signed-off-by: BALATON Z
In the VFIO VM state change handler when stopping the VM, the _RUNNING
bit in device_state is cleared which makes the VFIO device stop, including
no longer generating interrupts. Then we can save the pending states of
all interrupts in the GIC VM state change handler (on ARM).
So we have to set th
This patch set includes two fixes and one optimization for VFIO migration
as blew:
Patch 1-2:
- Fix two ordering problems in migration.
Patch 3:
- Optimize the enabling process of the MSI-X vectors in migration.
History:
v3 -> v4
- Use msix_function_masked instead of msix_masked() in Patch 3.
In VFIO migration resume phase and some guest startups, there are
already unmasked vectors in the vector table when calling
vfio_msix_enable(). So in order to avoid inefficiently disabling
and enabling vectors repeatedly, let's allocate all needed vectors
first and then enable these unmasked vector
On ARM64 the VFIO SET_IRQS ioctl is dependent on the VM interrupt
setup, if the restoring of the VFIO PCI device config space is
before the VGIC, an error might occur in the kernel.
So we move the saving of the config space to the non-iterable
process, thus it will be called after the VGIC accordi
Hi
I am new to the Qemu project and was wondering if it is possible to emulate
the above processor with it's peripherals (Uart, DMA at least) on an X86.
Would it be possible for the following OS to run in a Qemu emulation (as it
does on the real processor) ?
https://www.st.com/en/development-tools
On Wed, 10 Mar 2021, Philippe Mathieu-Daudé wrote:
On 3/10/21 12:41 AM, BALATON Zoltan wrote:
On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:
ping for review?
This is included in my pegasos2 series as 6/8 replacing half of a
similar patch from my original version. Since I've reported it I d
On Wed, 10 Mar 2021, Philippe Mathieu-Daudé wrote:
On 3/9/21 9:28 PM, BALATON Zoltan wrote:
To allow reusing ISA bridge emulation for vt8231_isa move the device
state of vt82c686b_isa emulation in an abstract via_isa class. This
change breaks migration back compatibility but this is not an issue
On Wed, 10 Mar 2021, Philippe Mathieu-Daudé wrote:
On 3/9/21 9:13 PM, BALATON Zoltan wrote:
On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:
Extract the VT82C686 PCI UHCI function into a new unit so
it is only build when the VT82C686 south bridge is selected.
I'm not sure it's worth separati
Hi Eric,
On 2021/3/9 22:36, Auger Eric wrote:
Hi,
On 2/27/21 9:33 AM, Wang Xingang wrote:
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and pxb root bus. At present, All root bus will go
through iommu when iommu is configured,
On 2021/3/10 0:08, Peter Xu wrote:
> On Tue, Mar 09, 2021 at 02:57:53PM +, Dr. David Alan Gilbert wrote:
>> * Thomas Huth (th...@redhat.com) wrote:
>>> On 09/03/2021 15.05, Keqian Zhu wrote:
On 2021/3/9 21:48, Thomas Huth wrote:
> On 17/12/2020 02.49, Keqian Zhu wrote:
[..
On 10/03/2021 01:00, BALATON Zoltan wrote:
On Tue, 9 Mar 2021, Alexey Kardashevskiy wrote:
On 09/03/2021 16:29, David Gibson wrote:
+struct ClientArchitectureSupportClass {
+ InterfaceClass parent;
+ target_ulong (*cas)(CPUState *cs, target_ulong vec);
+ void (*quiesce)(void);
Is
Hi Alex,
On 2021/3/10 7:17, Alex Williamson wrote:
> On Thu, 4 Mar 2021 21:34:46 +0800
> Kunkun Jiang wrote:
>
>> The cpu_physical_memory_set_dirty_lebitmap() can quickly deal with
>> the dirty pages of memory by bitmap-traveling, regardless of whether
>> the bitmap is aligned correctly or not.
Hi,
On 2021/3/10 0:15, Peter Xu wrote:
On Tue, Mar 09, 2021 at 10:33:04PM +0800, Kunkun Jiang wrote:
Hi,
On 2021/3/9 5:12, Peter Xu wrote:
On Mon, Mar 08, 2021 at 06:34:58PM +0800, Kunkun Jiang wrote:
Hi,
On 2021/3/5 22:22, Peter Xu wrote:
Kunkun,
On Fri, Mar 05, 2021 at 03:50:34PM +0800,
Joelle van Dyne, le mar. 09 mars 2021 10:11:31 -0800, a ecrit:
> On Tue, Mar 9, 2021 at 6:09 AM Philippe Mathieu-Daudé
> wrote:
> > On 3/9/21 1:27 AM, Joelle van Dyne wrote:
> > > Replace Windows specific macro with a more generic feature detection
> > > macro. Allows slirp smb feature to be disa
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 22 ++
include/exec/exec-all.h | 41
target/arm/cpu.h| 5 +
target/arm/helper.c | 248
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f0a9e968c9c1..e34a6a6174fe 10064
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 6 ++
target/arm/helper.c | 75
2 files changed, 81 insertions(+)
diff --git a/target/arm/cpu.
ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE.
They provides TLBI maintenance instructions that extend to the Outer
Shareable domain and that apply to a range of input addresses.
Changes from v2 to v3:
o Change the functions in cputlb.c to do a full flush. This should
only be a
Since Linux 5.10, write zeros to a multipath device using
ioctl(fd, BLKZEROOUT, range) with cache none or directsync return -EBUSY
permanently.
Similar to handle_aiocb_write_zeroes_unmap, handle_aiocb_write_zeroes_block
allow -EBUSY and -EINVAL errors during ioctl(fd, BLKZEROOUT, range).
Referenc
On 3/9/21 9:13 PM, BALATON Zoltan wrote:
> On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:
>> Extract the VT82C686 PCI UHCI function into a new unit so
>> it is only build when the VT82C686 south bridge is selected.
>
> I'm not sure it's worth separating just this one device from the other
> sim
On 3/9/21 9:28 PM, BALATON Zoltan wrote:
> To allow reusing ISA bridge emulation for vt8231_isa move the device
> state of vt82c686b_isa emulation in an abstract via_isa class. This
> change breaks migration back compatibility but this is not an issue
> for Fuloong2E machine which is not versioned
On 3/9/21 9:28 PM, BALATON Zoltan wrote:
> Collect superio functionality and its controlling config registers
> handling in an abstract VIA_SUPERIO class that is a subclass of
> ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
> abstract class.
>
> Signed-off-by: BALATON Zoltan
On 3/10/21 12:41 AM, BALATON Zoltan wrote:
> On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:
>> ping for review?
>
> This is included in my pegasos2 series as 6/8 replacing half of a
> similar patch from my original version. Since I've reported it I don't
> think I should be also reviewing it bu
There is multiple places doing a device reset. Factor that
out in a common method which matches the DeviceReset prototype,
so we can also remove the reset code from the DeviceRealize()
handler. Explicit the device is set in "read array" mode on
reset.
Signed-off-by: Philippe Mathieu-Daudé
---
hw
There is only one call to pflash_setup_mappings(). Convert 'rom_mode'
to boolean and set it to true directly within pflash_setup_mappings().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block/pflash_c
Use the 'mode_read_array' event when we set the device in such
mode, and use the 'reset' event in DeviceReset handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash
The same pattern is used when setting the flash in READ_ARRAY mode:
- Set the state machine command to READ_ARRAY
- Reset the write_cycle counter
- Reset the memory region in ROMD
Refactor the current code by extracting this pattern.
It is used three times:
- When the timer expires and not in byp
The same pattern is used when setting the flash in READ_ARRAY mode:
- Set the state machine command to READ_ARRAY
- Reset the write_cycle counter
- Reset the memory region in ROMD
Refactor the current code by extracting this pattern.
It is used three times:
- On a read access (on invalid command)
Fill the CFI table in out of DeviceRealize() in a new function:
pflash_cfi02_fill_cfi_table().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 193 +---
1 file changed, 99 insertions(+), 94 deletions(-)
diff --git a/hw/block/pflash_cfi02.c
There is only one call to pflash_register_memory() with
rom_mode == false. As we want to modify pflash_register_memory()
in the next patch, open-code this trivial function in place for
the 'rom_mode == false' case.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 6 --
1 f
Fill the CFI table in out of DeviceRealize() in a new function:
pflash_cfi01_fill_cfi_table().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 140 +---
1 file changed, 73 insertions(+), 67 deletions(-)
diff --git a/hw/block/pflash_cfi01.c
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 36
hw/block/pflash_cfi02.c | 9 ++---
2 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/hw/block/pflash_cfi01.c b/hw/
I remembered this almost 2 years old series while reviewing
David Edmondson's patches... (which I plan to apply on top).
Basically we move things around to make the code easier to maintain.
Please review :)
Regards,
Phil.
Philippe Mathieu-Daudé (9):
hw/block/pflash_cfi: Fix code style for ch
On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:
ping for review?
This is included in my pegasos2 series as 6/8 replacing half of a similar
patch from my original version. Since I've reported it I don't think I
should be also reviewing it but it's quite trivial so may not need that
much rev
On Thu, 4 Mar 2021 21:34:46 +0800
Kunkun Jiang wrote:
> The cpu_physical_memory_set_dirty_lebitmap() can quickly deal with
> the dirty pages of memory by bitmap-traveling, regardless of whether
> the bitmap is aligned correctly or not.
>
> cpu_physical_memory_set_dirty_lebitmap() supports pages
On Tue, 9 Mar 2021 21:52:40 +0100
Laurent Vivier wrote:
> Le 22/02/2021 à 12:28, Greg Kurz a écrit :
> > This is just an oversight.
> >
> > Fixes: f518be3aa35b ("target/ppc: Remove "compat" property of server class
> > POWER CPUs")
> > Cc: gr...@kaod.org
> > Signed-off-by: Greg Kurz
> > ---
>
On Tue, 9 Mar 2021 15:18:56 +
Stefan Hajnoczi wrote:
> On Mon, Mar 08, 2021 at 01:31:40PM +0100, Greg Kurz wrote:
> > @@ -363,8 +367,30 @@ static int vhost_user_read(struct vhost_dev *dev,
> > VhostUserMsg *msg)
> > qemu_chr_be_update_read_handlers(chr->chr, ctxt);
> > qemu_chr_fe_
On Tue, 9 Mar 2021 20:48:40 +0100
Thomas Huth wrote:
> On 09/03/2021 18.41, Wainer dos Santos Moschetta wrote:
> > Hi,
> >
> > Any issue that prevent this of being queued?
>
> Maybe it's just not clear who should take the patch ... CC:-ing qemu-trivial
> and qemu-block now, since I think it co
On Tue, 9 Mar 2021 at 16:00, Wainer dos Santos Moschetta
wrote:
>
> For the sake of improve debuggability of tests which use the
> wait_for_console_pattern(), this changed the _console_interaction() so that
> the expected message is printed if the test fail.
>
> Signed-off-by: Wainer dos Santos Mo
On 2/10/21 1:12 PM, Bastian Koppelmann wrote:
> Hi,
>
> On Wed, Jan 27, 2021 at 11:42:52PM +0100, Philippe Mathieu-Daudé wrote:
>> Taking notes while reviewing commit 671a0a1265a
>> ("use MMUAccessType instead of int in mmu_translate").
>>
>> Philippe Mathieu-Daudé (3):
>> target/tricore: Replac
On Tue, Mar 09, 2021 at 10:12:24AM +0100, Philippe Mathieu-Daudé wrote:
> On 3/5/21 2:02 AM, David Gibson wrote:
> > On Thu, Mar 04, 2021 at 11:42:10PM +0100, Philippe Mathieu-Daudé wrote:
> >> On 3/4/21 9:16 PM, BALATON Zoltan wrote:
> >>> On Thu, 4 Mar 2021, Philippe Mathieu-Daudé wrote:
> O
ping for review?
On 3/2/21 9:05 AM, Philippe Mathieu-Daudé wrote:
> TYPE_VIA_PM calls apm_init() in via_pm_realize(), so
> requires APM to be selected.
>
> Reported-by: BALATON Zoltan
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/isa/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> di
ping?
On 2/14/21 8:45 PM, Philippe Mathieu-Daudé wrote:
> Add a very quick test that runs a busybox binary in bFLT format:
>
> $ avocado --show=app run -t linux_user tests/acceptance/load_bflt.py
> JOB ID : db94d5960ce564c50904d666a7e259148c27e88f
> JOB LOG: ~/avocado/job-results/jo
ping?
On 2/24/21 11:46 PM, Philippe Mathieu-Daudé wrote:
> Since v4:
> - Rebase on Claudio's work to avoid stub
>
> This series restrict the 'feature-words' property to the x86
> architecture (other archs don't have it), and to system-mode
> (user-mode doesn't use it).
>
> v4: https://www.mail-a
On 3/9/21 7:37 PM, Alex Bennée wrote:
>
> Peter Maydell writes:
>
>> On Mon, 8 Mar 2021 at 13:51, Alex Bennée wrote:
>>>
>>> The following changes since commit 91e92cad67caca3bc4b8e920ddb5c8ca64aac9e1:
>>>
>>> Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210305'
>>> into
Le 11/01/2021 à 16:20, Philippe Mathieu-Daudé a écrit :
> The 'running' argument from VMChangeStateHandler does not require
> other value than 0 / 1. Make it a plain boolean.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/sysemu/runstate.h | 10 --
> target/arm/kvm_arm.h
Le 11/01/2021 à 16:20, Philippe Mathieu-Daudé a écrit :
> runstate_check() returns a boolean. runstate_is_running()
> returns what runstate_check() returns, also a boolean.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/sysemu/runstate.h | 2 +-
> softmmu/runstate.c| 2 +-
> 2
ping, qemu-trivial maybe?
On 2/22/21 3:34 PM, Philippe Mathieu-Daudé wrote:
> Paolo, this series is fully reviewed, can it go via your
> misc tree?
>
> On 1/11/21 4:20 PM, Philippe Mathieu-Daudé wrote:
>> Trivial prototype change to clarify the use of the 'running'
>> argument of VMChangeStateHan
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