On Wed, Mar 03, 2021 at 02:53:39PM -0500, Vivek Goyal wrote:
> Option "-V" currently displays the fuse protocol version virtiofsd is
> using. For example, I see this.
>
> $ ./virtiofsd -V
> "using FUSE kernel interface version 7.33"
>
> People also want to know software version of virtiofsd so th
On 3/5/21 4:16 PM, Willian Rampazzo wrote:
> On Thu, Mar 4, 2021 at 5:44 PM Niek Linnenbank
> wrote:
>>
>> The image for Armbian 19.11.3 bionic has been removed from the armbian
>> server.
>> Without the image as input the test arm_orangepi_bionic_19_11 cannot run.
>>
>> This commit removes the
On 3/5/21 4:04 PM, Willian Rampazzo wrote:
> On Thu, Mar 4, 2021 at 5:45 PM Niek Linnenbank
> wrote:
>>
>> The linux kernel 4.20.7 binary for sunxi has been removed from
>> apt.armbian.com:
>>
>> $ ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado
>> --show=app,console run
Le 08/03/2021 à 08:30, Philippe Mathieu-Daudé a écrit :
> On 3/7/21 9:56 PM, Laurent Vivier wrote:
>> Add a system controller for the m68k-virt machine.
>> This controller allows the kernel to power off or reset the machine.
>>
>> Signed-off-by: Laurent Vivier
>> Reviewed-by: Richard Henderson
>>
Change documentation style and fix minor typos in tests/qtest/libqos/qgraph.h
to automatically generate sphinx documentation in docs/devel/qgraph.rst
The mechanism explanation that once was in qgraph.h is now moved to qgraph.rst
There is no functional change intended.
v2 -> v3:
- add proper docu
On 3/7/21 9:56 PM, Laurent Vivier wrote:
> Add a system controller for the m68k-virt machine.
> This controller allows the kernel to power off or reset the machine.
>
> Signed-off-by: Laurent Vivier
> Reviewed-by: Richard Henderson
> ---
> include/hw/misc/m68k_virt_ctrl.h | 22 +
> hw/misc
That's a very incomplete log that you've pasted here, I think there
should be an earlier error message that should indicate the real
problem. Please recompile without "-j8" and paste the full error log at
the end.
** Changed in: qemu
Status: New => Incomplete
--
You received this bug noti
On 07/03/2021 17.48, Laurent Vivier wrote:
Add a system controller for the m68k-virt machine.
This controller allows the kernel to power off or reset the machine.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
include/hw/misc/m68k_virt_ctrl.h | 22 +
hw/misc/m68k_virt
On 08/03/2021 02.55, Rebecca Cran wrote:
In commit cbcf09872a936ccefef6a34298046d3b9aefc148 on February 25th
CODING_STYLE.rst was moved into the developer manual. So, the "Use the QEMU
coding style" section of https://wiki.qemu.org/Contribute/SubmitAPatch
should probably be updated to link to:
Some BSD platforms do not have this header.
Signed-off-by: Joelle van Dyne
---
meson.build | 1 +
block.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 0e53876f69..ba0db9fa1f 100644
--- a/meson.build
+++ b/meson.build
@@ -1153,6 +1153,7
Replace Windows specific macro with a more generic feature detection
macro. Allows slirp smb feature to be disabled manually as well.
Signed-off-by: Joelle van Dyne
---
configure | 26 +++---
meson.build | 3 +++
net/slirp.c | 16
3 files changed, 34 inser
iOS hosts do not have these defined so we fallback to the
default behaviour.
Co-authored-by: Warner Losh
Signed-off-by: Joelle van Dyne
---
block/file-posix.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/block/file-posix.c b/block/file-posix.c
index d1
On Darwin (iOS), there are no system level APIs for directly accessing
host block devices. We detect this at configure time.
Signed-off-by: Joelle van Dyne
---
meson.build | 6 +-
qapi/block-core.json | 10 +++---
block/file-posix.c | 33 ++---
3 f
These patches disables code that cannot be compiled or run on iOS by adding
feature/header detection at configure time.
-j
Joelle van Dyne (4):
block: feature detection for host block support
block: check for sys/disk.h
block: detect DKIOCGETBLOCKCOUNT/SIZE before use
slirp: feature detec
On Wed, Feb 10, 2021 at 2:55 AM Roman Bolshakov wrote:
>
> There's a change in mprotect() behaviour [1] in the latest macOS on M1
> and it's not yet clear if it's going to be fixed by Apple. For now we
> can avoid unsupported mprotect() calls. QEMU and qtests work fine
> without it.
>
> 1. https:/
On 23/02/2021 15.46, Stefan Hajnoczi wrote:
Add a function to remove previously-added abrt handler functions.
Now that a symmetric pair of add/remove functions exists we can also
balance the SIGABRT handler installation. The signal handler was
installed each time qtest_add_abrt_handler() was cal
On Sun, Jan 24, 2021 at 11:34 PM wrote:
>
> From: Marc-André Lureau
>
> Remove the manual build.
>
> Signed-off-by: Marc-André Lureau
Tested-by: Joelle van Dyne
On Sun, Jan 24, 2021 at 11:34 PM wrote:
>
> From: Marc-André Lureau
>
> git cherry-diff:
>
> Commits on bacb71f1c3ed5f40e393afd8be81bedfba13a401 branch that is not on
> 8f43a99191afb47ca3f3c6972f6306209f367ece branch
> + 1021b0dc38d39f1dc95a296fe3e05a24a087cdc6 disable_dns option
> + 0f94ceec752
On 23/02/2021 15.46, Stefan Hajnoczi wrote:
Tests that manage multiple processes may wish to kill QEMU before
destroying the QTestState. Expose a function to do that.
The vhost-user-blk-test testcase will need this.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Wainer dos Santos Moschetta
---
On 22/02/2021 17.10, Stefan Hajnoczi wrote:
For some reason memfd never used share=on. vhost-user relies on
mmap(MAP_SHARED) so this seems like a problem, but the tests still run
without it.
Add share=on for consistency and to prevent future bugs in the test.
Signed-off-by: Stefan Hajnoczi
---
Currently, the default msix vectors for virtio-net-pci is 3 which is
obvious not suitable for multiqueue guest, so we depends on the user
or management tools to pass a correct vectors parameter. In fact, we
can simplifying this by calculating the number of vectors on realize.
Consider we have N qu
On Mon, Mar 8, 2021 at 11:48 AM Jason Wang wrote:
>
>
> On 2021/3/4 3:11 上午, Philippe Mathieu-Daudé wrote:
> > From: Bin Meng
> >
> > The minimum Ethernet frame length is 60 bytes. For short frames with
> > smaller length like ARP packets (only 42 bytes), on a real world NIC
> > it can choose eit
On 2021/3/5 2:26 下午, Jason Wang wrote:
Hi All:
Followed by commit 22dc8663d9 ("net: forbid the reentrant RX"), we
still need to fix the issues casued by loopback mode where the NIC
usually it via calling nc->info->receive() directly.
The fix is to introduce new network helper and check the
qu
On 210307 2242, Alexander Bulekov wrote:
> My basic workflow for that is:
> QEMU_FUZZ_TIMEOUT=0 QTEST_LOG=1 FUZZ_SERIALIZE_QTEST=1 \
> ./qemu-fuzz-target \
>--fuzz-target=generic-fuzz-virtio-vga ./crash-... > /tmp/out
^
On 2021/3/4 3:11 上午, Philippe Mathieu-Daudé wrote:
From: Bin Meng
The minimum Ethernet frame length is 60 bytes. For short frames with
smaller length like ARP packets (only 42 bytes), on a real world NIC
it can choose either padding its length to the minimum required 60
bytes, or sending it o
2021年3月8日(月) 4:57 Christian Schoenebeck :
>
> DisplaySurface pointer passed to gd_switch() can be NULL, so check this
> before trying to dereference it.
>
> Fixes: c821a58ee7 ("ui/console: Pass placeholder surface to display")
> Reported-by: Coverity (CID 1448421)
> Signed-off-by: Christian Schoene
I see the problem. You only hit the breakpoint in the first forked
process? I was able to sort-of work around this, using detach-on-fork.
gdb -q --args ./qemu-fuzz-i386
(gef) set follow-fork-mode child
(gef) set detach-on-fork off
(gef) b generic_fuzz.c:667
(gef) r --fuzz-target=generic-fuzz-virt
On 2021/3/5 5:38 下午, Philippe Mathieu-Daudé wrote:
On 3/5/21 7:26 AM, Jason Wang wrote:
Hi All:
Followed by commit 22dc8663d9 ("net: forbid the reentrant RX"), we
still need to fix the issues casued by loopback mode where the NIC
usually it via calling nc->info->receive() directly.
The fix i
Public bug reported:
Hi,
I got the latest version from git. I have pre-compiled the dependency
libraries. All good. configure creates the necessary files. When I build
I got the following error:
[1368/6454] Compiling C object
libcapstone.a.p/capstone_arch_AArch64_AArch64InstPrinter.c.o
ninja: b
In commit cbcf09872a936ccefef6a34298046d3b9aefc148 on February 25th
CODING_STYLE.rst was moved into the developer manual. So, the "Use the
QEMU coding style" section of
https://wiki.qemu.org/Contribute/SubmitAPatch should probably be updated
to link to:
https://gitlab.com/qemu-project/qemu/-/
On Thu, Mar 4, 2021 at 3:12 AM Philippe Mathieu-Daudé wrote:
>
> This is Bin's series but using iovec structure in 1st patch
> for zero copy.
>
> Bin's cover:
>
> The minimum Ethernet frame length is 60 bytes. For short frames with
> smaller length like ARP packets (only 42 bytes), on a real world
Not sure how this "Author email address is mangled" happened.
$ git format-patch -o patches/error-parsing-ipv6 -1
$ git send-email --to='qemu-devel@nongnu.org,Samuel Thibault <
samuel.thiba...@ens-lyon.org>,"Daniel P. Berrangé" ' \
--smtp-server=foo
patches/error-parsing-ipv6/0001-inet_parse-Clari
On 3/7/21 1:25 PM, Laurent Vivier wrote:
This is needed to boot MacOS ROM.
Pull the condition code and the program counter from the stack.
Operation:
(SP) -> CCR
SP + 2 -> SP
(SP) -> PC
SP + 4 -> SP
This operation is not privileged.
Reported-by: Mark Cave-Ayland
Tested-by
On 3/7/21 12:26 PM, Mark Cave-Ayland wrote:
According to the M68040UM Appendix D the requirement for data accesses to be
word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the
68020 onwards will allow unaligned data accesses but at the cost of being less
efficient.
Add a n
On 3/7/21 11:57 AM, Laurent Vivier wrote:
Le 07/03/2021 à 20:24, Philippe Mathieu-Daudé a écrit :
The spec says this register is only available on 64-bit targets.
Should we restrict this "#if TARGET_LONG_SIZE == 8"?
else log_mask(GUEST_ERROR)...
This seems overkill to me but that would respect
On 3/7/21 11:08 AM, Laurent Vivier wrote:
Both loads should happen (and thus exceptions recognized) before any other
state writeback.
Something like that?
ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
tcg_gen_addi_i32(QREG_SP, QREG_SP, 2);
tmp = gen_load(s, OS_LONG, QREG_
Patchew URL: https://patchew.org/QEMU/20210308002928.3385275-1-...@google.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210308002928.3385275-1-...@google.com
Subject: [PATCH] inet_parse: Clarify IPv6 comment and
Wrapping an IP address in square brackets does not necessarily
mean the address is an IPv6 address. The wrapping is just an aid
to parsing since IPv6 addresses have colons, but does not provide
semantic information.
E.g., [127.0.0.1] is a valid way to write 127.0.0.1.
Signed-off-by: Doug Evans
--
TYPE_PFLASH_CFI01 is a TYPE_SYS_BUS_DEVICE which registers its romd
MemoryRegion with sysbus_init_mmio(), so we can use the generic
sysbus_mmio_get_region() to get the region, no need for a specific
pflash_cfi01_get_memory() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 2 +
TYPE_PFLASH_CFI01 is a TYPE_SYS_BUS_DEVICE which registers its romd
MemoryRegion with sysbus_init_mmio(), so we can use the generic
sysbus_mmio_get_region() to get the region, no need for a specific
pflash_cfi01_get_memory() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc_sysfw.c |
TYPE_PFLASH_CFI01 is a TYPE_SYS_BUS_DEVICE which registers its romd
MemoryRegion with sysbus_init_mmio(), so we can use the generic
sysbus_mmio_get_region() to get the region, no need for a specific
pflash_cfi01_get_memory() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/xtensa/xtfpga.c |
Since we replaced all uses of pflash_cfi01_get_memory() with
sysbus_mmio_get_region(), we can now remove this unused helper.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/block/flash.h | 1 -
hw/block/pflash_cfi01.c | 5 -
2 files changed, 6 deletions(-)
diff --git a/include/hw/bloc
TYPE_PFLASH_CFI01 is a TYPE_SYS_BUS_DEVICE which registers its romd
MemoryRegion with sysbus_init_mmio(), so we can use the generic
sysbus_mmio_get_region() to get the region, no need for a specific
pflash_cfi01_get_memory() helper.
First replace the few pflash_cfi01_get_memory() uses by
sysbus_mm
This is needed to boot MacOS ROM.
Pull the condition code and the program counter from the stack.
Operation:
(SP) -> CCR
SP + 2 -> SP
(SP) -> PC
SP + 4 -> SP
This operation is not privileged.
Reported-by: Mark Cave-Ayland
Tested-by: Mark Cave-Ayland
Signed-off-by: Laurent Viv
Le 07/03/2021 à 21:26, Mark Cave-Ayland a écrit :
> According to the M68040UM Appendix D the requirement for data accesses to be
> word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the
> 68020 onwards will allow unaligned data accesses but at the cost of being less
> efficie
Le 07/03/2021 à 21:26, Mark Cave-Ayland a écrit :
> If a NuBus slot doesn't contain a card, the Quadra hardware generates a
> physical
> bus error if the CPU attempts to access the slot address space. Both Linux and
> MacOS use a separate bus error handler during NuBus accesses in order to
> dete
Add a system controller for the m68k-virt machine.
This controller allows the kernel to power off or reset the machine.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
include/hw/misc/m68k_virt_ctrl.h | 22 +
hw/misc/m68k_virt_ctrl.c | 152 +
A (generic) copy of the GLUE device we already have for q800 to use with
the m68k-virt machine.
The q800 one would disappear in the future as q800 uses actually the djMEMC
controller.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
include/h
The machine is based on Goldfish interfaces defined by Google
for Android simulator. It uses Goldfish-rtc (timer and RTC),
Goldfish-pic (PIC) and Goldfish-tty (for serial port and early tty).
The machine is created with 128 virtio-mmio bus, and they can
be used to use serial console, GPU, disk, NI
Implement the goldfish pic device as defined in
https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/intc/goldfish_pic.h | 33 +
The Quadra 800 machine is very limited to run linux, it manages
only 1 GiB of memory and only some specific interfaces.
The Virtual M68k Machine is based on Goldfish interfaces defined by Google
for Android simulator. It uses Goldfish-rtc (timer and RTC),
Goldfish-pic (PIC) and Goldfish-tty (for s
Implement the goldfish tty device as defined in
https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
and based on the kernel driver code:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/goldfish.c
Signed-off-by:
DisplaySurface pointer passed to gd_switch() can be NULL, so check this
before trying to dereference it.
Fixes: c821a58ee7 ("ui/console: Pass placeholder surface to display")
Reported-by: Coverity (CID 1448421)
Signed-off-by: Christian Schoenebeck
---
ui/gtk.c | 4 ++--
1 file changed, 2 inserti
According to the M68040UM Appendix D the requirement for data accesses to be
word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the
68020 onwards will allow unaligned data accesses but at the cost of being less
efficient.
Add a new M68K_FEATURE_NO_DALIGN feature to specify t
If a NuBus slot doesn't contain a card, the Quadra hardware generates a physical
bus error if the CPU attempts to access the slot address space. Both Linux and
MacOS use a separate bus error handler during NuBus accesses in order to detect
and recover when addressing empty slots.
According to the
Here are a couple of extra target/m68k patches taken from my attempts to try
and boot MacOS.
Signed-off-by: Mark Cave-Ayland
Mark Cave-Ayland (2):
target/m68k: don't set SSW ATC bit for physical bus errors
target/m68k: add M68K_FEATURE_NO_DALIGN feature
target/m68k/cpu.c | 1 +
tar
Le 07/03/2021 à 20:24, Philippe Mathieu-Daudé a écrit :
> On 3/7/21 5:48 PM, Laurent Vivier wrote:
>> Implement the goldfish tty device as defined in
>>
>> https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
>>
>> and based on the kernel driver code:
On 3/7/21 5:48 PM, Laurent Vivier wrote:
> Implement the goldfish tty device as defined in
>
> https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
>
> and based on the kernel driver code:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds
On 07/03/2021 18:22, Laurent Vivier wrote:
This is needed to boot MacOS ROM.
Pull the condition code and the program counter from the stack.
Operation:
(SP) -> CCR
SP + 2 -> SP
(SP) -> PC
SP + 4 - > SP
This operation is not privileged.
Reported-by: Mark Cave-Ayland
Sign
Le 07/03/2021 à 19:45, Richard Henderson a écrit :
> On 3/7/21 10:22 AM, Laurent Vivier wrote:
>> + ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
>> + gen_set_sr(s, ccr, true);
>> + tcg_temp_free(ccr);
>> + tcg_gen_addi_i32(QREG_SP, QREG_SP, 2);
>> + tmp = gen_load(s, OS_LONG,
On 3/7/21 10:22 AM, Laurent Vivier wrote:
+ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
+gen_set_sr(s, ccr, true);
+tcg_temp_free(ccr);
+tcg_gen_addi_i32(QREG_SP, QREG_SP, 2);
+tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
+tcg_gen_addi_i32(QREG_SP, QREG_SP, 4
On Sun, 7 Mar 2021, Laurent Vivier wrote:
This is needed to boot MacOS ROM.
Pull the condition code and the program counter from the stack.
Operation:
(SP) -> CCR
SP + 2 -> SP
(SP) -> PC
SP + 4 - > SP
Doesn't look like the commit message was fixed, there's still a space
there.
This is needed to boot MacOS ROM.
Pull the condition code and the program counter from the stack.
Operation:
(SP) -> CCR
SP + 2 -> SP
(SP) -> PC
SP + 4 - > SP
This operation is not privileged.
Reported-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
---
Notes:
v2: upd
Le 07/03/2021 à 19:07, Laurent Vivier a écrit :
> This is needed to boot MacOS ROM.
>
> Pull the condition code and the program counter from the stack.
>
> Operation:
>
> (SP) -> CCR
> SP + 2 -> SP
> (SP) -> PC
> (SP + 4) - > SP
This is in fact:
SP + 4 -> SP
>
> This oper
This adds processing of VIRTIO_VSOCK_F_SEQPACKET feature bit. Guest
negotiates it with vhost, thus both will know that SOCK_SEQPACKET
supported by peer.
Signed-off-by: Arseny Krasnov
---
hw/virtio/vhost-vsock.c | 16 +++-
include/standard-headers/linux/virtio_vs
This is needed to boot MacOS ROM.
Pull the condition code and the program counter from the stack.
Operation:
(SP) -> CCR
SP + 2 -> SP
(SP) -> PC
(SP + 4) - > SP
This operation is not privileged.
Reported-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
---
target/m68k/tran
Willian Rampazzo writes:
> On Fri, Mar 5, 2021 at 6:31 AM Alex Bennée wrote:
>>
>> Hi,
>>
>> Another week another testing/next roll. The series includes a couple
>> of my proposed documentation tweaks (including the re-org of the devel
>> manual). We also enable testing for the hexagon linux-u
Implement the goldfish tty device as defined in
https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
and based on the kernel driver code:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/goldfish.c
Signed-off-by:
The machine is based on Goldfish interfaces defined by Google
for Android simulator. It uses Goldfish-rtc (timer and RTC),
Goldfish-pic (PIC) and Goldfish-tty (for serial port and early tty).
The machine is created with 128 virtio-mmio bus, and they can
be used to use serial console, GPU, disk, NI
A (generic) copy of the GLUE device we already have for q800 to use with
the m68k-virt machine.
The q800 one would disappear in the future as q800 uses actually the djMEMC
controller.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
include/h
Implement the goldfish pic device as defined in
https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/intc/goldfish_pic.h | 33 +
Add a system controller for the m68k-virt machine.
This controller allows the kernel to power off or reset the machine.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
include/hw/misc/m68k_virt_ctrl.h | 22 +
hw/misc/m68k_virt_ctrl.c | 152 +
The Quadra 800 machine is very limited to run linux, it manages
only 1 GiB of memory and only some specific interfaces.
The Virtual M68k Machine is based on Goldfish interfaces defined by Google
for Android simulator. It uses Goldfish-rtc (timer and RTC),
Goldfish-pic (PIC) and Goldfish-tty (for s
The FreeBSD project has a number of enhancements to bsd-user. Add myself
as maintainer and Kyle Evans as a reviewer. Also add our github repo.
Signed-off-by: Warner Losh
Signed-off-by: Kyle Evans
Reviewed-by: Thomas Huth
---
MAINTAINERS | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
FreeBSD 12.1 has reached end of life. Use 12.2 instead so that FreeBSD's
project's packages will work. Update which timezone to pick. Work around a QEMU
bug that incorrectly raises an exception on a CRC32 instruction with the FPU
disabled. The qemu bug is described here:
https://www.mail-archive.
Hi David,
On Sun, Mar 7, 2021 at 3:18 PM David Hildenbrand wrote:
> On 05.03.21 16:51, Peter Xu wrote:
> > On Fri, Mar 05, 2021 at 04:44:36PM +0100, David Hildenbrand wrote:
> >> On 05.03.21 16:42, Peter Xu wrote:
> >>> On Fri, Mar 05, 2021 at 11:16:33AM +0100, David Hildenbrand wrote:
> +#
On 05.03.21 16:51, Peter Xu wrote:
On Fri, Mar 05, 2021 at 04:44:36PM +0100, David Hildenbrand wrote:
On 05.03.21 16:42, Peter Xu wrote:
On Fri, Mar 05, 2021 at 11:16:33AM +0100, David Hildenbrand wrote:
+#define OVERCOMMIT_MEMORY_PATH "/proc/sys/vm/overcommit_memory"
+static bool map_noreserv
The bottom 5 bits contain the number of bytes remaining in the FIFO which is
trivial to implement with Fifo8 (the remaining bits are unimplemented and left
as 0 for now).
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.
When the MacOS toolbox ROM transfers data from a target device to an unaligned
memory address, the first/last byte of a 16-bit transfer needs to be handled
separately. This means that the first byte is preloaded into the FIFO before
the transfer, or the last byte remains in the FIFO after the trans
At this point it is now possible to properly implement the FIFO flush command
without causing guest errors.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.6369-32-mark.cave-ayl...@ilande.co.uk>
---
hw/scsi/esp.c | 2 ++
1 file changed, 2 insertions(+)
d
Rename ESP_CMDBUF_SZ to ESP_CMDFIFO_SZ and cmdbuf_cdb_offset to
cmdfifo_cdb_offset
to indicate that the command buffer type has changed from an array to a Fifo8.
This also enables us to remove the ESPState field cmdlen since the command
length
is now simply the number of elements used in cmdfifo
The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to
and from the target. Since the SCSI bus is 16-bits wide, use the memory API
to split a 4 byte access into 2 x 2 byte accesses.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Viv
This matches the description in the datasheet and is required as support for
non-DMA transfers is added.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.6369-36-mark.cave-ayl...@ilande.co.uk>
---
hw/scsi/esp.c | 6 ++
1 file changed, 6 insertions(+)
Rename TI_BUFSZ to ESP_FIFO_SZ since this constant is really describing the size
of the FIFO and is not directly related to the TI size.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.6369-39-mark.cave-ayl...@ilande.co
Currently the target selection for PDMA is done after the SCSI command has been
delivered which is not correct. Perform target selection as part of the initial
get_cmd() call when the command is submitted: if no target is present, don't
raise DRQ.
If the target is present then switch to the comman
The cmdbuf is really just a copy of FIFO data (including extra message phase
bytes) so its pdma_origin is effectively TI. Fortunately we already know when
we are receiving a SCSI command since do_cmd == 1 which enables us to
distinguish between the two cases in esp_pdma_read()/esp_pdma_write().
Si
The MacOS toolbox ROM uses non-DMA TI commands to handle the first/last byte
of an unaligned 16-bit transfer to memory.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.6369-42-mark.cave-ayl...@ilande.co.uk>
---
hw/scsi/esp.c | 133
Some guests use a mixture of DMA and non-DMA transfers in combination with the
SATN and stop command to transfer message out phase and command phase bytes to
the target. Prepare for the next commit by adding a maxlen parameter to
get_cmd() to allow partial transfers.
Signed-off-by: Mark Cave-Aylan
Real hardware simply counts down using the in-built TC to determine when the
the PDMA request is complete. Use the TC to determine the PDMA transfer length
which then enables us to remove the redundant pdma_len variable.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewe
Here the updates to async_len and ti_size are moved into the corresponding
esp_pdma_read()/esp_pdma_write() function to eliminate the reference to
pdma_cur in do_dma_pdma_cb().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.6369-23-mark.cave-ayl...@ilande
The SCSI bus should remain in the message out phase after the SATN and stop
command rather than transitioning to the command phase. A new ESPState variable
cmdbuf_cdb_offset is added which stores the offset of the CDB from the start
of cmdbuf when accumulating extended message out phase data.
Curr
The MacOS toolbox ROM issues a command to the ESP controller as part of its
"FAST" SCSI routines and then proceeds to read the incoming data soon after
receiving the command completion interrupt.
Unfortunately due to SCSI block transfers being asynchronous the incoming data
may not yet be present
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.6369-16-mark.cave-ayl...@ilande.co.uk>
---
hw/scsi/esp.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 07d57cb791..0fafc
Now that PDMA SCSI commands are accumulated in cmdbuf in the same way as normal
commands, the existing logic for locating the start of the SCSI command in
cmdbuf via cmdlen can be used. This enables the PDMA-specific pdma_start and
also get_pdma_buf() to be removed.
Signed-off-by: Mark Cave-Ayland
Commit ea84a44250 "scsi: esp: Defer command completion until previous interrupts
have been handled" provided a mechanism to delay the command completion
interrupt
until ESP_RINTR is read after the command has completed.
With the previous fixes for latching the ESP_RINTR bits and deferring the
se
Currently the ESP_RINTR register is set to a specific value as required within
the ESP state machine. In order to implement the upcoming deferred interrupt
functionality it is necessary to set individual bits within ESP_RINTR so that
a deferred interrupt will not overwrite the value of any other in
The transfer direction is currently determined by checking the sign of ti_size
but as this series progresses ti_size can be zero at the end of the transfer.
Use the SCSI phase to determine the transfer direction as used in other SCSI
controller implementations.
Signed-off-by: Mark Cave-Ayland
Re
ESP SCSI commands are already accumulated in cmdbuf and so there is no need to
keep a separate pdma_buf buffer. Accumulate SCSI commands for PDMA transfers in
cmdbuf instead of pdma_buf so update cmdlen accordingly and change pdma_origin
for PDMA transfers to CMD which allows the PDMA origin to be
This eliminates the last user of the PDMA-specific pdma_cur variable which can
now be removed.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.6369-24-mark.cave-ayl...@ilande.co.uk>
---
hw/scsi/esp.c | 23 +
Move the trace event to the end of the function so that it correctly reports
the returned value if it doesn't come directly from the rregs array.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20210304221103.6369-7-mark.cave-ayl...@i
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