The device-type names for the pro100 network cards, are i8255.. We were
matching "eepro", which catches the PCI PIO/MMIO regions for those
devices, however misses the actual PCI device, which we use to map the
BARs, before fuzzing. Fix that
Signed-off-by: Alexander Bulekov
---
tests/qtest/fuzz/g
Introduces structure AcpiBuildOem to hold the value of OEM fields and
uses dedicated macros to initialize/set the values.
Unnecessary dynamically allocated OEM fields are re-factored to static
allocation.
Signed-off-by: Marian Postevca
---
hw/acpi/hmat.h | 2 +-
hw/i386/acpi-c
The code that sets/gets oem fields is duplicated in both PC and MICROVM
variants. This commit moves it to X86MachineState so that all x86
variants can use it and duplication is removed.
Signed-off-by: Marian Postevca
---
include/hw/i386/microvm.h | 4 ---
include/hw/i386/pc.h | 4 ---
inc
This patch series consolidates ACPI OEM fields handling
by:
- Moving common code in PC and MICROVM to X86.
- Changes unnecessary dynamic memory allocation to static allocation
- Uses dedicated structure to keep values of fields instead of two
separate strings
- Adds helper macros to initialize th
On Sat, 20 Feb 2021, Philippe Mathieu-Daudé wrote:
Cc'ing Paolo (Memory API maintainer).
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
In VIA super south bridge the io ranges of superio components
(parallel and serial ports and FDC) can be controlled by superio
config registers to set their base add
On 2/15/21 3:51 AM, Peter Maydell wrote:
> The AN524 has a different SYSCLK frequency from the AN505 and AN521;
> make the SYSCLK frequency a field in the MPS2TZMachineClass rather
> than a compile-time constant so we can support the AN524.
>
> Signed-off-by: Peter Maydell
> Reviewed-by: Philippe
** Description changed:
Steps to reproduce:
- 1. Install QEMU using homebrew on Mac OS X (I used Big Sur)
+ 1. Install QEMU using homebrew on Mac OS X (I tried on Catalina and Big Sur)
2. Spin up a guest VM (say) Cent OS 8 using user mode networking.
3. Install podman inside the guest
4
On Sat, 20 Feb 2021, Philippe Mathieu-Daudé wrote:
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
Similar to the SMBus io registers there is a power management io range
that is set via similar base address reg and enable bit. Some handling
of this was already there but with several problems: using the
On Sat, 20 Feb 2021, Philippe Mathieu-Daudé wrote:
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
These functions are memory region callbacks so we have to check
against relative address not the mapped address. Also reduce
indentation by returning early and log unimplemented accesses.
Additionally we
For some vector operations, "1D" is not a valid type, and there
are separate instructions for the 64-bit scalar operation.
Buglink: https://bugs.launchpad.net/qemu/+bug/1916112
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c
I guess it has been a while since I've run aa32 risu on aa64 host.
The launchpad bug is something that should have been seen from the
beginning, but the similar aa64 operations are expanded as integer
code, not vector code. The aa32 neon code has only recently been
converted to use gvecs.
The cm
Fix a typo in the encodeing of the cmle (zero) instruction.
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/t
Thomas Huth writes:
> On 19/02/2021 13.00, Philippe Mathieu-Daudé wrote:
>> On 2/19/21 12:09 PM, Thomas Huth wrote:
>>> We're building a lot of containers in the gitlab-CI that we never use.
>>> This takes away network bandwidth and CPU time from other jobs for no
>>> use, so let's remove them
Thomas Huth writes:
> We're building a lot of containers in the gitlab-CI that we never use.
> This takes away network bandwidth and CPU time from other jobs for no
> use, so let's remove them for now. The individual containers could be
> re-added later when we really need them.
They are used
On 2/20/21 12:20 PM, Philippe Mathieu-Daudé wrote:
> As the 'rw' argument is unused, remove it.
>
> Reported-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/tlb_helper.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henders
As the 'rw' argument is unused, remove it.
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tlb_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 082c17928d3..8b85ef735
On 2/8/21 12:23 AM, Philippe Mathieu-Daudé wrote:
> Commit 83be6b54123 ("Fix MSA instructions LD. on big endian
> host") introduced use of typedef/prototypes declared in "tcg/tcg.h"
> without including it. This was not a problem because "tcg/tcg.h" is
> pulled in by "exec/cpu_ldst.h". To be able to
On 2/15/21 2:45 PM, Fredrik Noring wrote:
> On Mon, Feb 15, 2021 at 11:59:57AM +, Daniel P. Berrangé wrote:
>> On Sun, Feb 14, 2021 at 06:59:02PM +0100, Philippe Mathieu-Daudé wrote:
>>> Add a Docker image providing cross toolchain for the MIPS R5900 CPU
>>> (used on the Sony PS2).
>>>
>>> This
Cc'ing Paolo (Memory API maintainer).
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
> In VIA super south bridge the io ranges of superio components
> (parallel and serial ports and FDC) can be controlled by superio
> config registers to set their base address and enable/disable them.
> This is not easy
On Fri, 19 Feb 2021 at 22:00, Gerd Hoffmann wrote:
>
> The following changes since commit c79f01c9450bcf90c08a77f13fbf67bdba59a316:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210218' in=
> to staging (2021-02-18 16:33:36 +)
>
> are available in the Git repository at
The sigill is for the code generated for the aa32 instruction
0xf7ca0820: f3780407 vshl.u64 d16, d7, d8
f7ca0820
ld_vec v64,e8,tmp9,env,$0xf68pref=0x
ld_vec v64,e8,tmp10,env,$0x1060 pref=0x
n
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
> These functions are memory region callbacks so we have to check
> against relative address not the mapped address. Also reduce
> indentation by returning early and log unimplemented accesses.
> Additionally we remove separate index value from SuperIOConfig
** Description changed:
Steps to reproduce:
1. Install QEMU using homebrew on Mac OS X (I used Big Sur)
- 2. Spin up a guest VM (say) Cent OS8 using user mode networking.
+ 2. Spin up a guest VM (say) Cent OS 8 using user mode networking.
3. Install podman inside the guest
4. Run podman
** Description changed:
Steps to reproduce:
1. Install QEMU using homebrew on Mac OS X (I used Big Sur)
2. Spin up a guest VM (say) Cent OS8 using user mode networking.
3. Install podman inside the guest
4. Run podman pull alpine
The result is:
[root@localhost ~]# podman pul
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
> Similar to the SMBus io registers there is a power management io range
> that is set via similar base address reg and enable bit. Some handling
> of this was already there but with several problems: using the wrong
> registers and bits, wrong size range, n
Public bug reported:
Steps to reproduce:
1. Install QEMU using homebrew on Mac OS X (I used Big Sur)
2. Spin up a guest VM (say) Cent OS8 using user mode networking.
3. Install podman inside the guest
4. Run podman pull alpine
The result is:
[root@localhost ~]# podman pull alpine
Resolved "alpi
Be aware that most of the regression test failures are caused by lack of
ptrace() support.
The wine traces above show one of these cases. I will provide traces of
an actual relevant failure.
However the failure to restart the correct thread is in some way related
to the use of iret in set_full_cp
Public bug reported:
Basically e.g, if I try with below command on macOS:
qemu-system-x86_64 \
-m 4G \
-vga virtio \
-display default,show-cursor=on \
-usb \
-device usb-tablet \
-mac
On 2/19/21 12:18 PM, Peter Collingbourne wrote:
> Section D6.7 of the ARM ARM states:
>
> For the purpose of determining Tag Check Fault handling, unprivileged
> load and store instructions are treated as if executed at EL0 when
> executed at either:
> - EL1, when the Effective value of PSTATE.UAO
This has nothing to do with the Jetson Nano, which
uses a very standard Arm cortex-a57.
I can reproduce this on any arm64 host.
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is s
On 2/19/21 4:44 AM, Stefan Sandström wrote:
> From: Stefan Sandstrom
>
> Add and fix deallocation of temporary TCG registers in CRIS code
> generation.
>
> Tested-by: Edgar E. Iglesias
> Reviewed-by: Edgar E. Iglesias
> Change-Id: I17fce5d95bdc4418337ba885d53ba97afb1bafcc
> Signed-off-by: Stef
On Freitag, 19. Februar 2021 20:01:12 CET Vivek Goyal wrote:
> On Fri, Feb 19, 2021 at 06:33:46PM +0100, Christian Schoenebeck wrote:
> > On Freitag, 19. Februar 2021 17:08:48 CET Vivek Goyal wrote:
> > > On Fri, Sep 25, 2020 at 10:06:41AM +0200, Christian Schoenebeck wrote:
> > > > On Freitag, 25.
From: Bin Meng
Some peripherals require 64-bit PCI address, so let's map the high
mmio space for PCIe.
For RV32, the address is hardcoded to below 4 GiB from the highest
accessible physical address. For RV64, the base address depends on
top of RAM and is aligned to its size which is using 16 GiB
From: Bin Meng
RV32 supports 34-bit physical address hence the maximum RAM size
should be limited. Limit the RAM size to 10 GiB, which leaves
some room for PCIe high mmio space.
For 32-bit host, this is not needed as machine->ram_size cannot
represent a RAM size that big. Use a #if size test to
From: Bin Meng
`link_up` is never used in gpex_pcie_init(). Drop it.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
hw/riscv/virt.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cfd
From: Bin Meng
This series does the following clean-ups:
- Drop 'struct MemmapEntry'
- virt: Drop the 'link_up' parameter of gpex_pcie_init()
It also adds the following small enhancement to 'virt' machine:
- Limit RAM size in a 32-bit system
- Map high mmio for PCIe
Changes in v3:
- Fix the typ
From: Bin Meng
There is already a MemMapEntry type defined in hwaddr.h. Let's drop
the RISC-V defined `struct MemmapEntry` and use the existing one.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
(no changes since v1)
hw/riscv/microchip_pfsoc.
Am 20.02.21 um 14:31 schrieb Stefan Weil:
TCG works and I get a Linux boot prompt in the guest Raspbian when
vector instructions for TCG are disabled, so obviously the undefined
instruction is simply unsupported for Jetson Nano and Xavier.
Patch used to disable it:
diff --git a/tcg/aarch64/tcg
Patchew URL:
https://patchew.org/QEMU/161382791482.29356.5013965818751172438.mal...@soybean.canonical.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 161382791482.29356.5013965818751172438.mal...@soybean.canonical.
TCG works and I get a Linux boot prompt in the guest Raspbian when
vector instructions for TCG are disabled, so obviously the undefined
instruction is simply unsupported for Jetson Nano and Xavier.
Patch used to disable it:
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 5e
I can confirm the issue (tested with Jetson Nano and Xavier running
Ubuntu bionic).
Linux starts booting, shows "Welcome to Raspbian GNU/Linux 10 (buster)!"
after 33 s on Nano, but QEMU crashes after showing "Mounted Kernel Debug
File System" about 77 s after start.
Debugging is difficult because
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20201011195001.3219730-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/scsi/megasas.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/scsi/megasas.c b
From: Gan Qixin
The category of the virtio-pmem device is not set, put it into the 'storage'
category.
Signed-off-by: Gan Qixin
Reviewed-by: Pankaj Gupta
Message-Id: <20201130083630.2520597-3-ganqi...@huawei.com>
Signed-off-by: Laurent Vivier
---
hw/virtio/virtio-pmem.c | 1 +
1 file changed
From: Philippe Mathieu-Daudé
Change generated automatically using the Coccinelle
patch included in commit bf853881690 ("qdev: use
device_class_set_parent_realize/unrealize/reset()")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210201080348.438095-1-f4...@
From: Christian Schoenebeck
I already used this github URL for PRs before and will continue to use it in
foreseeable future.
Signed-off-by: Christian Schoenebeck
Reviewed-by: Greg Kurz
Message-Id:
Signed-off-by: Laurent Vivier
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --gi
From: Gan Qixin
The category of the nvdimm device is not set, put it into the 'storage'
category.
Signed-off-by: Gan Qixin
Reviewed-by: Pankaj Gupta
Reviewed-by: Thomas Huth
Message-Id: <20201130083630.2520597-5-ganqi...@huawei.com>
Signed-off-by: Laurent Vivier
---
hw/mem/nvdimm.c | 1 +
1
From: Ryan Finnie
Several SPDX headers contain "SPDX-License-Identifer" (note the
missing "i" before "er"); fix these typos.
Signed-off-by: Ryan Finnie
Cc: qemu-triv...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210201200147.211914-1-r...@finnie.org>
Signed-off-by: Laurent V
From: Gan Qixin
The category of the u2f-passthru device is not set, put it into the 'misc'
category.
Signed-off-by: Gan Qixin
Acked-by: Gerd Hoffmann
Message-Id: <20201130083630.2520597-10-ganqi...@huawei.com>
Signed-off-by: Laurent Vivier
---
hw/usb/u2f-passthru.c | 1 +
1 file changed, 1 i
From: Thomas Huth
This was only required for the pc-1.0 and earlier machine types.
Now that these have been removed, we can also drop the corresponding
code from the FDC device.
Signed-off-by: Thomas Huth
Reviewed-by: John Snow
Acked-by: John Snow
Message-Id: <20210203171832.483176-3-th...@re
From: Gan Qixin
Some tpm devices have no category, put them into the correct category.
Signed-off-by: Gan Qixin
Reviewed-by: Stefan Berger
Message-Id: <20201130083630.2520597-8-ganqi...@huawei.com>
Signed-off-by: Laurent Vivier
---
hw/tpm/tpm_tis_isa.c| 1 +
hw/tpm/tpm_tis_sysbus.c | 1 +
From: Philippe Mathieu-Daudé
'drivers_blacklisted' is never accessed, remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Paul Durrant
Message-Id: <20210202155644.998812-1-phi...@redhat.com>
Signed-off-by: Laurent Vivier
---
hw/i386/xen/xen_platform.c | 13 ++---
1 file cha
From: Philippe Mathieu-Daudé
Update the F: line after the Meson refactor.
Fixes: 1bb4cb1c338..73362fc0b0c ("default-configs: ...")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20201117114656.1222555-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
MAINTA
From: Gan Qixin
The category of the vmmouse device is not set, put it into the 'input'
category.
Signed-off-by: Gan Qixin
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20201130083630.2520597-4-ganqi...@huawei.com>
Signed-off-by: Laurent Vivier
---
hw/i386/vmmouse
branch-for-6.0-pull-request
for you to fetch changes up to 1cb428356beec30cd5067add76e51e01d0f6f680:
MAINTAINERS: Fix default-configs/ entries (2021-02-20 12:36:19 +0100)
Pull request trivial patche
** Changed in: qemu
Status: New => Confirmed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1916112
Title:
Illegal instruction crash of QEMU on Jetson Nano
Status in QEMU:
Confirmed
Bug d
Peter Maydell writes:
> Does anybody use the ozlabs patchwork install for QEMU patches,
> either occasionally or on a regular basis ?
> http://patchwork.ozlabs.org/project/qemu-devel/list/
> The admins for that system are trying to identify which of
> the various projects are really using their
ui/console used to accept NULL as graphic console surface, but its
semantics was inconsistent among displays:
- cocoa and gtk-egl perform NULL dereference.
- egl-headless, spice and spice-egl do nothing.
- gtk releases underlying resources.
- sdl2-2d and sdl2-gl destroys the window.
- vnc shows a m
On Fri, 19 Feb 2021 at 16:10, Bin Meng wrote:
>
> From: Bin Meng
>
> RV32 supports 34-bit physical address hence the maximum RAM size
> should be limitted. Limit the RAM size to 10 GiB, which leaves
> some room for PCIe high mmio space.
>
> For 32-bit host, this is not needed as machine->ram_size
On Sat, Feb 20, 2021 at 12:29 AM Peter Maydell wrote:
>
> Does anybody use the ozlabs patchwork install for QEMU patches,
> either occasionally or on a regular basis ?
> http://patchwork.ozlabs.org/project/qemu-devel/list/
> The admins for that system are trying to identify which of
> the various
On Sat, Feb 20, 2021 at 9:42 AM Stefan Weil wrote:
>
> Am 20.02.21 um 00:07 schrieb Philippe Mathieu-Daudé:
>
> > Cc'ing Stefan / Yonggang / Paolo.
> >
> > On 2/20/21 12:03 AM, Peter Maydell wrote:
> >> On Fri, 19 Feb 2021 at 22:54, nerus wrote:
> >>> Good evening, I turn to you because I have a
On Fri, Feb 19, 2021 at 05:51:02PM +0100, Thomas Huth wrote:
> On 19/02/2021 17.26, Peter Maydell wrote:
> > Does anybody use the ozlabs patchwork install for QEMU patches,
> > either occasionally or on a regular basis ?
> > http://patchwork.ozlabs.org/project/qemu-devel/list/
> > The admins for th
From: Bin Meng
At present the sd_erase() does not erase the requested range of card
data to 0xFFs. Let's make the erase operation actually happen.
Signed-off-by: Bin Meng
---
Changes in v3:
- fix the skip erase logic for SDSC cards
Changes in v2:
- honor the write protection bits for SDSC ca
Am 20.02.21 um 00:07 schrieb Philippe Mathieu-Daudé:
Cc'ing Stefan / Yonggang / Paolo.
On 2/20/21 12:03 AM, Peter Maydell wrote:
On Fri, 19 Feb 2021 at 22:54, nerus wrote:
Good evening, I turn to you because I have a problem that does not appear in
the official documentation, nor in the dif
> Am 19.02.2021 um 23:47 schrieb Peter Xu :
>
> On Fri, Feb 19, 2021 at 10:20:42PM +0100, David Hildenbrand wrote:
>>> A shiver just went down my spine. Please don‘t just for the sake of
>>> creating a snapshot.
>>>
>>> (Just imagine you don‘t have a shared zeropage...)
>>
>> ... and I just r
64 matches
Mail list logo
