John Snow writes:
> On 2/17/21 11:35 AM, Markus Armbruster wrote:
>> John Snow writes:
>>
>>> On 2/17/21 4:39 AM, Markus Armbruster wrote:
John Snow writes:
> Signed-off-by: John Snow
> ---
>scripts/qapi/introspect.py | 18 ++
>1 file changed,
Hello Jason,
+-- On Thu, 18 Feb 2021, Jason Wang wrote --+
| On 2021/2/10 下午10:52, P J P wrote:
| > From: Prasad J Pandit
| >
| > While processing transmit (tx) descriptors in process_tx_desc()
| > various descriptor fields are not checked properly. This may lead
| > to infinite loop like issue
On 18/02/2021 04.40, Halil Pasic wrote:
Commit 2c44220d05 ("meson: convert hw/arch*"), which migrated the old
Makefile.objs to meson.build accidentally excluded virtio-ccw-9p.c and
thus the virtio-9p-ccw device from the build (and potentially also
included the file virtio-ccw-blk.c twice in the
On 17/02/2021 21.20, Richard Henderson wrote:
We're currently only testing TCI with a 64-bit host -- also test
with a 32-bit host. Enable a selection of softmmu and user-only
targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-
On 17/02/2021 21.20, Richard Henderson wrote:
The longest test at the moment seems to be a (slower)
aarch64 host, for which test-mmap takes 64 seconds.
Signed-off-by: Richard Henderson
---
configure | 3 +++
tests/tcg/Makefile.target | 6 --
2 files changed, 7 insertions
From: Isaku Yamahata
Reviewed-by: Igor Mammedov
Signed-off-by: Isaku Yamahata
---
tests/qtest/bios-tables-test.c | 24
1 file changed, 24 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 93d037c29d..e020c83d2a 100644
---
On 2021/2/11 上午1:45, Laurent Vivier wrote:
Commit a1190ab628 has added a "allow_unplug_during_migration = true" at
the end of the main "if" block, so it is not needed to set it anymore
in the previous checking.
Remove it, to have only sub-ifs that check for needed conditions and exit
if one fa
From: Sean Christopherson
Omit HPET AML if the HPET is disabled, QEMU is not emulating it and the
guest may get confused by seeing HPET in the ACPI tables without a
"physical" device present.
The change of DSDT when -no-hpet is as follows.
@@ -141,47 +141,6 @@ DefinitionBlock ("", "DSDT", 1, "B
On 2021/2/11 上午1:45, Laurent Vivier wrote:
In failover_add_primary(), we search the id of the failover device by
scanning the list of the devices in the opts list to find a device with
a failover_pair_id equals to the id of the virtio-net device.
If the failover_pair_id is not found, QEMU igno
From: Isaku Yamahata
Declare PNP0C01 device to reserve MMCONFIG region to conform to the
spec better and play nice with guest BIOSes/OSes.
According to PCI Firmware Specification[0], MMCONFIG region must be
reserved by declaring a motherboard resource. It's optional to reserve
the region in memo
From: Isaku Yamahata
>From table 5.9 SMI_CMD of ACPI spec
> This field is reserved and must be zero on system
> that does not support System Management mode.
When smm is not enabled, set it to zero to comform to the spec.
When -machine smm=off is passed, the change to FACP is as follows.
@@ -1,
On 2021/2/11 上午1:45, Laurent Vivier wrote:
failover_add_primary() calls qdev_device_add() and doesn't unref
the device. Because of that, when the device is unplugged a reference
is remaining and prevents the cleanup of the object.
This prevents to be able to plugin back the failover primary de
From: Isaku Yamahata
Reviewed-by: Igor Mammedov
Signed-off-by: Isaku Yamahata
---
tests/qtest/bios-tables-test.c | 76 ++
1 file changed, 76 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 77053975aa..93d037c29d
From: Isaku Yamahata
The following patch will introduce incompatible behavior of SMM.
Introduce a property to keep the old behavior for compatibility.
To enable smm compat, use "-global ICH9-LPC.smm-compat=on" or
"-global PIIX4_PM.smm-compat=on"
Suggested-by: Igor Mammedov
Signed-off-by: Isaku
From: Isaku Yamahata
If SMM is not supported, ACPI fixed hardware doesn't support
legacy-mode. ACPI-only platform. Where SCI_EN in PM1_CNT register is
always set.
The bit tells OS legacy mode(SCI_EN cleared) or ACPI mode(SCI_EN set).
With the next patch (setting fadt.smi_cmd = 0 when smm isn't e
From: Isaku Yamahata
The following tests will modify acpi tables.
prepare qtests to allow acpi table change.
add new tables for new tests.
- tests/data/acpi/pc/DSDT.nohpet
- tests/data/acpi/pc/FACP.nosmm
- tests/data/acpi/q35/DSDT.nohpet
- tests/data/acpi/q35/FACP.nosmm
Acked-by: Igor Mammedov
On 2021/2/10 下午10:52, P J P wrote:
From: Prasad J Pandit
While processing transmit (tx) descriptors in process_tx_desc()
various descriptor fields are not checked properly. This may lead
to infinite loop like issue. Add checks to avoid them.
Reported-by: Alexander Bulekov
Reported-by: Cheol
From: Isaku Yamahata
update golden master acpi tables and empty
bios-tables-test-allowed-diff.h.
Signed-off-by: Isaku Yamahata
---
tests/data/acpi/pc/DSDT.nohpet | Bin 0 -> 4923 bytes
tests/data/acpi/pc/FACP.nosmm | Bin 0 -> 116 bytes
tests/data/acpi/q35/DSDT
From: Isaku Yamahata
Newly created acpi data files(tests/data/acpi/) cause false positive
warning.
If file names are acpi expected file, don't emit warning.
Fixes: e625ba2a41 ("checkpatch: fix acpi check with multiple file name")
Signed-off-by: Isaku Yamahata
---
scripts/checkpatch.pl | 4 +++-
From: Isaku Yamahata
Miscellaneous bug fixes related to ACPI to play nice with guest BIOSes/OSes
by conforming to ACPI spec better.
Changes from v4:
- rebased to 1af5629673
- move compat property from 3/10 to 4/10
- use the end of the address for rage maximum of memory region
- code simplificati
Commit 2c44220d05 ("meson: convert hw/arch*"), which migrated the old
Makefile.objs to meson.build accidentally excluded virtio-ccw-9p.c and
thus the virtio-9p-ccw device from the build (and potentially also
included the file virtio-ccw-blk.c twice in the source set). And since
CONFIG_VIRTFS can'
On 2021/2/10 下午4:38, Michael S. Tsirkin wrote:
On Wed, Feb 10, 2021 at 02:19:59PM +0800, Jason Wang wrote:
On 2021/2/9 下午11:04, Michael S. Tsirkin wrote:
On Tue, Feb 09, 2021 at 02:51:05PM +, Daniel P. Berrangé wrote:
On Tue, Feb 09, 2021 at 09:34:20AM -0500, Michael S. Tsirkin wrote:
O
Since the virtio-gpu-ccw device depends on the hw-display-virtio-gpu
module, which provides the type virtio-gpu-device, packaging the
hw-display-virtio-gpu module as a separate package that may or may not
be installed along with the qemu package leads to problems. Namely if
the hw-display-virtio-gp
From: Bin Meng
Some peripherals require 64-bit PCI address, so let's map the high
mmio space for PCIe.
For RV32, the address is hardcoded to below 4 GiB from the highest
accessible physical address. For RV64, the base address depends on
top of RAM and is aligned to its size which is using 16 GiB
From: Laurent Vivier
After a migration the clock offset is updated, but we also
need to re-arm the alarm if needed.
Signed-off-by: Laurent Vivier
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20201220112615.933036-7-laur...@vivier.eu
Signed-off-by: Alistair Fra
From: Bin Meng
There is already a MemMapEntry type defined in hwaddr.h. Let's drop
the RISC-V defined `struct MemmapEntry` and use the existing one.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20210122122958.12311-2-bmeng...@gmail.com
From: Bin Meng
Add RISC-V system emulator documentation for generic information.
`Board-specific documentation` and `RISC-V CPU features` are only
a placeholder and will be added in the future.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210126060007.12904-9-bmeng...@gm
From: Bin Meng
This adds detailed documentation for RISC-V `sifive_u` machine,
including the following information:
- Supported devices
- Hardware configuration information
- Boot options
- Machine-specific options
- Running Linux kernel
- Running VxWorks kernel
- Running U-Boot, and with an alt
From: Bin Meng
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210126060007.12904-8-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
docs/system/targets.rst | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/docs/system/targets.r
From: Bin Meng
RV32 supports 34-bit physical address hence the maximum RAM size
should be limitted. Limit the RAM size to 10 GiB, which leaves
some room for PCIe high mmio space.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210122122958.12311-4-bmeng...@gmail.com
Signed-
From: Bin Meng
All other peripherals' IRQs are in the format of decimal value.
Change SIFIVE_U_GEM_IRQ to be consistent.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210126060007.12904-7-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
include/hw/riscv/sifive_u.h
From: Bin Meng
This adds the QSPI2 controller to the SoC, and connects an SD
card to it. The generation of corresponding device tree source
fragment is also added.
Specify machine property `msel` to 11 to boot the same upstream
U-Boot SPL and payload image for the SiFive HiFive Unleashed board.
From: Bin Meng
This adds the QSPI0 controller to the SoC, and connects an ISSI
25WP256 flash to it. The generation of corresponding device tree
source fragment is also added.
Since the direct memory-mapped mode is not supported by the SiFive
SPI model, the property does not populate the second
From: Bin Meng
This updates the flash information table to include various ISSI
flashes that are supported by upstream U-Boot and Linux kernel.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Message-id: 20210126060007.12904-3-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
hw/bloc
From: Bin Meng
`link_up` is never used in gpex_pcie_init(). Drop it.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210122122958.12311-3-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletio
From: Bin Meng
This adds the SiFive SPI controller model for the FU540 SoC.
The direct memory-mapped SPI flash mode is unsupported.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210126060007.12904-4-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
include/hw/ssi/s
From: Bin Meng
At present when blk_pread() / blk_pwrite() fails, a guest error
is logged, but this is not really a guest error. Change to use
error_report() instead.
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 1611026585-29971-1-git-se
From: Bin Meng
This adds the ISSI SPI flash support. The number of dummy cycles in
fast read, fast read dual output and fast read quad output commands
is currently using the default 8. Likewise, the same default value
is used for fast read dual/quad I/O command. Per the datasheet [1],
the number
Signed-off-by: Alistair Francis
Acked-by: Bin Meng
Acked-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Palmer Dabbelt
Message-id:
6bc077e5ae4a9512c8adf81ae194718f2f17c402.1612836645.git.alistair.fran...@wdc.com
---
MAINTAINERS | 9 +
1 file changed, 9 insertions
From: Yifei Jiang
Add the support needed for creating prstatus elf notes. This allows
us to use QMP dump-guest-memory.
Now ELF notes of RISC-V only contain prstatus elf notes.
Signed-off-by: Yifei Jiang
Signed-off-by: Mingwang Li
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Revie
From: Bin Meng
csr_ops[] is currently declared with an unknown size in cpu.h.
Since the array size is known, let's do a complete declaration.
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 1611024723-14293-1-git-send-email-bmeng...@gmail.
tags/pull-riscv-to-apply-20210217-1
for you to fetch changes up to d0867d2dad4125d2295b28d6f91fa49cf034ffd2:
hw/riscv: virt: Map high mmio for PCIe (2021-02-17 17:47:19 -0800)
RISC-V PR for 6.0
This PR is a collection of RISC
On 21-02-11 17:46:39, Jonathan Cameron wrote:
> On Tue, 2 Feb 2021 14:58:30 +
> Jonathan Cameron wrote:
>
> > On Mon, 1 Feb 2021 16:59:22 -0800
> > Ben Widawsky wrote:
> >
> > > This is the beginning of implementing mailbox support for CXL 2.0
> > > devices. The implementation recognizes wh
Patchew URL:
https://patchew.org/QEMU/20210217234023.1742406-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210217234023.1742406-1-richard.hender...@linaro.org
Subject: [PULL 00/35] he
The following changes since commit f0f75dc174b6c79eb78a161d1c0921f82d7f1bf0:
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into
staging (2021-02-17 13:04:48 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-he
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-33-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
tests/tcg/hexagon/atomics.c | 139 +++
tests/tcg/hexagon/dual_stores.c | 60 +
tests/tcg/hexagon/mem_noshuf.c|
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-34-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
tests/tcg/hexagon/fpstuff.c | 370 ++
tests/tcg/hexagon/Makefile.targe
From: Taylor Simpson
Enable multiarch tests for Hexagon
Modify tests/tcg/configure.sh
Add reference files to tests/tcg/hexagon
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612763186-18161-32-git-send-email-tsimp...@quicinc.com>
From: Taylor Simpson
Read the instruction memory
Create a packet data structure
Generate TCG code for the start of the packet
Invoke the generate function for each instruction
Generate TCG code for the end of the packet
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-30-git-send-ema
From: Taylor Simpson
Add file to default-configs
Add hexagon to meson.build
Add hexagon to target/meson.build
Add target/hexagon/meson.build
Change scripts/qemu-binfmt-conf.sh
We can build a hexagon-linux-user target and run programs on
the Hexagon scalar core. With hexagon-linux-clang installe
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612763186-18161-24-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/opcodes.h | 58
target/hexagon/opc
From: Taylor Simpson
The imported code uses host floating point. We override them
to use qemu softfloat
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-29-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/gen_
From: Taylor Simpson
Implementation of Linux user emulation for Hexagon
Some common files modified in addition to new files in linux-user/hexagon
Acked-by: Laurent Vivier
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-31-git-send-email-tsimp...@quic
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612763186-18161-18-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/fma_emu.h | 36 ++
target/hexagon/fma_emu.c | 702 +
From: Taylor Simpson
Helpers won't work if there are multiple definitions, so we override these
instructions using #define fGEN_TCG_.
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-28-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/gen_tcg
From: Taylor Simpson
Run the C preprocessor across the instruction definition files and macro
definition file to expand macros and prepare the semantics_generated.pyinc
file. The resulting file contains one entry with the semantics for each
instruction and one line with the instruction attribute
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-16-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/arch.h | 34 +
target/hexagon/arch.c | 300 ++
2 files changed, 334 insertio
From: Taylor Simpson
Include the generated files and set up the data structures
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-27-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/genptr.h | 25 +++
target/hexagon/genptr.c | 331 +++
From: Taylor Simpson
Determine legal VLIW slots for each instruction
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-26-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/iclass.h| 50 +++
From: Taylor Simpson
Python script that emits the decode tree in dectree_generated.h.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-23-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/dectree.py | 351 ++
From: Taylor Simpson
Take the words from instruction memory and build a packet_t for TCG code
generation
The following operations are performed
Convert the .new encoded offset to the register number of the producer
Reorder the packet so .new producer is before consumer
Apply constant
From: Taylor Simpson
macros to interface with the generator
macros referenced in instruction semantics
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-25-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/macros
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-13-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/attribs.h | 35
target/hexagon/
From: Taylor Simpson
Python scripts generate the following files
helper_protos_generated.h.inc
For each instruction we create DEF_HELPER function prototype
helper_funcs_generated.c.inc
For each instruction we create the helper function definition
tcg_funcs_generated.c.
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-17-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/conv_emu.h | 31 +++
target/hexagon/conv_emu.c | 177 ++
2 files changed, 208 in
From: Taylor Simpson
GDB register read and write routines
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612763186-18161-9-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/internal.h | 2
From: Taylor Simpson
The insn_t and packet_t are the interface between instruction decoding and
TCG code generation
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-11-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/h
From: Taylor Simpson
Run the C preprocessor across the instruction definition and encoding
files to expand macros and prepare the iset.py file. The resulting
fill contains python data structures used to build the decode tree.
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
R
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-15-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/printinsn.h | 27 +++
target/hexagon/printinsn.
From: Taylor Simpson
Define types used in files imported from the Hexagon architecture library
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612763186-18161-10-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderso
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612763186-18161-7-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/hex_regs.h | 83 +
From: Taylor Simpson
Declare bitfields within registers such as user status register (USR)
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-12-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/reg_fields.h
From: Taylor Simpson
Add hexagon to disas/meson.build
Add disas/hexagon.c
Add hexagon to include/disas/dis-asm.h
Signed-off-by: Taylor Simpson
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612763186-18161-6-git-send-email-tsimp...@quicinc.com>
Signed-off-
From: Taylor Simpson
Add target state header, target definitions and initialization routines
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-5-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/cpu-param.h | 29
target/hexagon/cpu.h
From: Taylor Simpson
The majority of helpers are generated. Define the helper functions needed
then include the generated file
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-8-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/helper.h|
From: Taylor Simpson
Define EM_HEXAGON 164
Signed-off-by: Taylor Simpson
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-4-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
include/el
From: Taylor Simpson
Gives an introduction and overview to the Hexagon target
Signed-off-by: Taylor Simpson
Message-Id: <1612763186-18161-3-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/README | 235 ++
1 file
Signed-off-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Message-Id: <20201021045149.1582203-2-richard.hender...@linaro.org>
---
include/qemu/int128.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/
From: Taylor Simpson
Add Taylor Simpson as the Hexagon target maintainer
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1612763186-18161-2-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 9 +
1 file changed, 9 inserti
When parent directory has default acl and a file is created in that
directory, then umask is ignored and final file permissions are
determined using default acl instead. (man 2 umask).
Currently, fuse applies the umask and sends modified mode in create
request accordingly. fuse server can set FUSE
fuse has an option FUSE_POSIX_ACL which needs to be opted in by fuse
server to enable posix acls.
Add virtiofsd option "-o posix_acl/no_posix_acl" to let users enable/disable
posix acl support. By default it is disabled as of now.
Currently even if file server has not opted in for FUSE_POSIX_ACL,
Next patch is going to make use of "umask" syscall. So allow it.
Signed-off-by: Vivek Goyal
---
tools/virtiofsd/passthrough_seccomp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/virtiofsd/passthrough_seccomp.c
b/tools/virtiofsd/passthrough_seccomp.c
index 62441cfcdb..f49ed94b5e 10
Hi,
This is V2 of the patches. Changes since v1 are.
- Rebased on top of latest master.
- Took care of Miklos's comments to block acl xattrs if user
explicitly disabled posix acl.
Luis Henriques reported that fstest generic/099 fails with virtiofs.
Little debugging showed that we don't enable
Cleber Rosa writes:
> On Thu, Feb 11, 2021 at 05:19:45PM +, Alex Bennée wrote:
>> These tests make sure we can boot the Xen hypervisor with a Dom0
>> kernel using the guest-loader. We currently have to use a kernel I
>> built myself because there are issues using the Debian kernel images.
>
On 21-02-02 12:23:50, Jonathan Cameron wrote:
> On Mon, 1 Feb 2021 16:59:21 -0800
> Ben Widawsky wrote:
>
> > This implements all device MMIO up to the first capability. That
> > includes the CXL Device Capabilities Array Register, as well as all of
> > the CXL Device Capability Header Registers.
Patchew URL:
https://patchew.org/QEMU/20210217202036.1724901-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210217202036.1724901-1-richard.hender...@linaro.org
Subject: [PATCH v4 00/71
On Wed, Feb 17, 2021 at 12:03:16PM +0100, Thomas Huth wrote:
> On 17/02/2021 11.07, Stefan Hajnoczi wrote:
> > QEMU is participating in Outreachy May-August and is applying for GSoC
> > 2021. It's time to publish information on these internship programs and
> > how to apply.
>
> Thanks, it's onlin
On 2/17/21 12:15 PM, Laurent Vivier wrote:
>> +#include "../i386/termbits.h"
>
> should be #include "../generic/termbits.h"
>
> Acked-by: Laurent Vivier
Fixed against the v8 patch set. Thanks,
r~
Hi Daniel, Philippe,
Op di 16 feb. 2021 10:49 schreef Daniel P. Berrangé :
> On Fri, Feb 12, 2021 at 03:10:00PM +0100, Philippe Mathieu-Daudé wrote:
> > Hi Niek and QEMU community,
> >
> > On 2/11/21 11:00 PM, Niek Linnenbank wrote:
> > > The following are maintenance patches for the Allwinner
We're currently only testing TCI with a 64-bit host -- also test
with a 32-bit host. Enable a selection of softmmu and user-only
targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
.gitlab-ci.d/crossbu
Expand the single-use macros into the new functions.
Use cpu_ldsb_mmuidx_ra and cpu_ldsw_le_mmuidx_ra so
that the trace event receives the correct sign flag.
Signed-off-by: Richard Henderson
---
tcg/tci.c | 215 +++---
1 file changed, 75 insertions
We already had mulu2_i32 for a 32-bit host; expand this to 64-bit
hosts as well. The muls2_i32 and the 64-bit opcodes are new.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 8
tcg/tci.c| 35 +--
tcg/tci/tcg-target.c.inc
The longest test at the moment seems to be a (slower)
aarch64 host, for which test-mmap takes 64 seconds.
Signed-off-by: Richard Henderson
---
configure | 3 +++
tests/tcg/Makefile.target | 6 --
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/configure b/confi
This operation is critical to staying within the interpretation
loop longer, which avoids the overhead of setup and teardown for
many TBs.
The check in tcg_prologue_init is disabled because TCI does
want to use NULL to indicate exit, as opposed to branching to
a real epilogue.
Signed-off-by: Rich
We already had the 32-bit versions for a 32-bit host; expand this
to 64-bit hosts as well. The 64-bit opcodes are new.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 8
tcg/tci.c| 40 ++--
tcg/tci/tcg-target.c.inc |
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index eeafec6d44..e4a5872b2a 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.i
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 12 +--
tcg/tci.c| 44
tcg/tci/tcg-target.c.inc | 9
3 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target
When this opcode is not available in the backend, tcg middle-end
will expand this as a series of 5 opcodes. So implementing this
saves bytecode space.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 4 ++--
tcg/tci.c| 16 +++-
tcg/tci/tcg-target.c.in
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index f7595fbd65..c2bbd85130 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.
These were already present in tcg-target.c.inc,
but not in the interpreter.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 20 ++--
tcg/tci.c| 40
2 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/tc
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