Hi,
> +DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1),
IIRC we have a DEFINE_PROP_SIZE() which can parse units and therefore
accepts -- for example -- "512k" or "1M".
take care,
Gerd
*** This bug is a duplicate of bug 1913873 ***
https://bugs.launchpad.net/bugs/1913873
Chronogically speaking #1913873 is a duplicate of #1890152...
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/
Cc'ing Dmitry Fleytman
On 1/31/21 5:29 AM, Gaoning Pan wrote:
> Public bug reported:
>
> Hello,
>
> I found an assertion failure in hw/net/vmxnet3.c:1793
>
> This was found in latest version 5.2.0.
>
> my reproduced is as follows:
>
>
> cat << EOF | ./qemu-system-x86_64 \
> -device vmxnet3 \
On 2/1/21 1:01 AM, BALATON Zoltan wrote:
> From: Lucien Murray-Pitts
>
> The BUSCR/PCR CR defines were missing for 68060, and the move_to/from helper
> functions were also missing a decode for the 68060 M68K_CR_CAAR CR register.
>
> Added missing defines, and respective decodes for all three CR
On Mon, Feb 1, 2021 at 7:10 AM Jason Wang wrote:
>
>
> On 2021/1/30 上午4:54, Eugenio Pérez wrote:
> > Signed-off-by: Eugenio Pérez
> > ---
> > include/hw/virtio/virtio.h | 2 ++
> > hw/virtio/virtio.c | 5 +
> > 2 files changed, 7 insertions(+)
> >
> > diff --git a/include/hw/virti
On 25.01.2021 14:09, Alex Bennée wrote:
Pavel Dovgalyuk writes:
On 22.01.2021 14:42, Alex Bennée wrote:
Pavel Dovgalyuk writes:
Sometimes we need to collect the translation logs starting
from some point of the execution. Some TB listings may
be missed in this case, when blocks were trans
Sometimes interrupt event comes at the same time with
the virtual timers. In this case replay tries to proceed
the timers, because deadline for them is zero.
This patch allows processing interrupts and exceptions
by entering the vCPU execution loop, when deadline is zero,
but checkpoint associated
On 30/01/2021 17.46, Warner Losh wrote:
bsd-user: Add new mainatiners
The FreeBSD project has a number of enhancements to bsd-user. Add myself
as maintainer and Kyle Evans as a reviewer. Also add our github repo.
Signed-off-by: Warner Losh mailto:i...@bsdimp.com>>
---
MAINTAINERS | 5 -
On 2021/1/30 上午4:54, Eugenio Pérez wrote:
Shadow virtqueue notifications forwarding is disabled when vhost_dev
stops.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 5 ++
include/hw/virtio/vhost.h | 4 +
hw/virtio/vhost-shadow-virtqueue.c | 123
On 30/01/2021 17.46, Warner Losh wrote:
bsd-user: Add new mainatiners
s/mainatiners/maintainers/
The FreeBSD project has a number of enhancements to bsd-user. Add myself
as maintainer and Kyle Evans as a reviewer. Also add our github repo.
Thanks for taking care of this!
Signed-off-by: Wa
ping？This patch set about code style problem in net receives no replies.
Did I miss any response?
The link follows:
http://patchwork.ozlabs.org/project/qemu-devel/cover/20201222082340.67405-1-zhangha...@huawei.com/
ping？This patch set about code style problem in qobject receives no replies.
Did I miss any response?
The link follows:
http://patchwork.ozlabs.org/project/qemu-devel/cover/20201228071129.24563-1-zhangha...@huawei.com/
On 2021/1/30 上午4:54, Eugenio Pérez wrote:
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/vhost.h | 1 +
hw/virtio/vhost.c | 17 +
2 files changed, 18 insertions(+)
diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index 4a8bc75415..fca076e3f0
On 2021/1/30 上午4:54, Eugenio Pérez wrote:
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/virtio.h | 2 ++
hw/virtio/virtio.c | 5 +
2 files changed, 7 insertions(+)
diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index 9988c6d5c9..9013c03424 100644
---
On 2021/1/29 下午5:07, Eugenio Pérez wrote:
Not checking this can lead to invalid dev->vdev member access in
vhost_device_iotlb_miss if backend issue an iotlb message in a bad
timing, either maliciously or by a bug.
Reproduced rebooting a guest with testpmd in txonly forward mode.
#0 0x55
The last branch recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors that records a running trace of the most
recent branches taken by the processor in the LBR stack. The QEMU
could configure whether it's enabled or not for each guest via CLI.
The LBR feature would be en
Eduardo has a suggestion: instead of hardcoding the
PERF_CAPABILITIES rules in this loop, this could become a
FeatureWordInfo field. It would be very useful for other
features like intel-pt, where we need some bits to match the
host too.
Suggested-by: Eduardo Habkost
Signed-off-by: Like Xu
---
On Fri, Jan 29, 2021 at 12:17:19PM +0100, Cédric Le Goater wrote:
65;6201;1c> The memory layout of the PowerNV machine is defined as :
>
> #define KERNEL_LOAD_BASE((void *)0x2000)
> #define KERNEL_LOAD_SIZE0x0800
>
> #define INITRAMFS_LOAD_BASE KERNEL_LOAD_BASE + KERNEL_LOAD
On 2021/1/27 22:21, Alex Williamson wrote:
> On Wed, 27 Jan 2021 19:27:35 +0800
> Shenming Lu wrote:
>
>> On 2021/1/27 5:36, Alex Williamson wrote:
>>> On Wed, 9 Dec 2020 16:09:19 +0800
>>> Shenming Lu wrote:
>>>
Different from the normal situation when the guest starts, we can
know
Any comments?
It's really a bug and can cause the qemu to segmentfault.
Thanks,
Michael
-Original Message-
From: 仇大玉
Sent: 2021年1月28日 13:16
To: qemu-bl...@nongnu.org; qemu-devel@nongnu.org
Cc: kw...@redhat.com; mre...@redhat.com; js...@redhat.com; 08005...@163.com
Subject: RE: [PATCH v4
From: Lucien Murray-Pitts
The m680XX_cpu_initfn functions have been rearranged to cascade starting from
the base 68000, so that the 68010 then inherits from this, and so on until the
68060.
This makes it simpler to track features since in most cases the m68k were
product enhancements on each oth
From: Lucien Murray-Pitts
On m68k there are two varities of stack pointers: USP with SSP or ISP/MSP.
Only the 68020/30/40 support the MSP register the stack swap helpers don't
support this feature.
This patch adds this support, as well as comments to CPUM68KState to
make it clear how stacks are
From: Lucien Murray-Pitts
Add CPU class detection for each CR type in the m68k_move_to/from helpers,
so that it throws and exception if an unsupported register is requested
for that CPU class.
Reclassified MOVEC insn. as only supported from 68010.
Signed-off-by: Lucien Murray-Pitts
Signed-off-
From: Lucien Murray-Pitts
The BUSCR/PCR CR defines were missing for 68060, and the move_to/from helper
functions were also missing a decode for the 68060 M68K_CR_CAAR CR register.
Added missing defines, and respective decodes for all three CR registers to
the helpers.
Although this patch define
From: Lucien Murray-Pitts
Improvement in comments for the instantiation functions.
This is to highlight what each cpu class, in the 68000 series, contains
in terms of instructions/features.
Signed-off-by: Lucien Murray-Pitts
Signed-off-by: BALATON Zoltan
---
target/m68k/cpu.c | 44 +++
From: Lucien Murray-Pitts
Add more detailed comments to each case of m68k_move_to/from helpers to list
the supported CPUs for that CR as they were wrong in some cases, and
missing some cpu classes in other cases.
Signed-off-by: Lucien Murray-Pitts
Signed-off-by: BALATON Zoltan
---
target/m68k
Hello,
This is Lucien's m68k series rebased on and fixed up to work with
current master as per previous discussion:
https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg02840.html
I've left previous Reviewed-by tags for reference but these should
probably be reviewed again. I've only lightly
On Fri, 29 Jan 2021, at 19:09, Cédric Le Goater wrote:
> On 1/28/21 11:40 PM, David Gibson wrote:
> > On Thu, Jan 28, 2021 at 08:46:01AM +0100, Cédric Le Goater wrote:
> >> On 1/28/21 1:46 AM, Joel Stanley wrote:
> >>> On Tue, 26 Jan 2021 at 17:14, Cédric Le Goater wrote:
>
> and reus
On 1/31/21 1:38 AM, Liren Wei wrote:
> However, similar to the situation described in:
> https://lists.nongnu.org/archive/html/qemu-devel/2018-02/msg02529.html
>
> When we have 2 vCPUs with one of them writing to the code page while
> the other just translated some code within that same page, the
Public bug reported:
Operating system: Gentoo
Architecture: x86_64
kernel version: 5.4.72, 5.10.11
libvirt version: at least 6.9.0, 6.10.0, 7.0.0
Hypervisor and version: qemu 5.1.0, 5.2.0
With software versions described above and following configurations:
libvirt:
key_file = "/etc/ssl/libvirt/se
For Orange Pi PC:
Reviewed-by: Niek Linnenbank
Op zo 31 jan. 2021 19:45 schreef Philippe Mathieu-Daudé :
> Most of ARM machines display their CPU when QEMU list the available
> machines (-M help). Some machines do not. Fix to unify the help
> output.
>
> Signed-off-by: Philippe Mathieu-Daudé
>
On 1/29/21 9:10 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/sparc/tcg-target-con-str.h | 23 ++
> tcg/sparc/tcg-target.h | 5 +--
> tcg/sparc/tcg-target.c.inc | 81 +-
> 3 files changed, 55 insertions(+), 54 dele
On 1/31/21 6:34 PM, Volker Rümelin wrote:
> Commit 4e66c9ef64 "tracetool: add input filename and line number to
> Event" forgot to add a line number and a filename argument at one
> build method call site.
>
> Traceback (most recent call last):
> File "./scripts/simpletrace.py", line 261, in
>
I have identified the core issue:
Synchronous exceptions/traps in linux-user/i386/cpu_loop.c are handled as a
return value from cpu_exec().
cpu_exec() resets exception_index to -1 in cpu_handle_exception()
This means that queue_signal() (called from gen_signal() in the cpu
loop) does not store
On 1/31/21 3:45 PM, andrew.cooper3--- via wrote:
> On 31/01/2021 14:18, Philippe Mathieu-Daudé wrote:
>> The Xen on ARM documentation only mentions the i386-softmmu
>> target. As the x86_64-softmmu doesn't seem used, remove it
>> to avoid wasting cpu cycles building it.
>>
>> Signed-off-by: Philipp
Most of ARM machines display their CPU when QEMU list the available
machines (-M help). Some machines do not. Fix to unify the help
output.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/digic_boards.c | 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.
The Versal SoC instantiates the TYPE_XLNX_ZYNQMP_RTC object in
versal_create_rtc()(). Select CONFIG_XLNX_ZYNQMP to fix:
$ make check-qtest-aarch64
...
Running test qtest-aarch64/qom-test
qemu-system-aarch64: missing object type 'xlnx-zynmp.rtc'
Broken pipe
Signed-off-by: Philippe Mathie
Add a dependency XLNX_ZYNQMP -> PTIMER to fix:
/usr/bin/ld:
libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o: in function
`xlnx_zynqmp_can_realize':
hw/net/can/xlnx-zynqmp-can.c:1082: undefined reference to `ptimer_init'
hw/net/can/xlnx-zynqmp-can.c:1085: undefined reference to
`ptimer_tran
The Versal SoC instantiates the TYPE_XLNX_ZDMA object in
versal_create_admas(). Introduce the XLNX_ZDMA configuration
and select it to fix:
$ qemu-system-aarch64 -M xlnx-versal-virt ...
qemu-system-aarch64: missing object type 'xlnx.zdma'
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Alistai
The STM32F405 SoC uses an OR gate on its ADC IRQs.
Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC")
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: alist...@alistair23.me
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 13cc42dcc84..a
The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines.
Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization")
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Igor Mitsyanko
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index a
Trivial bugfixes and cleanup patches noticed while rebasing
my "Support disabling TCG on ARM (part 2)" series.
Since v2:
- removed incorrect patches added in v2 =)
- more fixes for Versal board (CAN, RTC)
Since v1:
- added patches to remove 64-bit specific features on 32-bit build.
Philippe Math
On 1/31/21 5:44 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> The following machines are no more built when TCG is disabled:
Hi,
I started setting up some developer documentation for 9pfs:
https://wiki.qemu.org/Documentation/9p
Still quite a bunch that should be added (e.g. there should be a section about
threads and coroutines), but at least it's a start ...
Best regards,
Christian Schoenebeck
Commit 4e66c9ef64 "tracetool: add input filename and line number to
Event" forgot to add a line number and a filename argument at one
build method call site.
Traceback (most recent call last):
File "./scripts/simpletrace.py", line 261, in
run(Formatter())
File "./scripts/simpletrace.py",
Hi,
-hw->samples = obt.samples;
+hw->samples = (spdo->has_buffer_count ? spdo->buffer_count : 4) *
+obt.samples;
+# @buffer-count: number of buffers (default 4)
Any specific reason for this default?
In my testing I've needed much higher values.
8 still got me crackling sound
> Jannik, can you send a Signed-off-by line so we can accept
> your patch? See:
> https://wiki.qemu.org/Contribute/SubmitAPatch#Patch_emails_must_include_a_Signed-off-by:_line
Sure! I hope this is right, I'm not exactly experienced with mailing
list development.
Signed-off-by: Jannik Glückert
>
#ifdef DEBUG
-alsa_dump_info(req, obt, obtfmt, pdo);
+alsa_dump_info(req, obt, obtfmt, apdo);
#endif
"if (DEBUG) { }" is a nice way to have this checked by the
compiler. With "#define DEBUG 0" the compiler will optimize away
the dead code, so it isn't much different to #ifdef'ed
We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d0853fae5ae..2d8312267
IDAU is specific to M-profile. KVM only supports A-profile.
Restrict this interface to TCG, as it is pointless (and
confusing) on a KVM-only build.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 7 ---
target/arm/cpu_tcg.c | 8
2 files changed, 8 insertions(+), 7 d
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
A KVM-only build won't be able to run TCG cpus, move the
v7A CPU definitions to cpu_tcg.c.
Reported-by: Peter Maydell
Si
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
The following machines are no more built when TCG is disabled:
- cubieboard cubietech cubieboard (Cortex-A8)
Machines can be automatically selected using the Kconfig
'default y' syntax. This change allow deselecting these
machines without having to modify default-configs/ files.
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/devices/aarch64-softmmu.mak | 3 ---
default-configs/devices/arm-so
KVM requires the target cpu to be at least ARMv8 architecture.
Restrict the last ARMv7 CPUs (A-profile) to TCG.
(This is where I realize no need to split the v7 A/R/M profiles
anymore... I could have use a single ARM_V7, although it is useful
to have the M-profile separated).
Based-on: <20210131
On 1/31/21 4:22 PM, Jannik Glückert wrote:
>> Jannik, can you send a Signed-off-by line so we can accept
>> your patch? See:
>> https://wiki.qemu.org/Contribute/SubmitAPatch#Patch_emails_must_include_a_Signed-off-by:_line
>
> Sure! I hope this is right, I'm not exactly experienced with mailing
> l
Hi Zenghui,
On 1/30/21 5:32 AM, Zenghui Yu wrote:
> When handling guest range-based IOTLB invalidation, we should decode the TG
> field into the corresponding translation granule size so that we can pass
> the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to
> properly emula
On 1/30/21 7:54 PM, Peter Maydell wrote:
> On Sat, 30 Jan 2021 at 18:36, Philippe Mathieu-Daudé wrote:
>>
>> Hi Peter,
>>
>> On 1/30/21 4:37 PM, Peter Maydell wrote:
>>> On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé
>>> wrote:
KVM requires a cpu based on (at least) the ARMv7 arc
On 1/31/21 1:36 PM, Philippe Mathieu-Daudé wrote:
> On 1/31/21 12:13 PM, Philippe Mathieu-Daudé wrote:
>> Add a target-specific Kconfig.
>>
>> Target foo now has CONFIG_FOO defined.
>>
>> Two architecture have a particularity, ARM and MIPS:
>> their 64-bit version include the 32-bit subset.
>>
>> S
On 1/31/21 1:31 PM, Philippe Mathieu-Daudé wrote:
> On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote:
>> The SBSA-ref board only use CPUs available in the 64-bit build,
>> it is pointless to have it available in the 32-bit build.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> Cc: Radoslaw
On 1/31/21 1:31 PM, Philippe Mathieu-Daudé wrote:
> On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote:
>> The ZynqMP ZCU102 board only use the Cortex-A53 CPU, which
>> is only available in the 64-bit build. It is pointless to
>> have this board present in the 32-bit build where this CPU
>> is not a
On 1/31/21 3:18 PM, Claudio Fontana wrote:
> On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
>> Modules are registered early with type_register_static().
>>
>> We would like to call tcg_enabled() when registering QOM types,
>
>
> Hi Philippe,
>
> could this not be controlled by meson at this
On 1/31/21 3:40 PM, Claudio Fontana wrote:
> On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
>> Cover from Samuel Ortiz from (part 1) [1]:
>>
>> This patchset allows for building and running ARM targets with TCG
>> disabled. [...]
>>
>> The rationale behind this work comes from the NEMU pr
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
>From the various SoC used by the Raspberry Pi machines, only
the BCM2837 is an ARMv8 (Cortex-A53).
Restrict the BCM2835
Move the abstract TYPE_BCM283X and TYPE_RASPI_MACHINE declarations
earlier to make the next commit easier to review.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/bcm2836.c | 32 +---
hw/arm/raspi.c | 18 ++
2 files changed, 27 insertions(+), 23 d
Peter mentioned [*] KVM only support ARMv8 targets. Restrict the
non-ARMv8 machines to TCG.
While this is still not enough to boot a raspi3 image using KVM:
$ qemu-system-aarch64 -M raspi3b -enable-kvm ...
qemu-system-aarch64: ../../softmmu/physmem.c:745: cpu_address_space_init: A=
ssertion `
On 1/31/21 3:34 PM, Sergei Trofimovich wrote:
> Before the change /usr/share/qemu/firmware/50-edk2-x86_64-secure.json
> contained the relative path:
> "filename": "share/qemu/edk2-x86_64-secure-code.fd",
> "filename": "share/qemu/edk2-i386-vars.fd",
>
> After then change th
On 31/01/2021 14:18, Philippe Mathieu-Daudé wrote:
> The Xen on ARM documentation only mentions the i386-softmmu
> target. As the x86_64-softmmu doesn't seem used, remove it
> to avoid wasting cpu cycles building it.
>
> Signed-off-by: Philippe Mathieu-Daudé
As far as I understand, it only gets u
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> Cover from Samuel Ortiz from (part 1) [1]:
>
> This patchset allows for building and running ARM targets with TCG
> disabled. [...]
>
> The rationale behind this work comes from the NEMU project where
> we're trying to only support x86
Before the change /usr/share/qemu/firmware/50-edk2-x86_64-secure.json
contained the relative path:
"filename": "share/qemu/edk2-x86_64-secure-code.fd",
"filename": "share/qemu/edk2-i386-vars.fd",
After then change the paths are absolute:
"filename": "/usr/share/
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Beside, KVM only supports A-profile, thus won't be able to ru
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Beside, KVM only supports A-profile, thus won't be able to ru
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Only enable the following ARMv6 CPUs when TCG is available:
>
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Only enable the following ARMv5 CPUs when TCG is available:
>
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Only enable the following ARMv4 CPUs when TCG is available:
>
xenpv machine requires USB, IDE_PIIX and PCI:
/usr/bin/ld:
libcommon.fa.p/hw_xen_xen-legacy-backend.c.o: in function
`xen_be_register_common':
hw/xen/xen-legacy-backend.c:757: undefined reference to `xen_usb_ops'
libqemu-i386-softmmu.fa.p/hw_i386_xen_xen_platform.c.o: in function
`unplug
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> Fixes when building with --disable-tcg on ARM:
>
> In file included from target/arm/helper.c:16:
> include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file
> or directory
> 42 | #include "tcg-runtime.h"
> |
9pfs is not an accelerator feature but a machine one,
move the selection on the machine Kconfig (in hw/).
Signed-off-by: Philippe Mathieu-Daudé
---
accel/Kconfig | 1 -
hw/i386/xen/Kconfig | 1 +
hw/xen/Kconfig | 1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/accel
The Xen on ARM documentation only mentions the i386-softmmu
target. As the x86_64-softmmu doesn't seem used, remove it
to avoid wasting cpu cycles building it.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/meson.bui
Introduce XEN_FV to differency the machine from the accelerator.
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/Kconfig | 2 ++
hw/i386/xen/Kconfig | 5 +
hw/i386/xen/meson.build | 2 +-
3 files changed, 8 insertions(+), 1 deletion(-)
create mode
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> Modules are registered early with type_register_static().
>
> We would like to call tcg_enabled() when registering QOM types,
Hi Philippe,
could this not be controlled by meson at this stage?
On X86, I register the tcg-specific types in tcg/*
Sort the Xen buildsys glue a bit.
v2: Considered Paolo's comments from v1
Supersedes: <20210129194415.3925153-1-f4...@amsat.org>
Philippe Mathieu-Daudé (4):
meson: Do not build Xen x86_64-softmmu on Aarch64
hw/i386/xen: Introduce XEN_FV Kconfig
hw/xen/Kconfig: Introduce XEN_PV config
hw/
Gentoo also noticed the bug: https://bugs.gentoo.org/766743
Jannik Glückert proposed a fix:
```
--- a/pc-bios/descriptors/meson.build
+++ b/pc-bios/descriptors/meson.build
@@ -8,7 +8,7 @@ foreach f: [
]
configure_file(input: files(f),
output: f,
- configurati
On 1/29/21 8:59 PM, Paolo Bonzini wrote:
> On 29/01/21 20:44, Philippe Mathieu-Daudé wrote:
>> hw/ide/ioport.c has a strong dependency on hw/isa/isa-bus.c:
>>
>> /usr/bin/ld: libcommon.fa.p/hw_ide_ioport.c.o: in function
>> `ide_init_ioport':
>> /usr/bin/ld: hw/ide/ioport.c:61: undefined refe
Forwarding to qemu-security@ to see if this issue is worth a CVE.
On 1/31/21 12:57 PM, P J P wrote:
> +-- On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote --+
> | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote:
> | > Per the ARM Generic Interrupt Controller Architecture specification
> | > (do
On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote:
We want to be able to use the 'SH4' config for architecture
specific features. As CONFIG_SH4 is only used to select
peripherals, rename it CONFIG_SH4_PERIPHERALS.
PERIPHERALS is a bit long and hard to write correctly. How about
CONFIG_SH4_DEVI
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Beside, KVM only supports A-profile, thus won't be able to ru
On 1/31/21 12:13 PM, Philippe Mathieu-Daudé wrote:
> Add a target-specific Kconfig.
>
> Target foo now has CONFIG_FOO defined.
>
> Two architecture have a particularity, ARM and MIPS:
> their 64-bit version include the 32-bit subset.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
...
> diff -
On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote:
> The ZynqMP ZCU102 board only use the Cortex-A53 CPU, which
> is only available in the 64-bit build. It is pointless to
> have this board present in the 32-bit build where this CPU
> is not available.
>
> Signed-off-by: Philippe Mathieu-Daudé
>
On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote:
> The SBSA-ref board only use CPUs available in the 64-bit build,
> it is pointless to have it available in the 32-bit build.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Cc: Radoslaw Biernacki
> Cc: Leif Lindholm
> ---
> hw/arm/meson.bui
+-- On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote --+
| On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote:
| > Per the ARM Generic Interrupt Controller Architecture specification
| > (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit,
| > not 10:
| >
| > - Table 4-21 GICD
From: Philippe Mathieu-Daudé
Add a job to build QEMU on Aarch64 with TCG disabled, so
this configuration won't bitrot over time.
We explicitly modify default-configs/aarch64-softmmu.mak to
only select the 'virt' and 'SBSA-REF' machines.
Signed-off-by: Philippe Mathieu-Daudé
---
Job ran for 7 m
From: Samuel Ortiz
We can now safely turn all TCG dependent build off when CONFIG_TCG is
off. This allows building ARM binaries with --disable-tcg.
Signed-off-by: Samuel Ortiz
[PMD: Heavily rebased during more than 2 years then finally rewritten]
Reviewed-by: Richard Henderson
Signed-off-by: P
On Sun, Jan 31, 2021 at 12:51 PM Philippe Mathieu-Daudé wrote:
>
> From: Philippe Mathieu-Daudé
>
> Add a job to build QEMU on Aarch64 with TCG disabled, so
> this configuration won't bitrot over time.
>
> We explicitly modify default-configs/aarch64-softmmu.mak to
> only select the 'virt' and 'S
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Only enable the following ARMv6 CPUs when TCG is available:
- ARM1136
- ARM1176
- ARM11MPCore
- Cortex-M0
The fo
From: Philippe Mathieu-Daudé
Reorder the rules to make this file easier to modify.
No logical change introduced in this commit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/meson.build | 19 ---
1 file changed, 12 insertions(+), 7 deletio
From: Thomas Huth
We've already got the CONFIG_ARM_V7M switch, but it currently can
not be disabled yet. The m_helper.c code should not be compiled
into the binary if the switch is not enabled. We also have to
provide some stubs in a separate file to make sure that we still
can link the other cod
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Only enable the following ARMv4 CPUs when TCG is available:
- StrongARM (SA1100/1110)
- OMAP1510 (TI925T)
The follow
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Beside, KVM only supports A-profile, thus won't be able to run
M-profile cpus.
Only enable the following ARMv7 M-Profile
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Beside, KVM only supports A-profile, thus won't be able to run
R-profile cpus.
Only enable the following ARMv7 R-Profile
Fixes when building with --disable-tcg on ARM:
In file included from target/arm/helper.c:16:
include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file
or directory
42 | #include "tcg-runtime.h"
| ^~~
Signed-off-by: Philippe Mathieu-Daudé
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