Paolo Bonzini writes:
> On 21/01/21 10:27, Max Reitz wrote:
>> Sure, I can do that.
>> I agree that there probably are better solutions than to wrap
>> everything in a lock. OTOH, it looks to me like this lock is the
>> most simple solution. If Daniel is right[1] and we should drop
>> coroutin
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5e851028c592..9a5cfd4fc632 100644
--- a/target/arm/cpu64.c
+++ b/ta
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h | 12 +++
cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
Signed-off-by: Rebecca Cran
---
target/arm/helper-a64.c | 4 +---
target/arm/helper.c | 4 ++--
target/arm/op_helper.c | 9 +
3 files changed, 4 inse
As suggested in
https://www.mail-archive.com/qemu-devel@nongnu.org/msg767057.html
this second patch contains code to move PSTATE_SS from uncached_cpsr to
env->pstate.
Being fairly new to both aarch64 and qemu development I hope I'm on the
right track, but I suspect my implementation is incomplet
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1788665
Title:
Low 2D grap
On 01/21/21 22:22, Laszlo Ersek wrote:
> On 01/15/21 11:24, Gerd Hoffmann wrote:
>> qemu sends various state info like current cursor shape to newly connected
>> clients in response to a set_encoding message. This is not correct according
>> to the rfb spec. Send that information in response to a
Doug Evans, le jeu. 21 janv. 2021 16:42:51 -0800, a ecrit:
> DNS should be DHCP
>
> Signed-off-by: Doug Evans
Reviewed-by: Samuel Thibault
> ---
> net/slirp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/net/slirp.c b/net/slirp.c
> index 8350c6d45f..be914c0be0 100
DNS should be DHCP
Signed-off-by: Doug Evans
---
net/slirp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/slirp.c b/net/slirp.c
index 8350c6d45f..be914c0be0 100644
--- a/net/slirp.c
+++ b/net/slirp.c
@@ -473,7 +473,7 @@ static int net_slirp_init(NetClientState *peer, c
Using MMUAccessType makes it more clear what the variable's use is.
No functional change.
Signed-off-by: Joe Komlodi
---
target/microblaze/mmu.c | 2 +-
target/microblaze/mmu.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.
Using the cfg.use_non_secure bitfield and the MMU access type, we can determine
if the access should be secure or not.
Signed-off-by: Joe Komlodi
---
target/microblaze/cpu.c| 2 +-
target/microblaze/cpu.h| 3 ++-
target/microblaze/helper.c | 26 +++---
3 files chang
This property is used to control the security of the following interfaces
on MicroBlaze:
M_AXI_DP - data interface
M_AXI_IP - instruction interface
M_AXI_DC - dcache interface
M_AXI_IC - icache interface
It works by enabling or disabling the use of the non_secure[3:0] signals.
Interfaces and thei
This is a 10/100 ethernet device that has several features.
Only the ones needed by the Linux driver have been implemented.
See npcm7xx_emc.c for a list of unimplemented features.
Reviewed-by: Hao Wu
Reviewed-by: Avi Fishman
Signed-off-by: Doug Evans
---
docs/system/arm/nuvoton.rst| 3 +-
Hi all,
This series adds memattrs on MicroBlaze transactions.
It does so by adding support for the use-non-secure property on MicroBlaze CPUs.
>From there, we can then determine if the transaction should be secure or not,
and memory attributes can be set accordingly.
Thanks!
Joe
Joe Komlodi (3)
On 21-01-21 15:17:16, Keith Busch wrote:
> On Fri, Jan 22, 2021 at 07:09:06AM +0900, Minwoo Im wrote:
> > -static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
> > +static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t
> > cntlid)
> > {
> > NvmeIdCtrl *id = &n->id_ctrl;
On 21-01-21 15:03:38, Keith Busch wrote:
> On Fri, Jan 22, 2021 at 07:09:04AM +0900, Minwoo Im wrote:
> > --- a/hw/block/nvme.c
> > +++ b/hw/block/nvme.c
> > @@ -23,6 +23,7 @@
> > * max_ioqpairs=, \
> > * aerl=, aer_max_queued=, \
> > * mdts=,zoned.appen
On 21-01-21 14:52:02, Keith Busch wrote:
> On Fri, Jan 22, 2021 at 07:09:03AM +0900, Minwoo Im wrote:
> > +static void nvme_subsys_setup(NvmeSubsystem *subsys)
> > +{
> > +char *subnqn;
> > +
> > +subnqn = g_strdup_printf("nqn.2019-08.org.qemu:%s",
> > subsys->parent_obj.id);
> > +strp
On Fri, Jan 22, 2021 at 07:09:06AM +0900, Minwoo Im wrote:
> -static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
> +static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t cntlid)
> {
> NvmeIdCtrl *id = &n->id_ctrl;
> uint8_t *pci_conf = pci_dev->config;
>
> +
On Fri, Jan 22, 2021 at 07:09:04AM +0900, Minwoo Im wrote:
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -23,6 +23,7 @@
> * max_ioqpairs=, \
> * aerl=, aer_max_queued=, \
> * mdts=,zoned.append_size_limit= \
> + * ,subsys= \
For cons
On 12/11/20 12:39 PM, Vladimir Sementsov-Ogievskiy wrote:
> Make bdrv_pad_request() honest: return error if
> qemu_iovec_init_extended() failed.
>
> Update also bdrv_padding_destroy() to clean the structure for safety.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> block/io.c | 45
On Fri, Jan 22, 2021 at 07:09:03AM +0900, Minwoo Im wrote:
> +static void nvme_subsys_setup(NvmeSubsystem *subsys)
> +{
> +char *subnqn;
> +
> +subnqn = g_strdup_printf("nqn.2019-08.org.qemu:%s",
> subsys->parent_obj.id);
> +strpadcpy((char *)subsys->subnqn, sizeof(subsys->subnqn), sub
On 12/11/20 12:39 PM, Vladimir Sementsov-Ogievskiy wrote:
> Prepare to the following patch when bdrv_pad_request() will be able to
s/Prepare to/Prepare for/
> fail. Update the comments.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> block/io.c | 25 +++--
> 1 file
On 12/11/20 12:39 PM, Vladimir Sementsov-Ogievskiy wrote:
> Calculation of sum may theoretically overflow, so use 64bit type and
> add some good assertions.
>
> Use int64_t constantly.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> block/io.c | 8 ++--
> 1 file changed, 6 insertion
On 1/21/21 2:23 AM, dje--- via wrote:
> Signed-off-by: Doug Evans
> ---
Rather light on the commit message description. The one-line summary
does a good job of saying "what" the commit does, but the rest of the
commit body should say "why" the commit is worthwhile, rather than being
silent.
>
On 1/21/21 12:51 PM, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Provide a simple way to see if there's currently a migration blocker in
> operation:
>
> $ ./x86_64-softmmu/qemu-system-x86_64 -nographic -M pc,usb=on -chardev
> null,id=n -device usb-serial,chardev=n
On 1/21/21 9:07 PM, Richard Henderson wrote:
> On 1/12/21 11:54 AM, Philippe Mathieu-Daudé wrote:
>> Based-on: <20210112184156.2014305-1-f4...@amsat.org>
>> "decodetree: Allow 'dot' in opcode names"
>
> I'm still unconvinced about this. I've reviewed the code without regard to
> the
>
Added Namespace Multi-path I/O and Namespace Sharing Capabilities (NMIC)
field to support shared namespace from controller(s).
This field is in Identify Namespace data structure in [30].
Signed-off-by: Minwoo Im
---
include/block/nvme.h | 4
1 file changed, 4 insertions(+)
diff --git a/in
We have nvme-subsys and nvme devices mapped together. To support
multi-controller scheme to this setup, controller identifier(id) has to
be managed. Earlier, cntlid(controller id) used to be always 0 because
we didn't have any subsystem scheme that controller id matters.
This patch introduced 'c
Hi Peter,
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Convert the SSYS code in the Stellaris boards (which encapsulates the
> system registers) to a proper QOM device. This will provide us with
> somewhere to put the output Clock whose frequency depends on the
> setting of the PLL configuration re
Added Controller Multi-path I/O and Namespace Sharing Capabilities
(CMIC) field to support multi-controller in the following patches.
This field is in Identify Controller data structure in [76].
Signed-off-by: Minwoo Im
---
include/block/nvme.h | 4
1 file changed, 4 insertions(+)
diff --
nvme-ns device is registered to a nvme controller device during the
initialization in nvme_register_namespace() in case that 'bus' property
is given which means it's mapped to a single controller.
This patch introduced a new property 'subsys' just like the controller
device instance did to map a n
On 1/21/21 8:06 PM, Peter Maydell wrote:
> The old-style convenience function cmsdk_apb_timer_create() for
> creating CMSDK_APB_TIMER objects is used in only two places in
> mps2.c. Most of the rest of the code in that file uses the new
> "initialize in place" coding style.
>
> We want to connect
Hello,
This series is fourth series for the support of NVMe subsystem scheme
with multi-controller and namespace sharing in a subsystem.
This time, I've removed 'detached' scheme introduced in the previous
series out of this series to focus on subsystem scheme in ths series.
The attach/detach sch
To support multi-path in QEMU NVMe device model, We need to have NVMe
subsystem hierarchy to map controllers and namespaces to a NVMe
subsystem.
This patch introduced a simple nvme-subsys device model. The subsystem
will be prepared with subsystem NQN with provided in
nvme-subsys device:
ex)
nvme controller(nvme) can be mapped to a NVMe subsystem(nvme-subsys).
This patch maps a controller to a subsystem by adding a parameter
'subsys' to the nvme device.
To map a controller to a subsystem, we need to put nvme-subsys first and
then maps the subsystem to the controller:
-device nvme-s
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Remove all the code that sets frequency properties on the CMSDK
> timer, dualtimer and watchdog devices and on the ARMSSE SoC device:
> these properties are unused now that the devices rely on their Clock
> inputs instead.
>
> Signed-off-by: Peter Maydell
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Now no users are setting the frq properties on the CMSDK timer,
"Now that no ..."? No clue, double "no*" sounds odd to me :)
> dualtimer, watchdog or ARMSSE SoC devices, we can remove the
> properties and the struct fields that back them.
>
> Signed-off
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Now that the CMSDK APB watchdog uses its Clock input, it will
> correctly respond when the system clock frequency is changed using
> the RCC register on in the Stellaris board system registers. Test
> that when the RCC register is written it causes the wa
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Use the MAINCLK Clock input to set the system_clock_scale variable
> rather than using the mainclk_frq property.
>
> Signed-off-by: Peter Maydell
> ---
> At some point we should make the SysTick take a Clock itself so
> that we can get rid of the system_
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Switch the CMSDK APB watchdog device over to using its Clock input;
> the wdogclk_frq property is now ignored.
>
> Signed-off-by: Peter Maydell
> ---
> hw/watchdog/cmsdk-apb-watchdog.c | 18 ++
> 1 file changed, 14 insertions(+), 4 delet
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Switch the CMSDK APB timer device over to using its Clock input; the
> pclk-frq property is now ignored.
>
> Signed-off-by: Peter Maydell
> ---
> hw/timer/cmsdk-apb-timer.c | 18 ++
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
>
On 12/11/20 12:39 PM, Vladimir Sementsov-Ogievskiy wrote:
> Actually, we can't extend the io vector in all cases. Handle possible
> MAX_IOV and size_t overflows.
>
> For now add assertion to callers (actually they rely on success anyway)
> and fix them in the following patch.
>
> Add also some ad
Hi Peter,
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create and connect the Clock input for the watchdog device on the
> Stellaris boards. Because the Stellaris boards model the ability to
> change the clock rate by programming PLL registers, we have to create
> an output Clock on the ssys_state
On 1/21/21 8:06 PM, Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_DUALTIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the pclk-frq
> property to using the Clock once all the use
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create and connect the two clocks needed by the ARMSSE.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/mps2-tz.c | 13 +
> 1 file changed, 13 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create and connect the two clocks needed by the ARMSSE.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/musca.c | 12
> 1 file changed, 12 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create a fixed-frequency Clock object to be the SYSCLK, and wire it
> up to the devices that require it.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/mps2.c | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 01/15/21 11:24, Gerd Hoffmann wrote:
> qemu sends various state info like current cursor shape to newly connected
> clients in response to a set_encoding message. This is not correct according
> to the rfb spec. Send that information in response to a full (incremental=0)
> framebuffer update r
On 1/20/21 5:25 AM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
The default "alabaster" sphinx theme has a couple shortcomings:
- the navbar moves along the page
- the search bar is not always at the same place
- it lacks some contrast and colours
The "rtd" theme from readthedoc
On Thu, Jan 21, 2021 at 3:29 PM Peter Lieven wrote:
>
> Am 21.01.21 um 20:42 schrieb Jason Dillaman:
> > On Wed, Jan 20, 2021 at 6:01 PM Peter Lieven wrote:
> >>
> >>> Am 19.01.2021 um 15:20 schrieb Jason Dillaman :
> >>>
> >>> On Tue, Jan 19, 2021 at 4:36 AM Peter Lieven wrote:
> > Am 18.0
On 1/21/21 3:28 PM, Thomas Huth wrote:
On 21/01/2021 19.13, Daniel P. Berrangé wrote:
On Thu, Jan 21, 2021 at 03:05:43PM -0300, Wainer dos Santos Moschetta
wrote:
Hi,
On 1/21/21 7:08 AM, Thomas Huth wrote:
On 10/01/2021 17.27, Philippe Mathieu-Daudé wrote:
Split the current GCC build-tci j
On Thu, Jan 14, 2021 at 02:05:06PM +, Stefan Hajnoczi wrote:
> On Mon, Jan 04, 2021 at 04:02:26PM -0500, Eduardo Habkost wrote:
> > Is anybody already going to merge this? If not, I can merge it.
>
> Great, thank you for merging it, Eduardo!
I had just queued the patches, but I will be able
Hi Doug
On Fri, Jan 22, 2021 at 12:29 AM Doug Evans wrote:
>
> On Thu, Jan 21, 2021 at 1:41 AM Marc-André Lureau
> wrote:
>>
>> Hi Doug,
>>
>> On Thu, Jan 21, 2021 at 12:24 PM dje--- via wrote:
>> >
>> > Hi. This patchset takes the original patch from Maxim,
>> > https://www.mail-archive.com/q
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create two input clocks on the ARMSSE devices, one for the normal
> MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the
> appropriate devices. The old property-based clock frequency setting
> will remain in place until conversion is complete.
Am 21.01.21 um 20:42 schrieb Jason Dillaman:
> On Wed, Jan 20, 2021 at 6:01 PM Peter Lieven wrote:
>>
>>> Am 19.01.2021 um 15:20 schrieb Jason Dillaman :
>>>
>>> On Tue, Jan 19, 2021 at 4:36 AM Peter Lieven wrote:
> Am 18.01.21 um 23:33 schrieb Jason Dillaman:
> On Fri, Jan 15, 2021 at 1
On Thu, Jan 21, 2021 at 1:41 AM Marc-André Lureau <
marcandre.lur...@gmail.com> wrote:
> Hi Doug,
>
> On Thu, Jan 21, 2021 at 12:24 PM dje--- via wrote:
> >
> > Hi. This patchset takes the original patch from Maxim,
> > https://www.mail-archive.com/qemu-devel@nongnu.org/msg569573.html
> > and upd
On 1/21/21 8:06 PM, Peter Maydell wrote:
> While we transition the ARMSSE code from integer properties
> specifying clock frequencies to Clock objects, we want to have the
> device provide both at once. We want the final name of the main
> input Clock to be "MAINCLK", following the hardware name.
On 1/21/21 8:06 PM, Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_TIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the
> wdogclk-frq property to using the Clock once all the user
On 1/21/21 8:06 PM, Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_TIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the pclk-frq
> property to using the Clock once all the users o
On 1/21/21 8:06 PM, Peter Maydell wrote:
> The state struct for the CMSDK APB timer device doesn't follow our
> usual naming convention of camelcase -- "CMSDK" and "APB" are both
> acronyms, but "TIMER" is not so should not be all-uppercase.
> Globally rename the struct to "CMSDKAPBTimer" (bringing
* Alex Williamson (alex.william...@redhat.com) wrote:
> On Thu, 21 Jan 2021 18:51:13 +
> "Dr. David Alan Gilbert (git)" wrote:
>
> > From: "Dr. David Alan Gilbert"
> >
> > Provide a simple way to see if there's currently a migration blocker in
> > operation:
> >
> > $ ./x86_64-softmmu/qemu
On 1/21/21 10:09 AM, BALATON Zoltan wrote:
> On Wed, 20 Jan 2021, BALATON Zoltan wrote:
>> On Tue, 19 Jan 2021, Richard Henderson wrote:
>>> My recent change for caching tcg constants has, in a number of cases,
>>> overflowed the statically allocated array of temporaries. Change to
>>> dynamic all
On Thu, Dec 10, 2020 at 12:51 PM Stefan Hajnoczi wrote:
>
> On Wed, Dec 09, 2020 at 06:08:14PM +0100, Eugenio Perez Martin wrote:
> > On Mon, Dec 7, 2020 at 6:42 PM Stefan Hajnoczi wrote:
> > > On Fri, Nov 20, 2020 at 07:50:45PM +0100, Eugenio Pérez wrote:
> > > > +{
> > > > +struct vhost_vri
On Wed, 20 Jan 2021, BALATON Zoltan wrote:
On Tue, 19 Jan 2021, Richard Henderson wrote:
My recent change for caching tcg constants has, in a number of cases,
overflowed the statically allocated array of temporaries. Change to
dynamic allocation.
This seems to work for me so
Tested-by: BALAT
On 1/12/21 11:54 AM, Philippe Mathieu-Daudé wrote:
> Based-on: <20210112184156.2014305-1-f4...@amsat.org>
> "decodetree: Allow 'dot' in opcode names"
I'm still unconvinced about this. I've reviewed the code without regard to the
spelling in the decodetree files.
r~
On Thu, 21 Jan 2021 18:51:13 +
"Dr. David Alan Gilbert (git)" wrote:
> From: "Dr. David Alan Gilbert"
>
> Provide a simple way to see if there's currently a migration blocker in
> operation:
>
> $ ./x86_64-softmmu/qemu-system-x86_64 -nographic -M pc,usb=on -chardev
> null,id=n -device usb
On 21.01.21 21:01, Alexander Graf wrote:
> On 21.01.21 19:47, Richard Henderson wrote:
>> From: Roman Bolshakov
>>
>> Pages can't be both write and executable at the same time on Apple
>> Silicon. macOS provides public API to switch write protection [1] for
>> JIT applications, like TCG.
>>
>> 1
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Convert the following opcodes to decodetree:
>
> - MULT.G - multiply 32-bit signed integers
> - MULTU.G - multiply 32-bit unsigned integers
> - DMULT.G - multiply 64-bit signed integers
> - DMULTU.G - multiply 64-bit unsigned integers
>
> Now t
On 21.01.21 19:47, Richard Henderson wrote:
> From: Roman Bolshakov
>
> Pages can't be both write and executable at the same time on Apple
> Silicon. macOS provides public API to switch write protection [1] for
> JIT applications, like TCG.
>
> 1.
> https://developer.apple.com/documentation/app
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Convert the following opcodes to decodetree:
>
> - MOD.G - mod 32-bit signed integers
> - MODU.G - mod 32-bit unsigned integers
> - DMOD.G - mod 64-bit signed integers
> - DMODU.G - mod 64-bit unsigned integers
>
> Signed-off-by: Philippe Mathi
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
> (divide 64-bit unsigned integers) opcodes to decodetree.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/godson2.decode| 2 ++
> target/mips/loong-ext.decode |
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Add a simple test of the CMSDK APB timer, since we're about to do
> some refactoring of how it is clocked.
>
> Signed-off-by: Peter Maydell
> ---
> tests/qtest/cmsdk-apb-timer-test.c | 76 ++
> MAINTAINERS
On 1/12/21 11:54 AM, Philippe Mathieu-Daudé wrote:
> There is no issue having multiple enum declarations with
> the same value. As we are going to remove the OPC_MULT_G_2E
> definition in few commits, restore the OPC_ADDUH_QB_DSP and
> OPC_MUL_PH_DSP definitions and use them where they belong.
>
>
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
> 'is_double' argument so it can generate DIV.G (divide 32-bit
> signed integers).
>
> With this commit we explicit the template used to generate
> opcode for 32/64-bit word variants.
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Introduce decode_loongson() to decode all Loongson vendor
> specific opcodes. Start converting a single opcode: DDIV.G
> (divide 64-bit signed integers).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 1 +
>
21.01.2021 04:26, Eric Blake wrote:
On 11/18/20 12:04 PM, Vladimir Sementsov-Ogievskiy wrote:
Check that cancel doesn't wait for 10s of nbd reconnect timeout.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/264 | 38 ++
tests/qemu-i
On 1/10/21 8:51 AM, Alexey Baturo wrote:
> Signed-off-by: Alexey Baturo
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson
r~
On Wed, Jan 20, 2021 at 6:01 PM Peter Lieven wrote:
>
>
> > Am 19.01.2021 um 15:20 schrieb Jason Dillaman :
> >
> > On Tue, Jan 19, 2021 at 4:36 AM Peter Lieven wrote:
> >>> Am 18.01.21 um 23:33 schrieb Jason Dillaman:
> >>> On Fri, Jan 15, 2021 at 10:39 AM Peter Lieven wrote:
> Am 15.01.2
21.01.2021 05:14, Eric Blake wrote:
On 11/18/20 12:04 PM, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
The problem
Assume we have mirror job with nbd target node with enabled reconnect.
Connection failed. So, all current requests to nbd node are waiting for
nbd driver to reconnect. And they wil
On 1/10/21 8:51 AM, Alexey Baturo wrote:
> Signed-off-by: Alexey Baturo
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 3 +++
> target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
> target/riscv
21.01.2021 05:21, Eric Blake wrote:
On 1/20/21 7:28 PM, Eric Blake wrote:
On 11/18/20 12:04 PM, Vladimir Sementsov-Ogievskiy wrote:
Check that cancel doesn't wait for 10s of nbd reconnect timeout.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/264 | 21 ++
21.01.2021 02:15, Eric Blake wrote:
On 11/18/20 12:04 PM, Vladimir Sementsov-Ogievskiy wrote:
We are going to cancel in-flight requests on mirror nbd target on job
cancel. Still nbd is often used not directly but as raw-format child.
So, add pass-through handler here.
Signed-off-by: Vladimir Se
On 1/12/21 9:13 PM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
> interfaces for immediate shift instructions.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-
Now no users are setting the frq properties on the CMSDK timer,
dualtimer, watchdog or ARMSSE SoC devices, we can remove the
properties and the struct fields that back them.
Signed-off-by: Peter Maydell
---
include/hw/arm/armsse.h | 2 --
include/hw/timer/cmsdk-apb-dualtimer.h
On Wed, 20 Jan 2021 at 20:44, Richard Henderson
wrote:
>
> This was defined at some point before ARMv8.4, and will
> shortly be used by new processor descriptions.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
Applied to target-arm.next, thanks.
-- PMM
On Wed, 20 Jan 2021 at 03:17, Richard Henderson
wrote:
>
> Only define the register if it exists for the cpu.
>
> Signed-off-by: Richard Henderson
> ---
>
> I've pulled this out of a largely defunct 2019 branch. This will
> be required for the cortex-a76, which only implements aa32 at el0.
>
> T
21.01.2021 04:17, Eric Blake wrote:
On 11/18/20 12:04 PM, Vladimir Sementsov-Ogievskiy wrote:
We are going to add more test cases, so use the library supporting test
cases.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/264 | 93 ++
Convert the SSYS code in the Stellaris boards (which encapsulates the
system registers) to a proper QOM device. This will provide us with
somewhere to put the output Clock whose frequency depends on the
setting of the PLL configuration registers.
This is a migration compatibility break for lm3s81
Use the MAINCLK Clock input to set the system_clock_scale variable
rather than using the mainclk_frq property.
Signed-off-by: Peter Maydell
---
At some point we should make the SysTick take a Clock itself so
that we can get rid of the system_clock_scale global entirely.
(In fact we want two Clock
Switch the CMSDK APB watchdog device over to using its Clock input;
the wdogclk_frq property is now ignored.
Signed-off-by: Peter Maydell
---
hw/watchdog/cmsdk-apb-watchdog.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c
Create a fixed-frequency Clock object to be the SYSCLK, and wire it
up to the devices that require it.
Signed-off-by: Peter Maydell
---
hw/arm/mps2.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index f762d1b46af..cd1c215f941 100644
--- a/hw/arm/mps2
Now that the watchdog device uses its Clock input rather than being
passed the value of system_clock_scale at creation time, we can
remove the hack where we reset the STELLARIS_SYS at board creation
time to force it to set system_clock_scale. Instead it will be reset
at the usual point in startup
Switch the CMSDK APB timer device over to using its Clock input; the
pclk-frq property is now ignored.
Signed-off-by: Peter Maydell
---
hw/timer/cmsdk-apb-timer.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-a
The old-style convenience function cmsdk_apb_timer_create() for
creating CMSDK_APB_TIMER objects is used in only two places in
mps2.c. Most of the rest of the code in that file uses the new
"initialize in place" coding style.
We want to connect up a Clock object which should be done between the
o
While we transition the ARMSSE code from integer properties
specifying clock frequencies to Clock objects, we want to have the
device provide both at once. We want the final name of the main
input Clock to be "MAINCLK", following the hardware name.
Unfortunately creating an input Clock with a name
Remove all the code that sets frequency properties on the CMSDK
timer, dualtimer and watchdog devices and on the ARMSSE SoC device:
these properties are unused now that the devices rely on their Clock
inputs instead.
Signed-off-by: Peter Maydell
---
hw/arm/armsse.c| 7 ---
hw/arm/mps2-tz
Create and connect the two clocks needed by the ARMSSE.
Signed-off-by: Peter Maydell
---
hw/arm/mps2-tz.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 6a9eed9022a..7acdf490f28 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@
Create and connect the Clock input for the watchdog device on the
Stellaris boards. Because the Stellaris boards model the ability to
change the clock rate by programming PLL registers, we have to create
an output Clock on the ssys_state device and wire it up to the
watchdog.
Note that the old co
Now that the CMSDK APB watchdog uses its Clock input, it will
correctly respond when the system clock frequency is changed using
the RCC register on in the Stellaris board system registers. Test
that when the RCC register is written it causes the watchdog timer to
change speed.
Signed-off-by: Pet
Add a simple test of the CMSDK watchdog, since we're about to do some
refactoring of how it is clocked.
Signed-off-by: Peter Maydell
---
tests/qtest/cmsdk-apb-watchdog-test.c | 80 +++
MAINTAINERS | 1 +
tests/qtest/meson.build |
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