On 03/01/2021 02.09, BALATON Zoltan via wrote:
All machines that select SERIAL also select PPC4XX so we can just add
this common dependency there once.
Signed-off-by: BALATON Zoltan
---
hw/ppc/Kconfig | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/ppc/Kconfig b/hw
On Fri, 1 Jan 2021, Peter Maydell wrote:
On Thu, 31 Dec 2020 at 20:55, BALATON Zoltan wrote:
The SoC is called 460EX (despite having a PPC 440 core not 460 one) but I
think you've looked at the right data sheet and it's just a typo. I also
don't know how the board is wired so I think in this ca
Reviewed-by: Huacai Chen
On Sat, Jan 2, 2021 at 7:17 AM Philippe Mathieu-Daudé wrote:
>
> On 1/1/21 9:42 PM, Philippe Mathieu-Daudé wrote:
> > On 12/15/20 7:45 AM, Jiaxun Yang wrote:
> >> It's useful for bootloader to do IO opreations.
> >>
> >> Signed-off-by: Jiaxun Yang
> >> ---
> >> target/
Reviewed-by: Huacai Chen
On Fri, Jan 1, 2021 at 6:49 AM Philippe Mathieu-Daudé wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/bonito.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
> index 0634f328
Reviewed-by: Huacai Chen
On Fri, Jan 1, 2021 at 6:49 AM Philippe Mathieu-Daudé wrote:
>
> Replace pci_set_byte(PCI_INTERRUPT_PIN) by
> pci_config_set_interrupt_pin().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/bonito.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-
Reviewed-by: Huacai Chen
On Fri, Jan 1, 2021 at 6:49 AM Philippe Mathieu-Daudé wrote:
>
> Use the PCI_DEVFN() macro to replace the '0x28' magic value,
> this way it is clearer we access PCI function #0 of slot #5.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/bonito.c | 2 +-
>
Reviewed-by: Huacai Chen
On Fri, Jan 1, 2021 at 6:49 AM Philippe Mathieu-Daudé wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/bonito.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
> index a99eced0657..0634f3289c
The trace event for pci_host_config_write() was also using the trace
event for read. Add corresponding trace and correct this.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 2 +-
hw/ppc/trace-events | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_pc
Dependency on FDT_PPC was added in commit b0048f76095
("hw/ppc/Kconfig: Only select FDT helper for machines using it") but
it does not seem to be really necessary so remove it again.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/Kconfig | 1 -
1 file changed, 1 de
The code mapping all PCI interrupts to a single CPU IRQ works but is
not trivial so document it in a comment.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index e
This fixes a long standing issue with MorphOS booting on sam460ex
which turns out to be because of suspicious values written to PCI
config address that apparently works on real machine but caused wrong
access on this device model. This replaces a previous work around for
this with a better fix that
All machines that select SERIAL also select PPC4XX so we can just add
this common dependency there once.
Signed-off-by: BALATON Zoltan
---
hw/ppc/Kconfig | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index dd86e664d2..8548f42b0d 100644
--
So this is v3 of a series that started to fix a potential problem with
irq mapping in pci440_pcix (used by sam460ex) that got some other
fixes along the way as by-products. But it turns out the irq issue
this was trying to fix is not really a problem so finally we just
update the comment for now do
On Mon, Dec 14, 2020 at 6:03 AM Richard Henderson
wrote:
>
> Now that all native tcg hosts support splitwx,
> make this pointer const.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c.inc | 3 +--
> tcg/arm/tcg-target.c.inc | 3 +--
> tcg/i386/tcg-target.c.inc| 3 +--
On Mon, Dec 14, 2020 at 6:03 AM Richard Henderson
wrote:
>
> Now that all native tcg hosts support splitwx,
> make this pointer const.
>
> Signed-off-by: Richard Henderson
> ---
> include/tcg/tcg.h| 2 +-
> tcg/tcg.c| 2 +-
> tcg/aarch64/tcg-target.c.inc | 3 +--
>
On Mon, Dec 14, 2020 at 6:03 AM Richard Henderson
wrote:
>
> Now that all native tcg hosts support splitwx, remove the define.
> Replace the one use with a test for CONFIG_TCG_INTERPRETER.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.h | 1 -
> tcg/arm/tcg-target.h
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> include/tcg/tcg.h | 13 +
> 1 file changed, 13 insertions(+)
Reviewed-by: Joelle van Dyne
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tci.c | 60 +++
> 1 file changed, 34 insertions(+), 26 deletions(-)
Reviewed-by: Joelle van Dyne
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> include/disas/dis-asm.h | 4 ++--
> disas.c | 4 +---
> disas/capstone.c| 2 +-
> 3 files changed, 4 insertions(+), 6 deletions(-)
Reviewed-by: Joelle van Dyne
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.h | 2 +-
> tcg/aarch64/tcg-target.c.inc | 57
> 2 files changed, 33 insertions(+), 26 deletions(-)
Reviewed-by: Joelle van Dyne
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> A typo generated a branch-and-link insn instead of plain branch.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Joelle van Dyne
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/i386/tcg-target.h | 2 +-
> tcg/i386/tcg-target.c.inc | 20 +++-
> 2 files changed, 12 insertions(+), 10 deletions(-)
Reviewed-by: Joelle van Dyne
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> This produces a small pc-relative displacement within the
> generated code to the TB structure that preceeds it.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/cpu-exec.c | 35 ++-
> tcg/tcg-op.c
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> There is nothing within the translators that ought to be
> changing the TranslationBlock data, so make it const.
>
> This does not actually use the read-only copy of the
> data structure that exists within the rx region.
>
> Signed-off-b
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> We cannot use a real temp file, because we would need to find
> a filesystem that does not have noexec enabled. However, a
> memfd is not associated with any filesystem.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/translate
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Report better error messages than just "could not allocate".
> Let alloc_code_gen_buffer set ctx->code_gen_buffer_size
> and ctx->code_gen_buffer, and simply return bool.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/translate
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> There is nothing within the translators that ought to be
> changing the TranslationBlock data, so make it const.
>
> This does not actually use the read-only copy of the
> data structure that exists within the rx region.
>
> Signed-off-b
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> We must change all targets at once, since all must match
> the declaration in tcg.c.
>
> Signed-off-by: Richard Henderson
> ---
> include/tcg/tcg.h| 2 +-
> tcg/tcg.c| 10 +-
> tcg/aarch64/tcg-t
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Pass both rx and rw addresses to tb_target_set_jmp_target.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.h | 2 +-
> tcg/arm/tcg-target.h | 2 +-
> tcg/i386/tcg-target.h| 6 +++---
> tcg/mip
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Simplify the arguments to always use s->code_ptr instead of
> take it as an argument. That makes it easy to ensure that
> the value_ptr is always the rx version.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg.c |
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> We must change all targets at once, since all must match
> the declaration in tcg.c.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg.c| 2 +-
> tcg/aarch64/tcg-target.c.inc | 2 +-
> tcg/arm/tcg-target.c.inc
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Change TCGLabel.u.value_ptr to const, and initialize it with
> tcg_splitwx_to_rx. Propagate const through tcg/host/ only
> as far as needed to avoid errors from the value_ptr change.
>
> Signed-off-by: Richard Henderson
> ---
> includ
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Add two helper functions, using a global variable to hold
> the displacement. The displacement is currently always 0,
> so no change in behaviour.
>
> Begin using the functions in tcg common code only.
>
> Signed-off-by: Richard Henders
I see you didn't touch cpu_loop_exit() and I'm curious how async
interrupts are handled. Have you tested this and it works i.e. booting
Windows 7 or Ubuntu 20.04? Also I've seen do_tb_phys_invalidate()
called both from code generation context (write unlocked) and
execution context (write locked), h
On 02/01/21 14:25, Peter Maydell wrote:
Question to Paolo -- it seems pretty fragile to have to explicitly
list "these source files need these extra CFLAGS" in half a dozen
meson.build files, because it's pretty non-obvious that adding
eg '#include "block/nbd.h"' to a .c file means that you also
On Sat, Jan 02, 2021 at 03:21:02PM +0300, Roman Bolshakov wrote:
> Pages can't be both write and executable at the same time on Apple
> Silicon. macOS provides public API to switch write protection [1] for
> JIT applications, like TCG.
>
> 1.
> https://developer.apple.com/documentation/apple_sili
ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in
macOS 11.0 - Use -[NSWorkspace openURL:] instead.
[-Wdeprecated-declarations]
if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
^
/Library/Devel
Hello,
i can't start any system if i use virgl. I get the following error:
qemu-x86_64: ../ui/console.c:1791: dpy_gl_ctx_create: Assertion
`con->gl' failed.
./and.sh: line 27: 3337167 Aborted qemu-x86_64 -m 4096
-smp cores=4,sockets=1 -cpu host -machine pc-q35-4.0,accel=kvm -de
On Thu, Dec 31, 2020 at 5:04 PM Bin Meng wrote:
>
> From: Bin Meng
>
> commit f6fb1f9b319f ("sdcard: Correct CRC16 offset in sd_function_switch()")
> changed the 16-bit CRC to be stored at offset 64. In fact, this CRC
> calculation is completely wrong. From the original codes, it wants
> to calcu
Hello,
i can't start any system if i use virgl. I get the following error:
qemu-x86_64: ../ui/console.c:1791: dpy_gl_ctx_create: Assertion
`con->gl' failed.
./and.sh: line 27: 3337167 Aborted qemu-x86_64 -m 4096
-smp cores=4,sockets=1 -cpu host -machine pc-q35-4.0,accel=kvm -de
Hi Bin,
On Sat, Jan 2, 2021 at 6:46 PM Bin Meng wrote:
>
> Hi Pragnesh,
>
> On Sat, Jan 2, 2021 at 8:27 PM Pragnesh Patel
> wrote:
> >
> > Hi BIn,
> >
> > 1) Please rebase this series on master.
>
> I remember I rebased it on master already.
It shows below,
pragneshp:sifive-qemu$ git am hw-ri
On Thu, Dec 31, 2020 at 5:04 PM Bin Meng wrote:
>
> From: Bin Meng
>
> After the card is put into SPI mode, CRC check for all commands
> including CMD0 will be done according to CMD59 setting. But this
> command is currently unimplemented. Simply allow the decoding of
> CMD59, but the CRC check i
Hi BIn,
1) Please rebase this series on master.
2) When i tried to boot from SD card image it shows below,
pragneshp:sifive-qemu$ ./build/riscv64-softmmu/qemu-system-riscv64 -M
sifive_u,msel=11 -m 4G -nographic -bios
~/opensource/u-boot/spl/u-boot-spl.bin -device
sd-card,spi=true,drive=mycard -d
On Thu, Dec 31, 2020 at 5:04 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Per the "Physical Layer Specification Version 8.00" chapter 7.5.1,
> "Command/Response", there is a minimum 8 clock cycles (Ncr) before
> the card response shows up on the data out line. However current
> implementation jumps
On Sat, Jan 02, 2021 at 01:16:48PM +, Peter Maydell wrote:
> On Sat, 2 Jan 2021 at 12:52, Roman Bolshakov wrote:
> >
> > ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in
> > macOS 11.0 - Use -[NSWorkspace openURL:] instead.
> > [-Wdeprecated-declarations]
> >
On Sat, Jan 02, 2021 at 01:25:07PM +, Peter Maydell wrote:
> On Sat, 2 Jan 2021 at 12:54, Roman Bolshakov wrote:
> >
> > crypto/tlscreds.h includes GnuTLS headers if CONFIG_GNUTLS is set, but
> > GNUTLS_CFLAGS, that describe include path, are not propagated
> > transitively to all users of cry
On Sat, 2 Jan 2021, Peter Maydell wrote:
On Sat, 2 Jan 2021 at 11:22, BALATON Zoltan wrote:
I have similar code in the series I've just posted where I'm mapping
regions of serial devices. I did consider using set_enabled and
set_address but ended up with removing and adding regions because I'm
Hi Pragnesh,
On Sat, Jan 2, 2021 at 9:30 PM Pragnesh Patel wrote:
>
> Hi Bin,
>
> On Sat, Jan 2, 2021 at 6:46 PM Bin Meng wrote:
> >
> > Hi Pragnesh,
> >
> > On Sat, Jan 2, 2021 at 8:27 PM Pragnesh Patel
> > wrote:
> > >
> > > Hi BIn,
> > >
> > > 1) Please rebase this series on master.
> >
> >
On Sat, 2 Jan 2021 at 12:54, Roman Bolshakov wrote:
>
> crypto/tlscreds.h includes GnuTLS headers if CONFIG_GNUTLS is set, but
> GNUTLS_CFLAGS, that describe include path, are not propagated
> transitively to all users of crypto and build fails if GnuTLS headers
> reside in non-standard directory
On Sat, 2 Jan 2021 at 12:52, Roman Bolshakov wrote:
>
> ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in
> macOS 11.0 - Use -[NSWorkspace openURL:] instead.
> [-Wdeprecated-declarations]
> if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES
Hi Pragnesh,
On Sat, Jan 2, 2021 at 8:27 PM Pragnesh Patel wrote:
>
> Hi BIn,
>
> 1) Please rebase this series on master.
I remember I rebased it on master already.
>
> 2) When i tried to boot from SD card image it shows below,
>
> pragneshp:sifive-qemu$ ./build/riscv64-softmmu/qemu-system-risc
On Wed, 23 Dec 2020 at 21:27, Eduardo Habkost wrote:
>
> The following changes since commit a05f8ecd88f15273d033b6f044b850a8af84a5b8:
>
> Merge remote-tracking branch
> 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging
> (2020-12-18 11:12:35 +)
>
> are available in the Gi
On Sat, 2 Jan 2021 at 11:22, BALATON Zoltan wrote:
> I have similar code in the series I've just posted where I'm mapping
> regions of serial devices. I did consider using set_enabled and
> set_address but ended up with removing and adding regions because I'm not
> sure what happens if guest tries
crypto/tlscreds.h includes GnuTLS headers if CONFIG_GNUTLS is set, but
GNUTLS_CFLAGS, that describe include path, are not propagated
transitively to all users of crypto and build fails if GnuTLS headers
reside in non-standard directory (which is a case for homebrew on Apple
Silicon).
Signed-off-by
ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in
macOS 11.0 - Use -[NSWorkspace openURL:] instead.
[-Wdeprecated-declarations]
if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
^
/Library/Devel
ld64 is making PIE executables for 10.7 and above by default, as
documented in ld(1).
Reviewed-by: Cameron Esfahani
Signed-off-by: Roman Bolshakov
---
configure | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configure b/configure
index 881af4b6be..942e20dfe7 100755
--- a/configure
+++ b/
Patchew URL:
https://patchew.org/QEMU/20210102122101.39617-1-r.bolsha...@yadro.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210102122101.39617-1-r.bolsha...@yadro.com
Subject: [PATCH] tcg: Fix execution on App
Pages can't be both write and executable at the same time on Apple
Silicon. macOS provides public API to switch write protection [1] for
JIT applications, like TCG.
1.
https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon
Signed-off-by: Roman Bol
Add emulation of VT8231 south bridge ISA part based on the similar
VT82C686B but implemented in a separate subclass that holds the
differences while reusing parts that can be shared.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 152 ++
include
Move lines around so that object definitions become consecutive and
not scattered around. This brings functions belonging to an object
together so it's clearer what is defined and what parts belong to
which object.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 279 +++
Collect superio functionality and its controlling config registers
handling in an abstract VIA_SUPERIO class that is a subclass of
ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
abstract class.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 240
Similar to the SMBus io registers there is a power management io range
that is set via similar base address reg and enable bit. Some handling
of this was already there but with several problems: using the wrong
registers and bits, wrong size range, not acually updating mapping and
handling reset co
Remove unneeded variables and setting value to 0 on zero initialised
data and replace check for error with error_fatal. Rationalise loop
that sets PCI config header fields read only.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 20 ++--
1 file changed, 6 insertions(+), 1
Currently the ISA devices that are part of the VIA south bridge,
superio chip are wired up by board code. Move creation of these ISA
devices to the VIA ISA bridge model so that board code does not need
to access ISA bus. This also allows vt82c686b-superio to be made
internal to vt82c686 which allow
These are not used or not needed.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index d7ce15bf9f..02d6759c00 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c6
On Sat, 2 Jan 2021, Philippe Mathieu-Daudé wrote:
On 1/2/21 12:19 AM, Peter Maydell wrote:
On Fri, 1 Jan 2021 at 23:12, Philippe Mathieu-Daudé wrote:
Per the datasheet (Chapter 5.7.1. "PCI address regions"),
the PCIMAP register:
Map the 64Mbyte regions marked "PCI_Lo" in the CPU's memory m
These functions are memory region callbacks so we have to check
against relative address not the mapped address. Also reduce
indentation by returning early and log unimplemented accesses.
Additionally we remove separate index value from SuperIOConfig and
store the index at reg 0 which is reserved a
The VT8231 south bridge is very similar to VT82C686B but there are
some differences in register addresses and functionality, e.g. the
VT8231 only has one serial port. This commit adds VT8231_SUPERIO
subclass based on the abstract VIA_SUPERIO class to emulate the
superio part of VT8231.
Signed-off-
The base address of the SMBus io ports and its enabled status is set
by registers in the PCI config space but this was not correctly
emulated. Instead the SMBus registers were mapped on realize to the
base address set by a property to the address expected by fuloong2e
firmware.
Fix the base and co
Drop DPRINTF and use trace functions instead. Two debug messages about
unimplemented registers could be converted to qemu_log_mask() but in
reality all registers are currently unimplemented (we just store and
return values of writable regs but do nothing with them). As we
already trace register acc
In VIA super south bridge the io ranges of superio components
(parallel and serial ports and FDC) can be controlled by superio
config registers to set their base address and enable/disable them.
This is not easy to implement in QEMU because ISA emulation is only
designed to set io base address once
Hello,
This is an all in one series containing all the patches from my
previous part I and part II vt82c686b clean up series plus the end of
it to finally add vt8231 emulation that will be used by subsequent
ppc/pegasos2 emulation. I consider this finished for now and good
enough to get in also cl
The vt82c686b-pm model can be shared between VT82C686B and VT8231. The
only difference between the two is the device id in what we emulate so
make an abstract via-pm model by renaming appropriately and add types
for vt82c686b-pm and vt8231-pm based on it.
Signed-off-by: BALATON Zoltan
---
hw/isa
Rename local variable holding object state for readability and
consistency.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 02d6759c00..2633cfe7dc
There's no reason to suffix everything with _DEVICE when the names are
already unique without it and shorter names are more readable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 48 +++
1 file changed, 23
Use less confusing naming for superio config register handling related
parts that makes it clearer what belongs to this part.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 48 +++
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/
Remove legacy vt82c686b_pm_init() function and also rename
VT82C686B_PM type name to match other device names.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 18 --
hw/mips/fuloong2e.c | 5 -
include/hw/isa/vt82c686.h
Remove some unneded, empty code and set user_creatable to false
(besides being not implemented yet, so does nothing anyway) it's also
normally part of VIA south bridge chips so no need to confuse users
showing them these devices.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
The via-[am]c97 code is supposed to implement the audio part of VIA
south bridge chips so it is better placed under hw/audio/. Split it
off into a separate file.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/audio/meson.build | 1 +
hw/audio/via-ac97.c | 106 ++
The superio memory region holds the io space index/data registers used
to access the superio config registers that are implemented in struct
SuperIOConfig. To keep these related things together move the memory
region to SuperIOConfig and rename it accordingly.
Also remove the unused "data" member o
This is really the ISA bridge part so name the type accordingly.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 1be1169
These are legacy init functions that are just equivalent to directly
calling pci_create_simple so do that instead. Also rename objects to
lower case via-ac97 and via-mc97 matching naming of other devices.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 9 -
hw/mips/fuloong2e.c | 4 +++-
include/hw/isa/vt82c686.h | 3 +--
3 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 956732
These parts are common between VT82C686B and VT8231 so can be shared
in the future. Rename them to VIA prefix accordingly.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
On 1/2/21 11:44 AM, Philippe Mathieu-Daudé wrote:
> On 1/2/21 12:19 AM, Peter Maydell wrote:
>> On Fri, 1 Jan 2021 at 23:12, Philippe Mathieu-Daudé wrote:
>>>
>>> Per the datasheet (Chapter 5.7.1. "PCI address regions"),
>>> the PCIMAP register:
>>>
>>> Map the 64Mbyte regions marked "PCI_Lo" in
On 1/2/21 12:19 AM, Peter Maydell wrote:
> On Fri, 1 Jan 2021 at 23:12, Philippe Mathieu-Daudé wrote:
>>
>> Per the datasheet (Chapter 5.7.1. "PCI address regions"),
>> the PCIMAP register:
>>
>> Map the 64Mbyte regions marked "PCI_Lo" in the CPU's memory map,
>> each of which can be assigned
Hello,
While cleaning up my VIA south bridge patches I've found that with the
finished version I did not get interrupts. At the end I've found a
solution in a similar device (piix4) but I don't understand why that's
needed. Could someone please explain?
Here's what I had originally in board
On 25/12/2020 21.19, Richard Henderson wrote:
This emphasizes that we don't support s390, only 64-bit s390x hosts.
Signed-off-by: Richard Henderson
---
meson.build | 2 --
tcg/{s390 => s390x}/tcg-target-conset.h | 0
tcg/{s390 => s390x}/tcg-target-constr.h | 0
88 matches
Mail list logo
