On Sun, Dec 13, 2020 at 10:30:16PM +0100, Fabrice Fontaine wrote:
> USBDEVFS_GET_SPEED is used since version 5.2.0 and
> https://gitlab.com/qemu-project/qemu/-/commit/202d69a715a4b1824dcd7ec1683d027ed2bae6d3
> resulting in the following build failure with kernel < 5.0:
>
> ../hw/usb/host-libusb.c:
Hi Keqian, Peter,
On 2020/12/15 15:23, zhukeqian wrote:
On 2020/12/14 23:36, Peter Xu wrote:
On Mon, Dec 14, 2020 at 10:14:11AM +0800, zhukeqian wrote:
[...]
Though indeed I must confess I don't know how it worked in general when host
page size != target page size, at least for migration.
> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Wednesday, December 9, 2020 6:30 AM
> To: Jiangyifei
> Cc: qemu-devel@nongnu.org Developers ; open
> list:RISC-V ; Zhangxiaofeng (F)
> ; Sagar Karandikar
> ; open list:Overall ;
> libvir-l...@redhat.com; B
> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Wednesday, December 9, 2020 6:26 AM
> To: Jiangyifei
> Cc: qemu-devel@nongnu.org Developers ; open
> list:RISC-V ; Zhangxiaofeng (F)
> ; Sagar Karandikar
> ; open list:Overall ;
> libvir-l...@redhat.com; B
Hi, Dave.
Since qemu 6.0 is open and some patches of this series have been reviewed,
might you have time to continue reviewing rest of them ?
On 2020/10/25 10:29, Zheng Chuan wrote:
>
>
> On 2020/10/24 3:02, Dr. David Alan Gilbert wrote:
>> * Zheng Chuan (zhengch...@huawei.com) wrote:
>>>
>>>
On 2020/12/14 23:36, Peter Xu wrote:
> On Mon, Dec 14, 2020 at 10:14:11AM +0800, zhukeqian wrote:
>
> [...]
>
> Though indeed I must confess I don't know how it worked in general when
> host
> page size != target page size, at least for migration. For example, I
> believe
>>>
Keqian Zhu (2):
accel: kvm: Fix memory waste under mismatch page size
accel: kvm: Add aligment check for kvm_log_clear_one_slot
accel/kvm/kvm-all.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
--
2.23.0
The parameters start and size are transfered from QEMU memory
emulation layer. It can promise that they are TARGET_PAGE_SIZE
aligned. However, KVM needs they are qemu_real_page_size aligned.
Though no caller breaks this aligned requirement currently, we'd
better add an explicit check to avoid futu
> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Wednesday, December 9, 2020 6:22 AM
> To: Jiangyifei
> Cc: qemu-devel@nongnu.org Developers ; open
> list:RISC-V ; Zhangxiaofeng (F)
> ; Sagar Karandikar
> ; open list:Overall ;
> libvir-l...@redhat.com; B
> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Wednesday, December 9, 2020 6:19 AM
> To: Jiangyifei
> Cc: qemu-devel@nongnu.org Developers ; open
> list:RISC-V ; Zhangxiaofeng (F)
> ; Sagar Karandikar
> ; open list:Overall ;
> libvir-l...@redhat.com; B
When handle dirty log, we face qemu_real_host_page_size and
TARGET_PAGE_SIZE. The first one is the granule of KVM dirty
bitmap, and the second one is the granule of QEMU dirty bitmap.
Generally speaking, qemu_real_host_page_size >= TARGET_PAGE_SIZE,
so misuse TARGET_PAGE_SIZE to init kvmslot dirty
This patch addresses this issue:
When accessing a volume on an NFS filesystem without supporting the file lock,
tools, like qemu-img, will complain "Failed to lock byte 100".
In the original code, the qemu_has_ofd_lock will test the lock on the
"/dev/null" pseudo-file. Actually, the file.locking i
Replace embedded binary with generated code.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c| 17 ++---
hw/mips/fuloong2e.c | 28
hw/mips/malta.c | 41 ++---
3 files changed, 16 insertions(+), 70 deletions(-)
d
It's useful for bootloader to do IO opreations.
Signed-off-by: Jiaxun Yang
---
target/mips/addr.c | 10 ++
target/mips/cpu.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/target/mips/addr.c b/target/mips/addr.c
index 27a6036c45..86f1c129c9 100644
--- a/target/mips/addr.c
+++
Translate embedded assembly into IO writes which is more
readable.
Also hardcode cm_base at boot time instead of reading from CP0.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 45 -
1 file changed, 12 insertions(+), 33 deletions(-)
diff --git a/
Translate embedded assembly into IO writes which is more
readable.
Signed-off-by: Jiaxun Yang
---
hw/mips/malta.c | 68 ++---
1 file changed, 19 insertions(+), 49 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index ffd67b8293..2799bc36c7
Add a bootloader helper to generate simple bootloaders for kernel.
It can help us reduce inline hex hack and also keep MIPS release 6
compatibility easier.
Signed-off-by: Jiaxun Yang
---
hw/mips/bootloader.c | 157 +++
hw/mips/meson.build | 2 +-
It will signed extend vaddr properly.
Signed-off-by: Jiaxun Yang
---
hw/mips/fuloong2e.c | 24 +-
hw/mips/malta.c | 62 ++---
2 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
ind
So it will sign extend adresses properly.
Signed-off-by: Jiaxun Yang
---
hw/mips/malta.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 7db009a3e9..1fbb8a3220 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1302,9 +1302,9 @@
Address should be unsigned anyway, otherwise it may carry
calculations wrongly.
Signed-off-by: Jiaxun Yang
---
hw/mips/fuloong2e.c | 12 ++--
hw/mips/malta.c | 22 +++---
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fu
v2:
A big reconstruction. rewrite helpers with CPU feature and sepreate
changesets.
Jiaxun Yang (8):
hw/mips: Make bootloader addresses unsgined
hw/mips/malta: Use address translation helper to calculate
bootloader_run_addr
hw/mips: Use address translation helper to handle ENVP_ADDR
hw
Same here on macOS 11.0.1 when specifying accel=hvf. Crash report is
attached.
$ qemu-system-x86_64 -machine accel=hvf -smp 2 -m 2G -hda current.qcow -boot d
-cdrom ubuntu-18.04.5-desktop-amd64.iso
qemu-system-x86_64: Error: HV_ERROR
[1]2912 abort qemu-system-x86_64 -machine accel=hvf
Hi, Daniel
Thanks for your reply.
I have just ended my trip, sorry for my late response.
I will send out the v4.
Daniel P. Berrangé 于2020年12月11日周五 上午12:55写道：
>
> On Fri, Dec 11, 2020 at 12:38:19AM +0800, Li Feng wrote:
> > This patch addresses this issue:
> > When accessing a volume on an NFS fil
Hi, Philippe,
On Mon, Dec 14, 2020 at 9:49 PM Philippe Mathieu-Daudé wrote:
>
> On 12/14/20 3:37 AM, Huacai Chen wrote:
> > Hi, Philippe,
> >
> > On Mon, Dec 14, 2020 at 7:09 AM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 12/13/20 11:17 PM, Philippe Mathieu-Daudé wrote:
> >>> On 12/11/20 12:
- Original Message -
> Hi!
>
> 07.12.2020, 08:52, "Jason Wang" :
> > On 2020/11/9 上午7:59, Alexey Kirillov wrote:
> >> +#ifdef CONFIG_SLIRP
> >> + case NET_BACKEND_USER: {
> >> + size_t len = strchr(ni->u.user.net, '/') - ni->u.user.net;
> >> + char *net = g_strndup(ni->u.user.net, l
> -Original Message-
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Tuesday, December 15, 2020 12:20 AM
> To: ganqixin
> Cc: qemu-arm ; QEMU Developers
> ; Chenqun (kuhn)
> ; Zhanghailiang
> ; Euler Robot
> ; Beniamino Galvani
> Subject: Re: [PATCH 1/7] allwinner-a10-pit:
Should qemu-options.hx be updated?
-j
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> Plumb the value through to alloc_code_gen_buffer. This is not
> supported by any os or tcg backend, so for now enabling it will
> result in an error.
>
> Signed-off-by: Richard Henderson
> ---
>
OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.
Signed-off-by: Alistair Francis
---
include/hw/riscv/opentitan.h | 23 +++---
hw/riscv/opentitan.c | 81 +---
2 file
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> This value is constant across all thread-local copies of TCGContext,
> so we might as well move it out of thread-local storage.
>
> Signed-off-by: Richard Henderson
> ---
> include/tcg/tcg.h| 2 +-
> accel/tcg/tcg-runtime.c
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> This value is constant across all thread-local copies of TCGContext,
> so we might as well move it out of thread-local storage.
>
> Use the correct function pointer type, and name the variable
> tcg_qemu_tb_exec, which means that we are
On Mon, Dec 14, 2020 at 6:03 AM Richard Henderson
wrote:
>
> For darwin, the CTR_EL0 register is not accessible, but there
> are system routines that we can use.
>
> For other hosts, copy the single pointer implementation from
> libgcc and modify it to support the double pointer interface
> we req
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> We are shortly going to have a split rw/rx jit buffer. Depending
> on the host, we need to flush the dcache at the rw data pointer and
> flush the icache at the rx code pointer.
>
> For now, the two passed pointers are identical, so the
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> This has been a tcg-specific function, but is also in use
> by hardware accelerators via physmem.c. This can cause
> link errors when tcg is disabled.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Joelle van Dyne
On 11/23/2020 05:36 PM, Quentin Grolleau wrote:
Hello,
In our company, we are hosting a large number of Vm, hosted behind
Openstack (so libvirt/qemu).
A large majority of our Vms are runnign with local data only, stored
on NVME, and most of them are RAW disks.
With Qemu 4.0(can be even with
On 11/7/20 12:08 AM, Cleber Rosa wrote:
And this seems like another change.
- Cleber.
Fair enough.
On Mon, Dec 14, 2020 at 4:13 PM Hao Wu wrote:
> This patch makes NPCM7XX Timer to use a the timer clock generated by the
> CLK module instead of the magic number TIMER_REF_HZ.
>
> Reviewed-by: Havard Skinnemoen
> Reviewed-by: Tyrone Ting
> Signed-off-by: Hao Wu
> ---
> hw/arm/npcm7xx.c
On Tue, 08 Dec 2020 14:56:08 PST (-0800), Alistair Francis wrote:
The RISC-V QEMU port currently has lot of preprocessor directives that
check if we are targetting a 32-bit or 64-bit CPU. This means that the
64-bit RISC-V target can not run 32-bit CPUs. This is different to most
other QEMU archit
On Mon, Dec 14, 2020 at 4:13 PM Hao Wu wrote:
> The ADC is part of NPCM7XX Module. Its behavior is controled by the
> ADC_CON register. It converts one of the eight analog inputs into a
> digital input and stores it in the ADC_DATA register when enabled.
>
> Users can alter input value by using q
On Mon, Dec 14, 2020 at 4:13 PM Hao Wu wrote:
> We add a qtest for the PWM in the previous patch. It proves it works as
> expected.
>
> Reviewed-by: Havard Skinnemoen
> Reviewed-by: Tyrone Ting
> Signed-off-by: Hao Wu
> ---
> tests/qtest/meson.build| 1 +
> tests/qtest/npcm7xx_pwm-t
On Mon, Dec 14, 2020 at 4:13 PM Hao Wu wrote:
> This patch series include a few more NPCM7XX devices including
>
> - Analog Digital Converter (ADC)
> - Pulse Width Modulation (PWM)
>
> We also modified the CLK module to generate clock values using qdev_clock.
> These clocks are used to determine
On Mon, Dec 14, 2020 at 4:13 PM Hao Wu wrote:
> The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
> identical PWM modules. Each module contains 4 PWM entries. Each PWM has
> two outputs: frequency and duty_cycle. Both are computed using inputs
> from software side.
>
> This mo
The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.
Users can alter input value by using qom-set QMP command.
Reviewed-by: Havard Skinnemoen
Revi
On Mon, Dec 14, 2020 at 4:13 PM Hao Wu wrote:
> This patch allows NPCM7XX CLK module to compute clocks that are used by
> other NPCM7XX modules.
>
> Add a new struct NPCM7xxClockConverterState which represents a
> single converter. Each clock converter in CLK module represents one
> converter in
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.
This module does not model detail pulse signals since it is expens
This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.
Reviewed-by: Havard Skinnemoen
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 5 +
hw/timer/npcm7xx_timer.c | 23 +++
We add a qtest for the PWM in the previous patch. It proves it works as
expected.
Reviewed-by: Havard Skinnemoen
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
tests/qtest/meson.build| 1 +
tests/qtest/npcm7xx_pwm-test.c | 490 +
2 files changed, 4
This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.
Add a new struct NPCM7xxClockConverterState which represents a
single converter. Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
ta
This patch series include a few more NPCM7XX devices including
- Analog Digital Converter (ADC)
- Pulse Width Modulation (PWM)
We also modified the CLK module to generate clock values using qdev_clock.
These clocks are used to determine various clocks in NPCM7XX devices.
Thank you for your revie
On Mon, Dec 14, 2020 at 08:30:50PM +, Peter Maydell wrote:
> This commit is the result of running the timer-del-timer-free.cocci
> script on the whole source tree.
For the ipmi portion:
Acked-by: Corey Minyard
>
> Signed-off-by: Peter Maydell
> ---
> I could split this up into multiple pa
Instead of using None as the built-in module filename, use an empty
string instead. This allows us to clarify the type of various interfaces
dealing with module names as always taking a string, which saves us from
having to use Optional[str] everywhere.
Signed-off-by: John Snow
---
scripts/qapi/
--
events.py had an info to route, was it by choice that it wasn't before?
Signed-off-by: John Snow
---
scripts/qapi/events.py | 2 +-
scripts/qapi/schema.py | 23 +--
scripts/qapi/types.py | 9 +
scripts/qapi/visit.py | 6 +++---
4 files changed, 22 insertions(+
A forthcoming patch is going to allow the empty string as a name for the
builtin module, and quotes will help us see that in test output. Without
this, git will be upset about trailing empty spaces in test output, so
the quotes are necessary.
Signed-off-by: John Snow
---
tests/qapi-schema/commen
In the modules that we are checking so far, we can be stricter about the
difference between Optional[T] and T types. Enable that check.
Enabling it now will assist review on further typing and cleanup work.
Signed-off-by: John Snow
---
scripts/qapi/mypy.ini | 1 -
1 file changed, 1 deletion(-)
QAPIGenC and QAPIGenH in particular depend on fname being defined, but
we have a usage of QAPIGenCCode that isn't intended to be associated
with a particular file.
No problem, move the write method down to the class that actually needs
it, and keep QAPIGenCCode more abstract.
Signed-off-by: John
Many places assume they can access these fields without checking them
first to ensure they are defined. Eliminating the _genc and _genh fields
and replacing them with functional properties that check for correct
state can ease the typing overhead by eliminating the Optional[T] return
type.
Signed-
We already assert this in end_if, but that's opaque to mypy. Do it in
_wrap_ifcond instead. Same effect at runtime, but mypy can now infer
the type in _wrap_ifcond's body.
Signed-off-by: John Snow
---
scripts/qapi/gen.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts
We use None to represent an object that has no source information
because it's a builtin. This complicates interface typing, since many
interfaces expect that there is an info object available to print errors
with.
Introduce a special QAPISourceInfo that represents these built-ins so
that if an er
Use this in preference to 'None', which helps remove some edge cases in
the typing.
Signed-off-by: John Snow
---
scripts/qapi/gen.py | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py
index a6dc991b1d03..0c5
Mypy cannot understand that this match can never be None, so help it
along.
Signed-off-by: John Snow
---
scripts/qapi/main.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/qapi/main.py b/scripts/qapi/main.py
index 42517210b805..271d9e84da94 100644
--- a/scripts/qa
Actually, the arg_type can indeed be Optional.
Signed-off-by: John Snow
---
scripts/qapi/events.py | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/scripts/qapi/events.py b/scripts/qapi/events.py
index 599f3d1f564b..9851653b9d11 100644
--- a/scripts/qapi/events.py
when boxed is true, expr.py asserts that we must have
arguments. Ultimately, this should mean that if boxed is True, that
arg_type should be defined. Mypy cannot infer this, and does not support
'stateful' type inference, e.g.:
```
if x:
assert y is not None
...
if x:
y.etc()
```
does n
Hi, this patchset enables strict optional checking in mypy for
everything we have typed so far.
In general, this patchset seeks to eliminate Optional[T] in favor of T
wherever possible. Optional types used for object properties,
function/method parameters and return values where we expect, in most
Hi,
In this series, we have incorporated the changes Marc-Andre proposed to
improve the code in v12. Following is a changelog that outlines the
differences between v12 and v13.
CHANGELOG:
[PATCH v13 02/19] multi-process: add configure and usage information
- Dropped “tests
This is just POC to prove that the docstrings, where they are written,
are correct to some minimum standard. It is included here for
reviewing/testing convenience.
Signed-off-by: John Snow
---
docs/conf.py | 3 ++-
docs/devel/index.rst | 1 +
docs/deve
This interprets single-backtick syntax in all of our Sphinx docs as a
cross-reference to *something*, including Python symbols.
Signed-off-by: John Snow
---
docs/conf.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/docs/conf.py b/docs/conf.py
index d40d8ff37bab..d0a8f78f6ead 100644
---
Merely a testing pre-requisite to prove consistency for docstrings in
QAPI refactors, not intended for review or merge.
John Snow (3):
[DO-NOT-MERGE] docs: replace single backtick (`) with double-backtick
(``)
[DO-NOT-MERGE] docs/sphinx: change default role to "any"
[DO-NOT-MERGE] docs:
The single backtick in ReST is the "default role". Currently, Sphinx's
default role is called "content". Sphinx suggests you can use the "Any"
role instead to turn any single-backtick enclosed item into a
cross-reference.
Before we do that, though, we'll need to turn all existing usages of the
"co
On 12/14/20 11:21 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Correct the indexing into s->cpu_ctlr for vCPUs.
>
Fixes: cbe1282b568 ("intc/arm_gic: Implement gic_update_virt() function")
LGTM but better double-check with GIC specialist ;)
Reviewed-by: Philippe Mathieu-Daudé
From: "Edgar E. Iglesias"
Correct the indexing into s->cpu_ctlr for vCPUs.
Signed-off-by: Edgar E. Iglesias
---
hw/intc/arm_gic.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index c60dc6b5e6..af41e2fb44 100644
--- a/hw/intc/arm_g
On Mon, Dec 14, 2020 at 10:56:13PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Claudio, Eduardo.
>
> On 12/14/20 8:10 PM, Eduardo Habkost wrote:
> > On Sat, Dec 12, 2020 at 04:55:23PM +0100, Claudio Fontana wrote:
> >> From: Eduardo Habkost
> >>
> >> since tcg_cpu_ops.h is only included in cpu.h,
>
From: "Edgar E. Iglesias"
Hi,
Found this while debugging an issue with lockups during boot of
Linux on Xen.
In the particular setup, I'm running without EL3 firmware so group0
interrupts are disabled on the physical interface and enabled on the
virtual interface.
Looks like we're checking the
On 12/14/20 3:02 PM, Richard Henderson wrote:
> Simplify the arguments to always use s->code_ptr instead of
> take it as an argument. That makes it easy to ensure that
> the value_ptr is always the rx version.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg.c | 6 +++---
>
On 12/14/20 3:02 PM, Richard Henderson wrote:
> There is nothing within the translators that ought to be
> changing the TranslationBlock data, so make it const.
>
> This does not actually use the read-only copy of the
> data structure that exists within the rx region.
>
> Signed-off-by: Richard H
Now that SUB LOGICAL outputs borrow, we can use that as input directly.
It also means we can re-use CC_OP_SUBU and produce an output borrow
directly from SUB LOGICAL WITH BORROW.
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/internal.h| 2 -
target/s390x/
The resulting cc is only dependent on the result and the carry-out.
Carry-out and borrow-out are inverses, so are trivially converted.
With tcg ops, it is easier to compute borrow-out than carry-out, so
save result and borrow-out rather than the inputs.
Borrow-out for 64-bit inputs is had via tcg_
On 12/14/20 3:02 PM, Richard Henderson wrote:
> We must change all targets at once, since all must match
> the declaration in tcg.c.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg.c| 2 +-
> tcg/aarch64/tcg-target.c.inc | 2 +-
> tcg/arm/tcg-target.c.inc | 2 +-
> t
The resulting cc is only dependent on the result and the
carry-out. So save those things rather than the inputs.
Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly
into cc_src. Carry-out for 32-bit inputs is had via extraction
from a normal 64-bit add (with zero-extended inputs).
On 12/14/20 3:02 PM, Richard Henderson wrote:
> There is nothing within the translators that ought to be
> changing the TranslationBlock data, so make it const.
>
> This does not actually use the read-only copy of the
> data structure that exists within the rx region.
>
> Signed-off-by: Richard H
Now that ADD LOGICAL outputs carry, we can use that as input directly.
It also means we can re-use CC_OP_ADDU and produce an output carry
directly from ADD LOGICAL WITH CARRY.
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/internal.h| 2 --
target/s390x/cc
While testing the float128_muladd changes for s390x host,
emulating under x86_64 of course, I noticed that the code
we generate for strings of ALCGR and SLBGR is pretty awful.
I realized that we were missing a trick: the output cc is
based only on the output (result and carry) and so we don't
need
Typo "disassembly" in subject?
On 12/14/20 3:02 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> include/disas/dis-asm.h | 4 ++--
> disas.c | 4 +---
> disas/capstone.c| 2 +-
> 3 files changed, 4 insertions(+), 6 deletions(-)
Reviewed-by: Philipp
On 12/14/20 3:02 PM, Richard Henderson wrote:
> Create a function to determine if a pointer is within the buffer.
>
> Signed-off-by: Richard Henderson
> ---
> include/tcg/tcg.h | 6 ++
> accel/tcg/translate-all.c | 26 --
> 2 files changed, 14 insertions(+),
On 12/14/20 3:02 PM, Richard Henderson wrote:
> This value is constant across all thread-local copies of TCGContext,
> so we might as well move it out of thread-local storage.
>
> Use the correct function pointer type, and name the variable
> tcg_qemu_tb_exec, which means that we are able to remov
On 12/14/20 3:02 PM, Richard Henderson wrote:
> This has been a tcg-specific function, but is also in use
> by hardware accelerators via physmem.c. This can cause
> link errors when tcg is disabled.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/cacheflush.h | 24 +
> tcg
Hi Claudio, Eduardo.
On 12/14/20 8:10 PM, Eduardo Habkost wrote:
> On Sat, Dec 12, 2020 at 04:55:23PM +0100, Claudio Fontana wrote:
>> From: Eduardo Habkost
>>
>> since tcg_cpu_ops.h is only included in cpu.h,
>> and as a standalone header it is not really useful,
>> as tcg_cpu_ops.h starts requi
Hi Peter,
This series has been reviewed, but it looks like it slipped through the cracks.
Is it possible it could be merged through your tree, assuming it looks good?
Thanks!
Joe
-Original Message-
From: Qemu-devel On Behalf
Of Joe Komlodi
Sent: Monday, November 16, 2020 3:11 PM
To: qe
On Fri, Dec 04, 2020 at 04:44:03PM +1100, David Gibson wrote:
> From: Greg Kurz
>
> Global properties have an @optional field, which allows to apply a given
> property to a given type even if one of its subclasses doesn't support
> it. This is especially used in the compat code when dealing with
I'm moving my git repositories to gitlab.com, update MAINTAINERS
to point to the correct URL.
Signed-off-by: Eduardo Habkost
---
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4663c143c3..6714257cf7 100644
--- a/MAINTAINERS
+
On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
wrote:
>
> This is currently a no-op within tci/tcg-target.h, but
> is about to be moved to a more generic location.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Joelle van Dyne
On Sat, Dec 12, 2020 at 04:55:07PM +0100, Claudio Fontana wrote:
[...]
> Claudio Fontana (14):
> i386: move kvm accel files into kvm/
> i386: move whpx accel files into whpx/
> i386: move hax accel files into hax/
> i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
> i386: move
Il lun 14 dic 2020, 21:48 Marc-André Lureau ha
scritto:
> Adding:
> meson.override_dependency('glib-2.0', dependency('glib-2.0', static:
> enable_static))
>
> just before the "vhost_user = not_found..." works. Is that what you had in
> mind?
>
Why not "meson.override_dependency('glib-2.0', glib
On Sat, Dec 12, 2020 at 11:00:03AM +0100, Claudio Fontana wrote:
> On 12/11/20 9:02 PM, Eduardo Habkost wrote:
> > On Fri, Dec 11, 2020 at 07:51:54PM +0100, Claudio Fontana wrote:
> >> On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote:
> >>> On 12/11/20 7:22 PM, Richard Henderson wrote:
> On 1
Patchew URL:
https://patchew.org/QEMU/20201214140314.18544-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201214140314.18544-1-richard.hender...@linaro.org
Subject: [PATCH v4 00/43] Mi
On 12/11/20 3:38 PM, Wainer dos Santos Moschetta wrote:
Replace the code (python) on after_script of the acceptance jobs that
is currently used to show the logs of failed tests. Instead it is used
the Avocado's testlogs plug-in which works likewise.
Signed-off-by: Wainer dos Santos Moschetta
From: Daniel P. Berrangé
The i440fx and Q35 machine types are both hardcoded to use the legacy
SMBIOS 2.1 entry point. This is a sensible conservative choice because
SeaBIOS only supports SMBIOS 2.1
EDK2, however, can also support SMBIOS 3.0 and QEMU already uses this on
the ARM virt machine typ
This prepares for exposing the SMBIOS entry point type as a
machine property on x86.
Based on a patch from Daniel P. Berrangé.
Signed-off-by: Daniel P. Berrangé
Signed-off-by: Eduardo Habkost
---
First version of this code was submitted at:
https://lore.kernel.org/qemu-devel/20200908165438.1008
On Fri, Dec 11, 2020 at 3:38 PM Wainer dos Santos Moschetta
wrote:
>
> To use Avocado's testlogs plug-in on CI it is required to use
> its 83.0 or greater version.
>
> Signed-off-by: Wainer dos Santos Moschetta
> ---
> tests/requirements.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-
This includes code previously submitted[1] by Daniel P. Berrangé
to add a "smbios-ep" machine property on PC.
SMBIOS 3.0 is necessary to support more than ~720 VCPUs, as a
large number of VCPUs can easily hit the table size limit of
SMBIOS 2.1 entry points.
[1]
https://lore.kernel.org/qemu-devel
Rename the enums to match the naming style used by QAPI. This
will allow us to more easily move the enum to the QAPI schema
later.
Based on portions of a patch submitted by Daniel P. Berrangé.
Signed-off-by: Daniel P. Berrangé
Signed-off-by: Eduardo Habkost
---
First version of this code was s
On Mon, Dec 14, 2020 at 9:07 PM Marc-André Lureau <
marcandre.lur...@gmail.com> wrote:
>
>
> On Mon, Dec 14, 2020 at 8:23 PM Paolo Bonzini wrote:
>
>> On 12/12/20 10:08, marcandre.lur...@redhat.com wrote:
>> > From: Marc-André Lureau
>> >
>> > Fix linking vhost-user binaries with with ./configur
1 - 100 of 366 matches
Mail list logo
