Re: [PATCH qemu v10] spapr: Implement Open Firmware client interface

On 05/12/2020 05:43, Greg Kurz wrote: On Fri, 4 Dec 2020 19:32:05 +0100 Greg Kurz wrote: That's all for now. Just one last item. I'm observing failures with nvram in the guest: [root@vir76 ~]# nvram --print-config [ 88.179444] nvram[936]: unhandled signal 11 at 7fffc83a nip 0

[PATCH 2/3] net: checksum: Add IP header checksum calculation

From: Guishan Qin At present net_checksum_calculate() only calculates TCP/UDP checksum in an IP packet, but assumes the IP header checksum to be provided by the software, e.g.: Linux kernel always calculates the IP header checksum. However this might not always be the case, e.g.: for an IP checks

[PATCH 1/3] net: checksum: Skip fragmented IP packets

From: Markus Carlstedt To calculate the TCP/UDP checksum we need the whole datagram. Unless the hardware has some logic to collect all fragments before sending the whole datagram first, it can only be done by the network stack, which is normally the case for the NICs we have seen so far. Skip th

[PATCH 3/3] net: checksum: Introduce fine control over checksum type

From: Bin Meng At present net_checksum_calculate() blindly calculates all types of checksums (IP, TCP, UDP). Some NICs may have a per type setting in their BDs to control what checksum should be offloaded. To support such hardware behavior, introduce a 'csum_flag' parameter to the net_checksum_ca

Re: [PATCH 27/30] x86 hvf cpus: Fix Lesser GPL version number

> On Oct 23, 2020, at 5:40 AM, Chetan Pant wrote: > > There is no "version 2" of the "Lesser" General Public License. > It is either "GPL version 2.0" or "Lesser GPL version 2.1". > This patch replaces all occurrences of "Lesser GPL version 2" with > "Lesser GPL version 2.1" in comment section.

[Bug 1906948] [NEW] Enabling OpenGL for GUI doesn't work on old laptop

Public bug reported: QEMU start command is: qemu-system-x86_64 -enable-kvm -m 2G -cpu host -smp 2 -cdrom ./linuxmint-20-mate-64bit.iso -boot d -vga virtio -soundhw hda -display gtk,gl=on and QEMU crashes immediately on startup and gives these error messages: qemu_gl_create_compile_shader: com

Re: [RFC v8 18/27] cpu: Move cpu_exec_* to tcg_ops

On 12/5/20 5:15 PM, Claudio Fontana wrote: > From: Eduardo Habkost > > Signed-off-by: Eduardo Habkost > [claudio: wrapped in CONFIG_TCG] > Signed-off-by: Claudio Fontana > Reviewed-by: Philippe Mathieu-Daudé > --- > accel/tcg/cpu-exec.c| 12 ++-- > include/hw/core/cpu.h

Re: [RFC v8 15/27] cpu: Introduce TCGCpuOperations struct

On 12/5/20 5:15 PM, Claudio Fontana wrote: > From: Eduardo Habkost > > The TCG-specific CPU methods will be moved to a separate struct, > to make it easier to move accel-specific code outside generic CPU > code in the future. Start by moving tcg_initialize(). > > The new CPUClass.tcg_opts field

[RFC v8 24/27] i386: split cpu accelerators from cpu.c, using AccelCPUClass

i386 is the first user of AccelCPUClass, allowing to split cpu.c into: cpu.ccpuid and common x86 cpu functionality host-cpu.c host x86 cpu functions and "host" cpu type kvm/cpu.cKVM x86 AccelCPUClass hvf/cpu.cHVF x86 AccelCPUClass tcg/cpu.cTCG x86 AccelCPU

[RFC v8 25/27] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn

move the call to the accel_cpu_interface method to the general cpu_exec_realizefn from target/i386, so it does not need to be called for every target explicitly as we enable more targets. Signed-off-by: Claudio Fontana --- cpu.c | 5 + target/i386/cpu.c | 15 --- 2 f

Re: [RFC v8 12/27] tcg: make CPUClass.cpu_exec_* optional

On 12/5/20 5:15 PM, Claudio Fontana wrote: > From: Eduardo Habkost > > This will let us simplify the code that initializes CPU class > methods, when we move cpu_exec_*() to a separate struct. [newline] Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Eduardo Habkost > Signed-off-by: Claud

[RFC v8 18/27] cpu: Move cpu_exec_* to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/cpu-exec.c| 12 ++-- include/hw/core/cpu.h | 6 -- include/hw/core/tcg-cpu-ops.h | 9 +++

Re: [RFC v8 14/27] cpu: Remove unnecessary noop methods

On 12/5/20 5:15 PM, Claudio Fontana wrote: > From: Eduardo Habkost > > Signed-off-by: Eduardo Habkost > Signed-off-by: Claudio Fontana > --- > hw/core/cpu.c | 13 - > 1 file changed, 13 deletions(-) > > diff --git a/hw/core/cpu.c b/hw/core/cpu.c > index 576fa1d7ba..994a12cb35 1006

[RFC v8 16/27] accel/tcg: split TCG-only code from cpu_exec_realizefn

move away TCG-only code, make it compile only on TCG. Signed-off-by: Claudio Fontana --- accel/tcg/cpu-exec.c | 28 + cpu.c | 70 --- hw/core/cpu.c | 6 +++- include/hw/core/cpu.h | 8 + 4 files changed, 74 in

[RFC v8 27/27] cpu: introduce cpu_accel_instance_init

centralize the calls to cpu->accel_cpu_interface Signed-off-by: Claudio Fontana --- hw/core/cpu.c | 9 + include/hw/core/cpu.h | 6 ++ target/i386/cpu.c | 9 ++--- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index f41c

Re: [RFC v8 13/27] tcg: Make CPUClass.debug_excp_handler optional

On 12/5/20 5:15 PM, Claudio Fontana wrote: > From: Eduardo Habkost > > Signed-off-by: Eduardo Habkost > Signed-off-by: Claudio Fontana > --- > accel/tcg/cpu-exec.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [RFC v8 00/22] i386 cleanup

Sorry, new script. this is of course "v8" of the i386 cleanup: v7 -> v8: add missing CONFIG_TCGs, fix bugs

[RFC v8 19/27] cpu: Move tlb_fill to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 6 +++--- accel/tcg/user-exec.c | 6 +++--- include/hw/core/cpu.h | 9 -

[RFC v8 26/27] hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn

move the call to qemu_init_vcpu inside cpu_common_realizefn, so it does not need to be done explicitly in each target cpu. This makes it a little bit better, but still the way realize is done continues to be bad; ideally the cpu_list_add would be done in common_cpu, and in this case we could avoid

[RFC v8 21/27] accel: extend AccelState and AccelClass to user-mode

Signed-off-by: Claudio Fontana --- MAINTAINERS| 2 +- accel/accel-common.c | 50 ++ accel/{accel.c => accel-softmmu.c} | 27 ++-- accel/accel-user.c | 24 ++ accel/meson.build

[RFC v8 13/27] tcg: Make CPUClass.debug_excp_handler optional

From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana --- accel/tcg/cpu-exec.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 890b88861a..64cba89356 100644 --- a/accel/tcg/cpu-exec.c +++ b/a

[RFC v8 22/27] accel: replace struct CpusAccel with AccelOpsClass

centralize the registration of the cpus.c module accelerator operations in accel/accel-softmmu.c Signed-off-by: Claudio Fontana --- MAINTAINERS | 3 ++- accel/accel-common.c | 11 + accel/accel-softmmu.c| 43 +++--- accel/acce

[RFC v8 10/27] i386: move TCG cpu class initialization out of helper.c

Signed-off-by: Claudio Fontana --- target/i386/cpu.c | 33 -- target/i386/cpu.h | 97 ++--- target/i386/helper-tcg.h | 112 ++ target/i386/helper.c | 23 --- target/i386/meson.build

[RFC v8 15/27] cpu: Introduce TCGCpuOperations struct

From: Eduardo Habkost The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded

[RFC v8 20/27] cpu: Move debug_excp_handler to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana --- accel/tcg/cpu-exec.c | 4 ++-- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 2 ++ target/arm/cpu.c | 2 +- target/i386/tcg-cpu.c | 2 +- target/lm32/cp

[RFC v8 08/27] i386: move TCG accel files into tcg/

Signed-off-by: Claudio Fontana --- target/i386/meson.build | 14 +- target/i386/{ => tcg}/bpt_helper.c | 0 target/i386/{ => tcg}/cc_helper.c | 0 target/i386/{ => tcg}/excp_helper.c | 0 target/i386/{ => tcg}/fpu_helper.c | 0 target/i386/{ => tcg}/int_helper.c |

[RFC v8 14/27] cpu: Remove unnecessary noop methods

From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana --- hw/core/cpu.c | 13 - 1 file changed, 13 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 576fa1d7ba..994a12cb35 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -199,15 +199,6 @@

[RFC v8 11/27] tcg: cpu_exec_{enter,exit} helpers

From: Eduardo Habkost Move invocation of CPUClass.cpu_exec_*() to separate helpers, to make it easier to refactor that code later. Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana --- accel/tcg/cpu-exec.c | 23 ++- 1 file changed, 18 insertions(+), 5 deletions

[RFC v8 07/27] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs

Signed-off-by: Claudio Fontana Reviewed-by: Roman Bolshakov --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 448593c904..f53f2678d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -444,7 +444,6 @@ M: Cameron Esfahani M: Roman Bolshakov W: https

[RFC v8 09/27] i386: move cpu dump out of helper.c into cpu-dump.c

Signed-off-by: Claudio Fontana --- target/i386/cpu-dump.c | 537 target/i386/cpu.h | 1 + target/i386/helper.c| 514 -- target/i386/meson.build | 1 + 4 files changed, 539 insertions(+), 514 deletions(-)

[RFC v8 23/27] accel: introduce AccelCPUClass extending CPUClass

add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. Signed-off-by: Claudio Fontana --- MAINTAINERS | 1 + accel/accel-common.c| 44 + include/

[RFC v8 12/27] tcg: make CPUClass.cpu_exec_* optional

From: Eduardo Habkost This will let us simplify the code that initializes CPU class methods, when we move cpu_exec_*() to a separate struct. Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana --- accel/tcg/cpu-exec.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-)

[RFC v8 06/27] i386: move hax accel files into hax/

Signed-off-by: Claudio Fontana --- MAINTAINERS | 2 +- target/i386/{ => hax}/hax-all.c | 0 target/i386/{ => hax}/hax-cpus.c | 0 target/i386/{ => hax}/hax-cpus.h | 0 target/i386/{ => hax}/hax-i386.h | 6 +++--- target/i386/{ => hax}/hax-interface.h

[RFC v8 03/27] accel/tcg: rename tcg-cpus functions to match module name

Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/tcg-cpus-icount.c | 24 ++-- accel/tcg/tcg-cpus-icount.h | 6 +-- accel/tcg/tcg-cpus-mttcg.c | 10 ++--- accel/tcg/tcg-cpus-rr.c | 74 ++-

[RFC v8 17/27] cpu: Move synchronize_from_tb() to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/cpu-exec.c | 4 ++-- include/hw/core/cpu.h | 8 include/hw/core/tcg-cpu-ops.h | 14 +++---

[RFC v8 05/27] i386: move whpx accel files into whpx/

Signed-off-by: Claudio Fontana --- MAINTAINERS | 5 + target/i386/meson.build | 5 + target/i386/whpx/meson.build | 4 target/i386/{ => whpx}/whp-dispatch.h | 0 target/i386/{ => whpx}/whpx-all.c | 0 target/i386/{ => whpx}/whpx-cp

[RFC v8 02/27] accel/tcg: split tcg_start_vcpu_thread

after the initial split into 3 tcg variants, we proceed to also split tcg_start_vcpu_thread. We actually split it in 2 this time, since the icount variant just uses the round robin function. Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- acce

[RFC v8 01/27] accel/tcg: split CpusAccel into three TCG variants

split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard H

[RFC v8 04/27] i386: move kvm accel files into kvm/

Signed-off-by: Claudio Fontana --- MAINTAINERS | 2 +- hw/i386/fw_cfg.c | 2 +- hw/i386/intel_iommu.c| 2 +- hw/i386/kvm/apic.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/i386/microvm.c

[RFC v8 00/22] i386 cleanup

*** BLURB HERE *** Hi all, this is v7 of the i386 cleanup, with the most interesting patches at the end. v6 -> v7: integrate TCGCpuOperations, refactored cpu_exec_realizefn * integrate TCGCpuOperations (Eduardo) Taken some refactoring from Eduardo for Tcg-only operations on CPUClass. * refacto

[PATCH] hw/timer/slavio_timer: Allow 64-bit accesses

Per the "NCR89C105 Chip Specification" referenced in the header: Chip-level Address Map -- | 1D0 -> | Counter/Timers| W,D| | 1DF |

Re: [PATCH] MAINTAINERS: che...@lemote.com -> chenhua...@kernel.org

On 12/5/20 10:22 AM, Huacai Chen wrote: > Use @kernel.org address as the main communications end point. Update the > corresponding M-entries and .mailmap (for git shortlog translation). > > Signed-off-by: Huacai Chen > --- > .mailmap| 2 ++ > MAINTAINERS | 8 > 2 files changed, 6 in

Re: [PATCH v1 1/1] intc/ibex_plic: Clear interrupts that occur during claim process

Tested-by: Jackie Ke Best Regards, Jackie Ke > On Dec 5, 2020, at 12:47 AM, Alistair Francis > wrote: > > Previously if an interrupt occured during the claim process (after the > interrupt is claimed but before it's completed) it would never be > cleared. > This patch ensures that we also c

Re: [PATCH 5/5] hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()

On 12/4/20 4:26 PM, Philippe Mathieu-Daudé wrote: > PTC field has 8 bits, PVPE has 4. We plan to use the > "hw/registerfields.h" API with MIPS CPU definitions > (target/mips/cpu.h). Meanwhile we use magic 8 and 4. > > Signed-off-by: Philippe Mathieu-Daudé > --- > We want to move that to mips_cpu_

Re: [PATCH 4/5] hw/mips/malta: Do not initialize MT registers if MT ASE absent

On 12/4/20 4:26 PM, Philippe Mathieu-Daudé wrote: > Do not initialize MT-related config register if the MT ASE > is not present. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/mips/malta.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 2/5] target/mips: Introduce ase_mt_available() helper

On 12/4/20 4:26 PM, Philippe Mathieu-Daudé wrote: > Instead of accessing CP0_Config3 directly and checking > the 'Multi-Threading Present' bit, introduce an helper > to simplify code review. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/cpu.h| 7 +++ > hw/mips/cps.c

Re: [PATCH 3/5] target/mips: Do not initialize MT registers if MT ASE absent

On 12/4/20 4:26 PM, Philippe Mathieu-Daudé wrote: > Do not initialize MT-related config registers if the MT ASE > is not present. As some functions access the 'mvp' structure, > we still zero-allocate it. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/translate_init.c.inc | 4

Re: [PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()

On 12/4/20 4:53 PM, Philippe Mathieu-Daudé wrote: > Yes, will follow. I'm tempted to inline gen_check_zero_element (actually > move gen_msa_BxZ as gen_check_zero_element prologue/epilogue). Not sure > gen_check_zero_element() can be reused later though. The other thing that could happen is that ge

Re: [PATCH 1/5] target/mips: Remove mips_def_t unused argument from mvp_init()

On 12/4/20 4:26 PM, Philippe Mathieu-Daudé wrote: > mvp_init() doesn't require any CPU definition (beside the > information accessible via CPUMIPSState). Remove the unused > argument. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/translate.c | 2 +- > target/mips/transla

Re: [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers

On 12/4/20 4:40 PM, Philippe Mathieu-Daudé wrote: > Back to the patch, instead of aliasing FPU registers to the MSA ones > (even when MSA is absent), we now alias the MSA ones to the FPU ones > (only when MSA is present). This is what I call the "inverted logic". > > BTW the point of this change i

Re: x86 TCG helpers clobbered registers

On 12/4/20 7:34 PM, Stephane Duverger wrote: >> You can't just inject a call anywhere you like. If you add it at >> the IR level, then the rest of the compiler will see it and work >> properly. If you add the call in the middle of another operation, >> the compiler doesn't get to see it and Bad T

Re: [RFC v7 15/22] cpu: Move tlb_fill to tcg_ops

On 12/4/20 8:27 PM, Philippe Mathieu-Daudé wrote: > On 12/4/20 7:14 PM, Claudio Fontana wrote: >> On 12/4/20 7:00 PM, Philippe Mathieu-Daudé wrote: >>> On 12/4/20 6:37 PM, Eduardo Habkost wrote: On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote: > On 11/30/20 3:35 AM,

Re: [PATCH] ppc/e500: Free irqs array to avoid memleak

On Fri, Dec 04, 2020 at 03:58:22PM +0800, Gan Qixin wrote: > When running qom-test, a memory leak occurred in the ppce500_init function, > this patch free irqs array to fix it. > > ASAN shows memory leak stack: > > Direct leak of 40 byte(s) in 1 object(s) allocated from: > #0 0xfffc5ceee1f0 i

Re: [PATCH 2/3] misc/mos6522: Use timer_free() in the finalize function to avoid memleak

On Fri, Dec 04, 2020 at 04:12:08PM +0800, Gan Qixin wrote: > When running device-introspect-test, a memory leak occurred in the > mos6522_init > function, this patch use timer_free() in the finalize function to fix it. > > ASAN shows memory leak stack: > > Direct leak of 96 byte(s) in 2 object(s

[PATCH] MAINTAINERS: che...@lemote.com -> chenhua...@kernel.org

Use @kernel.org address as the main communications end point. Update the corresponding M-entries and .mailmap (for git shortlog translation). Signed-off-by: Huacai Chen --- .mailmap| 2 ++ MAINTAINERS | 8 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/.mailmap b/.ma