Re: [PATCH 07/11] sockets: Fix default of UnixSocketAddress member @tight

Paolo Bonzini writes: > On 29/10/20 18:39, Paolo Bonzini wrote: >>> When @tight was set to false as it should be, absent @tight defaults >>> to false. Wrong, it should default to true. This is what breaks QMP. >> When @has_tight... > > Ah, I see what you meant here. Suggested reword: > > -

Re: [PATCH 07/11] sockets: Fix default of UnixSocketAddress member @tight

Eric Blake writes: > On 10/29/20 8:38 AM, Markus Armbruster wrote: >> QMP chardev-add defaults absent member @tight to false instead of >> true. HMP chardev-add and CLI -chardev correctly default to true. >> >> The previous commit demonstrated that socket_listen() and >> socket_connect() are br

Re: [PATCH 05/11] test-util-sockets: Synchronize properly, don't sleep(1)

Eric Blake writes: > On 10/29/20 8:38 AM, Markus Armbruster wrote: >> The abstract sockets test spawns a thread to listen and a accept, and > > s/and a/and/ Yes. >> a second one to connect, with a sleep(1) in between to "ensure" the >> former is listening when the latter tries to connect. Revi

Re: [PATCH v2 8/8] target/ppc: replaced the TODO with LOG_UNIMP and add break for silence warnings

On 10/30/20 1:40 AM, Chen Qun wrote: > When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: > target/ppc/mmu_helper.c: In function ‘dump_mmu’: > target/ppc/mmu_helper.c:1351:12: warning: this statement may fall through > [-Wimplicit-fallthrough=] > 1351 | if (ppc6

Re: [PATCH v7 0/3] hw/block/nvme: dulbe and dsm support

On Oct 27 18:57, Klaus Jensen wrote: > From: Klaus Jensen > > This adds support for the Deallocated or Unwritten Logical Block error > recovery feature as well as the Dataset Management command. > > v7: > - Handle negative return value from bdrv_block_status. > - bdrv_get_info may not be sup

Re: [PATCH v2 6/8] target/sparc/win_helper: silence the compiler warnings

On 10/30/20 1:40 AM, Chen Qun wrote: > When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: > target/sparc/win_helper.c: In function ‘get_gregset’: > target/sparc/win_helper.c:304:9: warning: this statement may fall through > [-Wimplicit-fallthrough=] > 304 | tra

Re: [PATCH v2 3/8] accel/tcg/user-exec: silence the compiler warnings

On 10/30/20 1:40 AM, Chen Qun wrote: > When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: > ../accel/tcg/user-exec.c: In function ‘handle_cpu_signal’: > ../accel/tcg/user-exec.c:169:13: warning: this statement may fall through > [-Wimplicit-fallthrough=] > 169 |

[PATCH v2] block: Remove unused BlockDeviceMapEntry

BlockDeviceMapEntry has never been used. It was added in commit facd6e2 "so that it is published through the introspection mechanism." What exactly introspecting types that aren't used for anything could accomplish isn't clear. What "introspection mechanism" to use is also nebulous. To the best

Re: Out-of-Process Device Emulation session at KVM Forum 2020

On Fri, Oct 30, 2020 at 3:04 AM Alex Williamson wrote: > It's great to revisit ideas, but proclaiming a uAPI is bad solely > because the data transfer is opaque, without defining why that's bad, > evaluating the feasibility and implementation of defining a well > specified data format rather than

Re: [PATCH v2 6/8] target/sparc/win_helper: silence the compiler warnings

On 10/29/20 5:40 PM, Chen Qun wrote: > When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: > target/sparc/win_helper.c: In function ‘get_gregset’: > target/sparc/win_helper.c:304:9: warning: this statement may fall through > [-Wimplicit-fallthrough=] > 304 | tra

Re: [PATCH v2 3/8] accel/tcg/user-exec: silence the compiler warnings

On 10/29/20 5:40 PM, Chen Qun wrote: > When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: > ../accel/tcg/user-exec.c: In function ‘handle_cpu_signal’: > ../accel/tcg/user-exec.c:169:13: warning: this statement may fall through > [-Wimplicit-fallthrough=] > 169 |

block: Fix some code style problems, "foo* bar" should be "foo *bar"

There have some code style problems be found when read the block driver code. So I fixes some problems of this error, ERROR: "foo* bar" should be "foo *bar". Signed-off-by: Liyang Shi Reported-by: Euler Robot --- block/blkdebug.c | 2 +- block/dmg.c | 2 +- block/qcow2.c| 4 ++-- bl

[PATCH] block: Fix some code style problems, "foo* bar" should be "foo *bar"

There have some code style problems be found when read the block driver code. So I fixes some problems of this error, ERROR: "foo* bar" should be "foo *bar". Signed-off-by: Liyang Shi Reported-by: Euler Robot --- block/blkdebug.c | 2 +- block/dmg.c | 2 +- block/qcow2.c| 4 ++-- bl

[PATCH v3 1/3] hw/9pfs : add spaces around operator

Fix code style. Operator needs spaces both sides. Signed-off-by: Xinhao Zhang Signed-off-by: Kai Deng Reported-by: Euler Robot Reviewed-by: Greg Kurz --- hw/9pfs/9p-local.c | 10 +- hw/9pfs/9p.c | 16 2 files changed, 13 insertions(+), 13 deletions(-) diff --gi

[PATCH v3 2/3] hw/9pfs : open brace '{' following struct go on the same line

Fix code style. Open braces for struct should go on the same line. Signed-off-by: Xinhao Zhang Signed-off-by: Kai Deng Reported-by: Euler Robot Reviewed-by: Greg Kurz --- hw/9pfs/9p.h | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/9pfs/9p.h b/hw/9pfs/9p.h inde

[PATCH v3 3/3] hw/9pfs : add space before the open parenthesis '('

Fix code style. Space required before the open parenthesis '('. Signed-off-by: Xinhao Zhang Signed-off-by: Kai Deng Reported-by: Euler Robot Reviewed-by: Greg Kurz --- hw/9pfs/cofs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/9pfs/cofs.c b/hw/9pfs/cofs.c index 5599

Live migration not possible from 5.0 to 5.1?

Hi All, I couldn't find any mention about live migration incompatibility between 5.0 and 5.1 in the release notes but at least on our AMD based platform live migration from 5.0 to 5.1 is not possible. The upgraded host had identical versions with it's pair before the upgrade was started: * qem

[PATCH] migration/dirtyrate: simplify inlcudes in dirtyrate.c

Remove redundant blank line which is left by Commit 662770af7c6e8c, also take this opportunity to remove redundant includes in dirtyrate.c. Signed-off-by: Chuan Zheng --- migration/dirtyrate.c | 5 - 1 file changed, 5 deletions(-) diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c i

Re: [PATCH] vfio-pci: add Ascend devices passthrough quirks

On Thu, 29 Oct 2020 19:40:48 +0800 Binfeng Wu wrote: > Ascend is a series of SoC processors developed by Huawei. Ascend310/910 > are highly efficient, flexible, and programmable AI processors in this > series and support device passthrough via vfio-pci. Ascends device > xloader update is only all

Re: Out-of-Process Device Emulation session at KVM Forum 2020

On Fri, 30 Oct 2020 09:11:23 +0800 Jason Wang wrote: > On 2020/10/29 下午11:46, Alex Williamson wrote: > > On Thu, 29 Oct 2020 23:09:33 +0800 > > Jason Wang wrote: > > > >> On 2020/10/29 下午10:31, Alex Williamson wrote: > >>> On Thu, 29 Oct 2020 21:02:05 +0800 > >>> Jason Wang wrote: > >>>

Question on UEFI ACPI tables setup and probing on arm64

Hi, I have a question on UEFI/ACPI tables setup and probing on arm64 platform. Currently on arm64 platform guest can be booted with both fdt and ACPI supported. If ACPI is enabled, [1] says the only defined method for passing ACPI tables to the kernel is via the UEFI system configuration table.

[PATCH] net/l2tpv3: Remove redundant check in net_init_l2tpv3()

The result has been checked to be NULL before, it cannot be NULL here, so the check is redundant. Remove it. Reported-by: Euler Robot Signed-off-by: AlexChen --- net/l2tpv3.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/net/l2tpv3.c b/net/l2tpv3.c index 55fea17c0

RE: [PATCH] tcg/optimize: Add fallthrough annotations

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Friday, October 30, 2020 4:07 AM > To: Thomas Huth ; Richard Henderson ; > qemu-devel@nongnu.org > Cc: Chenqun (kuhn) > Subject: Re: [PATCH] tcg/optimize: Add fallthrough annotations > > On 10/29/

[PATCH v8 11/11] hw/block/nvme: Document zoned parameters in usage text

Added brief descriptions of the new device properties that are now available to users to configure features of Zoned Namespace Command Set in the emulator. This patch is for documentation only, no functionality change. Signed-off-by: Dmitry Fomichev Reviewed-by: Niklas Cassel --- hw/block/nvme

[PATCH v8 06/11] hw/block/nvme: Support allocated CNS command variants

From: Niklas Cassel Many CNS commands have "allocated" command variants. These include a namespace as long as it is allocated, that is a namespace is included regardless if it is active (attached) or not. While these commands are optional (they are mandatory for controllers supporting the namesp

[PATCH v8 09/11] hw/block/nvme: Support Zone Descriptor Extensions

Zone Descriptor Extension is a label that can be assigned to a zone. It can be set to an Empty zone and it stays assigned until the zone is reset. This commit adds a new optional module property, "zoned.descr_ext_size". Its value must be a multiple of 64 bytes. If this value is non-zero, it become

[PATCH v8 08/11] hw/block/nvme: Introduce max active and open zone limits

Add two module properties, "zoned.max_active" and "zoned.max_open" to control the maximum number of zones that can be active or open. Once these variables are set to non-default values, these limits are checked during I/O and Too Many Active or Too Many Open command status is returned if they are e

[PATCH v8 05/11] hw/block/nvme: Add support for Namespace Types

From: Niklas Cassel Define the structures and constants required to implement Namespace Types support. Namespace Types introduce a new command set, "I/O Command Sets", that allows the host to retrieve the command sets associated with a namespace. Introduce support for the command set and enable

[PATCH v8 03/11] hw/block/nvme: Separate read and write handlers

With ZNS support in place, the majority of code in nvme_rw() has become read- or write-specific. Move these parts to two separate handlers, nvme_read() and nvme_write() to make the code more readable and to remove multiple is_write checks that so far existed in the i/o path. This is a refactoring

[PATCH v8 10/11] hw/block/nvme: Add injection of Offline/Read-Only zones

ZNS specification defines two zone conditions for the zones that no longer can function properly, possibly because of flash wear or other internal fault. It is useful to be able to "inject" a small number of such zones for testing purposes. This commit defines two optional device properties, "offl

[PATCH v8 01/11] hw/block/nvme: Add Commands Supported and Effects log

This log page becomes necessary to implement to allow checking for Zone Append command support in Zoned Namespace Command Set. This commit adds the code to report this log page for NVM Command Set only. The parts that are specific to zoned operation will be added later in the series. All incoming

[PATCH v8 07/11] hw/block/nvme: Support Zoned Namespace Command Set

The emulation code has been changed to advertise NVM Command Set when "zoned" device property is not set (default) and Zoned Namespace Command Set otherwise. Define values and structures that are needed to support Zoned Namespace Command Set (NVMe TP 4053) in PCI NVMe controller emulator. Define t

[PATCH v8 02/11] hw/block/nvme: Generate namespace UUIDs

In NVMe 1.4, a namespace must report an ID descriptor of UUID type if it doesn't support EUI64 or NGUID. Add a new namespace property, "uuid", that provides the user the option to either specify the UUID explicitly or have a UUID generated automatically every time a namespace is initialized. Sugge

[PATCH v2 11/11] target/arm: Improve do_prewiden_3d

We can use proper widening loads to extend 32-bit inputs, and skip the "widenfn" step. Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 +++ target/arm/translate-neon.c.inc | 66 ++--- 2 files changed, 43 insertions(+), 29 deletions(-) diff -

[PATCH v2 10/11] target/arm: Simplify do_long_3d and do_2scalar_long

In both cases, we can sink the write-back and perform the accumulate into the normal destination temps. Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 23 +-- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-neon.c.in

[PATCH v8 04/11] hw/block/nvme: Merge nvme_write_zeroes() with nvme_write()

nvme_write() now handles WRITE, WRITE ZEROES and ZONE_APPEND. Signed-off-by: Dmitry Fomichev Reviewed-by: Niklas Cassel Acked-by: Klaus Jensen --- hw/block/nvme.c | 72 +-- hw/block/trace-events | 1 - 2 files changed, 28 insertions(+), 45 deletio

[PATCH v8 00/11] hw/block/nvme: Support Namespace Types and Zoned Namespace Command Set

v7 -> v8: - Move refactoring commits to the front of the series. - Remove "attached" and "fill_pattern" device properties. - Only close open zones upon subsystem shutdown, not when CC.EN flag is set to 0. Avoid looping through all zones by iterating through lists of open and closed zone

[PATCH v2 08/11] target/arm: Add read/write_neon_element64

Replace all uses of neon_load/store_reg64 within translate-neon.c.inc. Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 + target/arm/translate-neon.c.inc | 94 - 2 files changed, 73 insertions(+), 47 deletions(-) diff --git a/tar

[PATCH v2 09/11] target/arm: Rename neon_load_reg64 to vfp_load_reg64

The only uses of this function are for loading VFP double-precision values, and nothing to do with NEON. Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++-- target/arm/translate-vfp.c.inc | 84 +- 2 files changed, 46 insertions(+), 46 de

[PATCH v2 04/11] target/arm: Use neon_element_offset in vfp_reg_offset

This seems a bit more readable than using offsetof CPU_DoubleU. Signed-off-by: Richard Henderson --- target/arm/translate.c | 13 - 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 88a926d1df..88ded4ac2c 100644 --- a/

[PATCH v2 07/11] target/arm: Rename neon_load_reg32 to vfp_load_reg32

The only uses of this function are for loading VFP single-precision values, and nothing to do with NEON. Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 +- target/arm/translate-vfp.c.inc | 184 - 2 files changed, 94 insertions(+), 94 del

[PATCH v2 06/11] target/arm: Expand read/write_neon_element32 to all MemOp

We can then use this to improve VMOV (scalar to gp) and VMOV (gp to scalar) so that we simply perform the memory operation that we wanted, rather than inserting or extracting from a 32-bit quantity. These were the last uses of neon_load/store_reg, so remove them. Signed-off-by: Richard Henderson

[PATCH v2 02/11] target/arm: Move neon_element_offset to translate.c

This will shortly have users outside of translate-neon.c.inc. Signed-off-by: Richard Henderson --- target/arm/translate.c | 20 target/arm/translate-neon.c.inc | 19 --- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/target/arm/tran

[PATCH v2 00/11] target/arm: Fix neon reg offsets

Much of the existing usage of neon_reg_offset is broken for big-endian hosts, as it computes the offset of the first 32-bit unit, not the offset of the entire vector register. Fix this by separating out the different usages. Make the whole thing look a bit more like the aarch64 code. Changes for

[PATCH v2 01/11] target/arm: Introduce neon_full_reg_offset

This function makes it clear that we're talking about the whole register, and not the 32-bit piece at index 0. This fixes a bug when running on a big-endian host. Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++ target/arm/translate-neon.c.inc | 44 +

[PATCH v2 03/11] target/arm: Use neon_element_offset in neon_load/store_reg

These are the only users of neon_reg_offset, so remove that. Signed-off-by: Richard Henderson --- target/arm/translate.c | 14 ++ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index bf0b5cac61..88a926d1df 100644 --- a/t

[PATCH v2 05/11] target/arm: Add read/write_neon_element32

Model these off the aa64 read/write_vec_element functions. Use it within translate-neon.c.inc. The new functions do not allocate or free temps, so this rearranges the calling code a bit. Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 target/arm/translate-neon.c

Re: [PATCH v2 00/19] Mirror map JIT memory for TCG

Patchew URL: https://patchew.org/QEMU/20201030004921.721096-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201030004921.721096-1-richard.hender...@linaro.org Subject: [PATCH v2 00/19]

Re: [PATCH V15 1/6] target/mips: Fix PageMask with variable page size

Hi, Richard, On Wed, Oct 28, 2020 at 4:48 PM Richard Henderson wrote: > > On 10/27/20 9:17 PM, Huacai Chen wrote: > > +invalid: > > +/* > > + * When invalid, ensure the value is bigger than or equal to > > + * the minimal but smaller than or equal to the maxium. > > + */ > > +

Re: Out-of-Process Device Emulation session at KVM Forum 2020

On 2020/10/29 下午11:46, Alex Williamson wrote: On Thu, 29 Oct 2020 23:09:33 +0800 Jason Wang wrote: On 2020/10/29 下午10:31, Alex Williamson wrote: On Thu, 29 Oct 2020 21:02:05 +0800 Jason Wang wrote: On 2020/10/29 下午8:08, Stefan Hajnoczi wrote: Here are notes from the session: protocol

[PATCH v2 19/19] tcg/aarch64: Support split-rwx code generation

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.c.inc | 57 tcg/tcg-pool.c.inc | 6 +++- 3 files changed, 38 insertions(+), 27 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-ta

[PATCH v2 16/19] tcg/i386: Support split-rwx code generation

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 20 +++- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 1b9d41bd56..bbbd1c2d4a 100644 --- a/tcg/i386/tcg-target

[PATCH v2 17/19] tcg/aarch64: Use B not BL for tcg_out_goto_long

A typo generated a branch-and-link insn instead of plain branch. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index fea784cf75..bd888bc66d 100644 -

[PATCH v2 10/19] tcg: Make tb arg to synchronize_from_tb const

There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx mirror. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 ++- target/arm/c

[PATCH v2 13/19] accel/tcg: Support split-rwx for linux with memfd

We cannot use a real temp file, because we would need to find a filesystem that does not have noexec enabled. However, a memfd is not associated with any filesystem. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 87 +++ 1 file changed, 80 i

[PATCH v2 04/19] tcg: Introduce tcg_mirror_rw_to_rx/tcg_mirror_rx_to_rw

Add two helper functions, using a global variable to hold the displacement. The displacement is currently always 0, so no change in behaviour. Begin using the functions in tcg common code only. Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 2 +- include/disas/disas.h

Re: Out-of-Process Device Emulation session at KVM Forum 2020

On 2020/10/30 上午2:07, Paolo Bonzini wrote: On 29/10/20 18:47, Kirti Wankhede wrote: On 10/29/2020 10:12 PM, Daniel P. Berrangé wrote: On Thu, Oct 29, 2020 at 04:15:30PM +, David Edmondson wrote: On Thursday, 2020-10-29 at 21:02:05 +08, Jason Wang wrote: 2) Did qemu even try to migrate

[PATCH v2 07/19] tcg: Adjust tcg_register_jit for const

We must change all targets at once, since all must match the declaration in tcg.c. Signed-off-by: Richard Henderson --- include/tcg/tcg.h| 2 +- tcg/tcg.c| 10 +- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-tar

[PATCH v2 00/19] Mirror map JIT memory for TCG

This is my take on Joelle's patch set: https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg07837.html First, lots more patches. For the most part, I convert one interface at a time, instead of trying to do it all at once. Then, convert the tcg backends one at a time, allowing for a backe

[PATCH v2 06/19] tcg: Adjust tcg_out_label for const

Simplify the arguments to always use s->code_ptr instead of take it as an argument. That makes it easy to ensure that the value_ptr is always the rx version. Signed-off-by: Richard Henderson --- tcg/tcg.c | 6 +++--- tcg/i386/tcg-target.c.inc | 10 +- 2 files changed, 8

Re: [RFC PATCH v5 00/33] Hexagon patch series

Patchew URL: https://patchew.org/QEMU/1604016519-28065-1-git-send-email-tsimp...@quicinc.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1604016519-28065-1-git-send-email-tsimp...@quicinc.com Subject: [RFC PATCH v5

[PATCH v2 2/8] hw/intc/arm_gicv3_kvm: silence the compiler warnings

When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: hw/intc/arm_gicv3_kvm.c: In function ‘kvm_arm_gicv3_put’: hw/intc/arm_gicv3_kvm.c:484:13: warning: this statement may fall through [-Wimplicit-fallthrough=] kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, tru

[PATCH v2 05/19] tcg: Adjust tcg_out_call for const

We must change all targets at once, since all must match the declaration in tcg.c. Signed-off-by: Richard Henderson --- tcg/tcg.c| 2 +- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc| 4 ++-- tcg/mips/tcg-target.c.inc

[PATCH v2 7/8] ppc: Add a missing break for PPC6xx_INPUT_TBEN

When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: hw/ppc/ppc.c: In function ‘ppc6xx_set_irq’: hw/ppc/ppc.c:118:16: warning: this statement may fall through [-Wimplicit-fallthrough=] 118 | if (level) { |^ hw/ppc/ppc.c:123:9: note: here

[PATCH v2 1/8] target/i386: silence the compiler warnings in gen_shiftd_rm_T1

The current "#ifdef TARGET_X86_64" statement affects the compiler's determination of fall through. When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: target/i386/translate.c: In function ‘gen_shiftd_rm_T1’: target/i386/translate.c:1773:12: warning: this statement may fal

[PATCH v2 3/8] accel/tcg/user-exec: silence the compiler warnings

When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: ../accel/tcg/user-exec.c: In function ‘handle_cpu_signal’: ../accel/tcg/user-exec.c:169:13: warning: this statement may fall through [-Wimplicit-fallthrough=] 169 | cpu_exit_tb_from_sighandler(cpu, old_set)

[RFC PATCH v5 33/33] Add Dockerfile for hexagon

Signed-off-by: Alessandro Di Federico Signed-off-by: Taylor Simpson --- .../debian-hexagon-cross.build-toolchain.sh| 141 + .../docker/dockerfiles/debian-hexagon-cross.docker | 18 +++ 2 files changed, 159 insertions(+) create mode 100755 tests/docker/dockerfiles/d

[RFC PATCH v5 32/33] Hexagon build infrastructure

Add file to default-configs Add hexagon to meson.build Add hexagon to target/meson.build Add target/hexagon/meson.build Change scripts/qemu-binfmt-conf.sh We can build a hexagon-linux-user target and run programs on the Hexagon scalar core. With hexagon-linux-clang installed, "make check-tcg" wil

[PATCH v2 18/19] tcg/aarch64: Implement flush_idcache_range manually

Copy the single pointer implementation from libgcc and modify it to support the double pointer interface we require. This halves the number of cache operations required when split-rwx is enabled. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 11 +--- tcg/aarch64/tcg-ta

[RFC PATCH v5 24/33] Hexagon (target/hexagon) macros

macros to interface with the generator macros referenced in instruction semantics Signed-off-by: Taylor Simpson --- target/hexagon/macros.h | 591 1 file changed, 591 insertions(+) create mode 100644 target/hexagon/macros.h diff --git a/target/h

[PATCH v2 14/19] RFC: accel/tcg: Support split-rwx for darwin/iOS with vm_remap

Cribbed from code posted by Joelle van Dyne , and rearranged to a cleaner structure. Completely untested. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 68 ++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/accel/tcg/translat

[PATCH v2 15/19] tcg: Return the rx mirror of TranslationBlock from exit_tb

This produces a small pc-relative displacement within the generated code to the TB structure that preceeds it. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 35 ++- tcg/tcg-op.c | 13 - 2 files changed, 34 insertions(+), 14 deleti

[RFC PATCH v5 30/33] Hexagon (linux-user/hexagon) Linux user emulation

Implementation of Linux user emulation for Hexagon Some common files modified in addition to new files in linux-user/hexagon Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- linux-user/hexagon/sockbits.h | 18 ++ linux-user/hexagon/syscall_nr.h | 322 +

[PATCH v2 03/19] tcg: Move tcg epilogue pointer out of TCGContext

This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Signed-off-by: Richard Henderson --- include/tcg/tcg.h| 2 +- accel/tcg/tcg-runtime.c | 2 +- tcg/tcg.c| 3 ++- tcg/aarch64/tcg-targe

[PATCH v2 12/19] tcg: Add --accel tcg,split-rwx property

Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend so for now, enabling it will result in an error. Signed-off-by: Richard Henderson --- include/sysemu/tcg.h | 2 +- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/t

[RFC PATCH v5 28/33] Hexagon (target/hexagon) TCG for floating point instructions

The imported code uses host floating point. We override them to use qemu softfloat Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 121 +++ 1 file changed, 121 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.

[RFC PATCH v5 29/33] Hexagon (target/hexagon) translation

Read the instruction memory Create a packet data structure Generate TCG code for the start of the packet Invoke the generate function for each instruction Generate TCG code for the end of the packet Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 85 ++ target/hexagon/transla

[RFC PATCH v5 27/33] Hexagon (target/hexagon) TCG for instructions with multiple definitions

Helpers won't work if there are multiple definitions, so we override these instructions using #define fGEN_TCG_. Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 198 +++ 1 file changed, 198 insertions(+) create mode 100644 target/hexagon/

[PATCH] target/riscv/csr.c : add space before the open parenthesis '('

Fix code style. Space required before the open parenthesis '('. Signed-off-by: Xinhao Zhang Signed-off-by: Kai Deng Reported-by: Euler Robot --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..e8b1

[RFC PATCH v5 25/33] Hexagon (target/hexagon) instruction classes

Determine legal VLIW slots for each instruction Signed-off-by: Taylor Simpson --- target/hexagon/iclass.h| 50 ++ target/hexagon/iclass.c| 73 ++ target/hexagon/imported/iclass.def | 51 ++

[PATCH v2 11/19] tcg: Use Error with alloc_code_gen_buffer

Report better error messages than just "could not allocate". Let alloc_code_gen_buffer set ctx->code_gen_buffer_size and ctx->code_gen_buffer, and simply return bool. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 60 ++- 1 file changed, 34 i

[RFC PATCH v5 11/33] Hexagon (target/hexagon) register fields

Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson --- target/hexagon/reg_fields.h | 36 target/hexagon/reg_fields_def.h | 41 + target/hexagon/reg_fields.c | 27

[PATCH v2 09/19] tcg: Make DisasContextBase.tb const

There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx mirror. Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 4 ++-- include/

[PATCH v2 02/19] tcg: Move tcg prologue pointer out of TCGContext

This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Use the correct function pointer type, and name the variable tcg_qemu_tb_exec, which means that we are able to remove the macro that does the casting. Replace HAVE_TCG_QEM

[RFC PATCH v5 26/33] Hexagon (target/hexagon) TCG generation

Include the generated files and set up the data structures Signed-off-by: Taylor Simpson --- target/hexagon/genptr.h | 25 ++ target/hexagon/genptr.c | 234 2 files changed, 259 insertions(+) create mode 100644 target/hexagon/genptr.h creat

[PATCH v2 08/19] tcg: Adjust tb_target_set_jmp_target for split rwx

Pass both rx and rw addresses to tb_target_set_jmp_target. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/arm/tcg-target.h | 2 +- tcg/i386/tcg-target.h| 6 +++--- tcg/mips/tcg-target.h| 2 +- tcg/ppc/tcg-target.h | 2 +- tcg/ri

[PATCH v2 6/8] target/sparc/win_helper: silence the compiler warnings

When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: target/sparc/win_helper.c: In function ‘get_gregset’: target/sparc/win_helper.c:304:9: warning: this statement may fall through [-Wimplicit-fallthrough=] 304 | trace_win_helper_gregset_error(pstate); |

[RFC PATCH v5 14/33] Hexagon (target/hexagon) instruction printing

Signed-off-by: Taylor Simpson --- target/hexagon/printinsn.h | 28 target/hexagon/printinsn.c | 158 + 2 files changed, 186 insertions(+) create mode 100644 target/hexagon/printinsn.h create mode 100644 target/hexagon/printinsn.c diff --git

[PATCH v2 01/19] tcg: Enhance flush_icache_range with separate data pointer

We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Signed-off-by: Richard Hende

[PATCH v2 8/8] target/ppc: replaced the TODO with LOG_UNIMP and add break for silence warnings

When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: target/ppc/mmu_helper.c: In function ‘dump_mmu’: target/ppc/mmu_helper.c:1351:12: warning: this statement may fall through [-Wimplicit-fallthrough=] 1351 | if (ppc64_v3_radix(env_archcpu(env))) { |

[RFC PATCH v5 23/33] Hexagon (target/hexagon) opcode data structures

Signed-off-by: Taylor Simpson --- target/hexagon/opcodes.h | 63 + target/hexagon/opcodes.c | 142 +++ 2 files changed, 205 insertions(+) create mode 100644 target/hexagon/opcodes.h create mode 100644 target/hexagon/opcodes.c dif

[RFC PATCH v5 06/33] Hexagon (target/hexagon) register names

Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/hex_regs.h | 83 +++ 1 file changed, 83 insertions(+) create mode 100644 target/hexagon/hex_regs.h diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h new

[RFC PATCH v5 03/33] Hexagon (include/elf.h) ELF machine definition

Define EM_HEXAGON 164 Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/elf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/elf.h b/include/elf.h index 7a418ee..f4fa3c1 100644 --- a/incl

[RFC PATCH v5 15/33] Hexagon (target/hexagon/arch.[ch]) utility functions

Signed-off-by: Taylor Simpson --- target/hexagon/arch.h | 35 ++ target/hexagon/arch.c | 294 ++ 2 files changed, 329 insertions(+) create mode 100644 target/hexagon/arch.h create mode 100644 target/hexagon/arch.c diff --git a/target/hexagon

[PATCH v2 5/8] target/sparc/translate: silence the compiler warnings

When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: target/sparc/translate.c: In function ‘gen_st_asi’: target/sparc/translate.c:2320:12: warning: this statement may fall through [-Wimplicit-fallthrough=] 2320 | if (!(dc->def->features & CPU_FEATURE_HYPV)) {

[RFC PATCH v5 02/33] Hexagon (target/hexagon) README

Gives an introduction and overview to the Hexagon target Signed-off-by: Taylor Simpson --- target/hexagon/README | 235 ++ 1 file changed, 235 insertions(+) create mode 100644 target/hexagon/README diff --git a/target/hexagon/README b/target/hexa

[RFC PATCH v5 08/33] Hexagon (target/hexagon) GDB Stub

GDB register read and write routines Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/internal.h | 3 +++ target/hexagon/cpu.c | 2 ++ target/hexagon/gdbstub.c | 47 +++ 3 files changed, 52 insertions(+) create

[PATCH v2 4/8] linux-user/mips/cpu_loop: silence the compiler warnings

When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: linux-user/mips/cpu_loop.c: In function ‘cpu_loop’: linux-user/mips/cpu_loop.c:104:24: warning: this statement may fall through [-Wimplicit-fallthrough=] 104 | if ((ret = get_user_ual(arg8, sp_reg +

[RFC PATCH v5 33/33] Add Dockerfile for hexagon

Signed-off-by: Alessandro Di Federico Signed-off-by: Taylor Simpson --- .../debian-hexagon-cross.build-toolchain.sh| 141 + .../docker/dockerfiles/debian-hexagon-cross.docker | 18 +++ 2 files changed, 159 insertions(+) create mode 100755 tests/docker/dockerfiles/d

[PATCH v2 0/8] silence the compiler warnings

Since v1: - Patch1: Add comments to explain the two case of fall through. Addressed Richard Henderson and Thomas Huth review comment. - Patch2: Addressed Peter Maydell review comment. - Patch3: Add QEMU_NORETURN to cpu_exit_tb_from_sighandler() function to avoid the compiler warnings. - Patch4: A

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