On Sat, Oct 10, 2020 at 10:32:13AM +0800, Jason Wang wrote:
>
> On 2020/10/3 下午6:02, Greg Kurz wrote:
> > The open-coded computation of the used size doesn't take the event
> > into account when the VIRTIO_RING_F_EVENT_IDX feature is present.
> > Fix that by using vhost_get_used_size().
> >
> > S
Hi QEMU/KVM developers,
I am sorry if my email disturbs you. I did an experiment and found the
guest physical addresses (GPAs) are not the same as the corresponding
host virtual addresses (HVAs). I am curious about why; I think they
should be the same. I am very appreciated if you can give some
co
Hi, Philippe,
On Sun, Oct 11, 2020 at 4:43 AM Philippe Mathieu-Daudé wrote:
>
> Since its introduction in commit 6af0bf9c7c3,
> the 'r4k' machine runs at 200 MHz.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/mips/r4k.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> d
Hi, Philippe,
On Sat, Oct 10, 2020 at 9:07 PM Philippe Mathieu-Daudé wrote:
>
> On 10/7/20 10:39 AM, Huacai Chen wrote:
> > From: Jiaxun Yang
> >
> > LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
> > group of instructions by loongson-ext ASE.
> >
> > This patch add implemen
Hi, Philippe,
On Sat, Oct 10, 2020 at 5:09 PM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 10/7/20 10:39 AM, Huacai Chen wrote:
> > Add Loongson-3 based machine support, it use liointc as the interrupt
> > controler and use GPEX as the pci controller. Currently it can work with
> > both TC
David Gibson 于2020年10月10日周六 下午2:34写道：
>
> On Fri, Oct 09, 2020 at 07:02:56AM -0700, Elena Afanasova wrote:
> > >From 09905773a00e417d3a37c12350d9e55466fdce8a Mon Sep 17 00:00:00 2001
> > From: Elena Afanasova
> > Date: Fri, 9 Oct 2020 06:41:36 -0700
> > Subject: [PATCH] hw/net: move allocation to
Pan Nengyuan 于2020年9月4日周五 下午3:19写道：
>
> 'err' is unnecessary in x86_cpu_class_check_missing_features(), we can change
> x86_cpu_expand_features()
> to return true on success, false on failure, then pass NULL here to remove it.
>
> Signed-off-by: Pan Nengyuan
> Suggested-by: Markus Armbruster
R
Chen Qun 于2020年10月10日周六 下午7:08写道：
>
> This if statement judgment is redundant and it will cause a warning:
>
> migration/block-dirty-bitmap.c:1090:13: warning: ‘bitmap_name’ may be used
> uninitialized in this function [-Wmaybe-uninitialized]
> g_strlcpy(s->bitmap_name, bitmap_name,
On 20.09.2020 15:25, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> The get_vmstate_memory_region() method from PCDIMMDeviceClass is only
> ever called from this class and is never overridden, so it can be converted
> into an ordinary function.
>
> Signed-off-by: Maciej S. Szmigier
On 09.10.2020 23:33, Eduardo Habkost wrote:
> On Fri, Oct 09, 2020 at 11:05:47PM +0200, Maciej S. Szmigiero wrote:
>> On 09.10.2020 22:07, Eduardo Habkost wrote:
>>> Having properties registered conditionally makes QOM type
>>> introspection difficult. Instead of skipping registration of the
>>> "
Now than all QOM users provides the input clock, do not allow
using a CPS without input clock connected.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/cps.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 915655b91e0..c624821315a 100644
--- a/hw/
The MIPSsim machine CPU frequency is too fast running at 200 MHz,
while it should be 12 MHz for the 24K and 6 MHz for the 5K core.
Ref: Linux commit c78cbf49c4ed
("Support for MIPSsim, the cycle accurate MIPS simulator.")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/mipssim.c | 12
All our QOM users provides an input clock. In order to avoid
avoid future machines added without clock, display a warning.
User-mode emulation use the CP0 timer with the RDHWR instruction
(see commit cdfcad788394) so keep using the fixed 200 MHz clock
without diplaying any warning. Only display it
The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create
a 'cpuclk' output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw/mips/malta.c b/hw/m
The CPU frequency is normally provided by the firmware in the
"cpuclock" environment variable. The 2E board can handles up
to 660MHz, but be conservative and take the same value used
by the Linux kernel: 533 MHz.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/fuloong2e.c | 8 +++-
1 file
The I6400 can run at 1 GHz or more. Create a 'cpuclk'
output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 1b3f69e949c..cf2296f44
Use the Clock API and let the CPU object have an input clock.
If no clock is connected, keep using the default frequency of
200 MHz used since the introduction of the 'r4k' machine in
commit 6af0bf9c7c3.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 4
target/mips/cpu.c |
The get_random() helper uses the CP0_Wired register, which is
unrelated to the CP0_Count register use as timer.
Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file")
incorrectly moved this get_random() helper with timer specific
code. Move it back to generic CP0 helpers.
Reviewed-by: A
Expose a qdev input clock named 'clk-in', and connect it to each
core to forward-propagate the clock.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/cps.h | 2 ++
hw/mips/cps.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.
The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61
CPU at ~134 MHz.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/jazz.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 47723093b63..e56e36cf3f7 100644
--- a/h
Instead of directly aborting, display a hint to help the developer
figure out the problem (likely trying to connect a clock to a device
pre-dating the Clock API, thus not expecting clocks).
Reviewed-by: Luc Michel
Reviewed-by: Damien Hedde
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe
Since not all CPU implementations use a cores use a CP0 timer
at half the frequency of the CPU, make this variable a property.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 9 +
target/mips/cpu.c | 19 +++
2 files changed, 20 insertions(+), 8 deletions(-)
Since its introduction in commit 6af0bf9c7c3,
the 'r4k' machine runs at 200 MHz.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/r4k.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/mips/r4k.c b/hw/mips/r4k.c
index 3487013a4a1..e64687b505a 100644
--- a/hw/mips/r4
Name variables holding nanoseconds with the '_ns' suffix.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cp0_timer.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
Since commit 9f2ff99c7f2 ("qdev-monitor: print the device's clock
with info qtree") we can display the clock frequencies in the
monitor. Use the recently introduced freq_to_str() to display
the frequencies using the closest SI unit (human friendlier).
Before:
(qemu) info qtree
[...]
dev: xi
TIMER_PERIOD value of '10 ns' can be explained looking at
commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz
and CP0 default count rate is half the frequency of the
CPU. Document that.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cp0_timer.c | 12 +++-
1 file changed, 11
From: Marc-André Lureau
Thanks to the monitors coroutine support, the screendump handler can
trigger a graphic_hw_update(), yield and let the main loop run until
update is done. Then the handler is resumed, and ppm_save() will write
the screen image to disk in the coroutine context (thus non-bloc
The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.c
Introduce freq_to_str() to convert frequency values in human
friendly units using the SI units for Hertz.
Suggested-by: Luc Michel
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/cutils.h | 12
util/cutils.c | 1
Currently the CP0 timer period is fixed at 10 ns, corresponding
to a fixed CPU frequency of 200 MHz (using half the speed of the
CPU).
In few commits we will be able to use a different CPU frequency.
In preparation, move the cp0_count_ns variable to CPUMIPSState
so we can modify it.
Signed-off-by
From: Marc-André Lureau
The assert() was added in commit b681a1c73e15 ("block: Repair the
throttling code."), when the qemu_co_queue_do_restart() function
required to be running in a coroutine. It was later made unnecessary in
commit a9d9235567e7 ("coroutine-lock: reschedule coroutine on the
AioC
From: Luc Michel
This function creates a clock and parents it to another object with a given
name. It calls clock_setup_canonical_path before returning the new
clock.
This function is useful to create clocks in devices when one doesn't
want to expose it at the qdev level (as an input or an outpu
Since v2:
- Renamed "clk" -> "clk-in"
- Renamed "cpuclk-out -> "cpu-refclk"
Missing review: patches 6-20
~~~
All the MIPS cores emulated by QEMU provides the Coproc#0
'Count' register which can be used as a free running timer.
Since it's introduction in 2005 this timer uses a fixed
frequency of
From: Marc-André Lureau
Hi,
Thanks to recent work by Kevin, it becomes possible to run HMP/QMP commands i=
n a
coroutine. The screendump command is a good target, as it requires to re-enter
the main-loop in ordre to flush the display, and write to file in a non-block=
ing
way.
Despite the flush
From: Marc-André Lureau
The function is going to be called from a coroutine, and may yields.
Let's ensure our image reference doesn't change over time (due to resize
etc) by keeping a ref.
Signed-off-by: Marc-André Lureau
---
ui/console.c| 15 ---
ui/trace-events | 2 +-
2 fil
The SYS_timer is not directly wired to the ARM core, but to the
SoC (peripheral) interrupt controller.
Fixes: 0e5bbd74064 ("hw/arm/bcm2835_peripherals: Use the SYS_timer")
Reviewed-by: Luc Michel
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/bcm2835_peripheral
The variable holding the CTRL_STATUS register is misnamed
'status'. Rename it 'ctrl_status' to make it more obvious
this register is also used to control the peripheral.
Reviewed-by: Luc Michel
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/timer/bcm2835_sy
This peripheral has 1 free-running timer and 4 compare registers.
Only the free-running timer is implemented. Add support the
COMPARE registers (each register is wired to an IRQ).
Reference: "BCM2835 ARM Peripherals" datasheet [*]
chapter 12 "System Timer":
The System Timer periphe
Use the BCM2835_SYSTIMER_COUNT definition instead of the
magic '4' value.
Reviewed-by: Luc Michel
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/timer/bcm2835_systmr.h | 4 +++-
hw/timer/bcm2835_systmr.c | 3 ++-
2 files changed, 5 insertions(+), 2
In this series we implement the COMPARE registers of the
SYS_timer, since they are used by Linux.
This fixes the hang reported by Niek here:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg682090.html
Since v3:
- Addressed Richard review comments (arithmetic fix)
Since v2:
- Fixed issue in
On 10/3/20 7:17 PM, Richard Henderson wrote:
On 10/2/20 11:42 AM, Philippe Mathieu-Daudé wrote:
@@ -78,16 +71,29 @@ static void bcm2835_systmr_write(void *opaque, hwaddr
offset,
uint64_t value, unsigned size)
{
BCM2835SystemTimerState *s = BCM2835_SYST
On 10/10/20 7:26 PM, Philippe Mathieu-Daudé wrote:
The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create
a 'cpuclk' output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 20 +---
1 file changed, 17 insertions(
The linux microblaze port only implements rt signal handing,
not the old style. This allows our linux-test to pass for mb,
if you have a cross-compiler available for the build.
r~
Richard Henderson (2):
linux-user/microblaze: Implement rt signal frames
linux-user/microblaze: Remove non-rt
The microblaze kernel does not support these, and uses
only rt style signal frames.
Signed-off-by: Richard Henderson
---
linux-user/microblaze/target_signal.h | 1 -
linux-user/microblaze/signal.c| 97 +--
2 files changed, 2 insertions(+), 96 deletions(-)
diff -
The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create
a 'cpuclk' output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw/mips/malta.c b/hw/m
The I6400 can run at 1 GHz or more. Create a 'cpuclk'
output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 1b3f69e949c..c998140d7
All our QOM users provides an input clock. In order to avoid
avoid future machines added without clock, display a warning.
User-mode emulation use the CP0 timer with the RDHWR instruction
(see commit cdfcad788394) so keep using the fixed 200 MHz clock
without diplaying any warning. Only display it
Currently the CP0 timer period is fixed at 10 ns, corresponding
to a fixed CPU frequency of 200 MHz (using half the speed of the
CPU).
In few commits we will be able to use a different CPU frequency.
In preparation, move the cp0_count_ns variable to CPUMIPSState
so we can modify it.
Signed-off-by
Allows microblaze to pass tests/tcg/multiarch/linux-test.c.
Signed-off-by: Richard Henderson
---
linux-user/microblaze/signal.c | 91 ++
1 file changed, 82 insertions(+), 9 deletions(-)
diff --git a/linux-user/microblaze/signal.c b/linux-user/microblaze/signal.c
Use the Clock API and let the CPU object have an input clock.
If no clock is connected, keep using the default frequency of
200 MHz used since the introduction of the 'r4k' machine in
commit 6af0bf9c7c3.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 4
target/mips/cpu.c |
Expose a qdev input clock named 'clk', and connect it to each
core.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/cps.h | 2 ++
hw/mips/cps.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index 9e35a881366..859a8d4a674 1
Since not all CPU implementations use a cores use a CP0 timer
at half the frequency of the CPU, make this variable a property.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 9 +
target/mips/cpu.c | 19 +++
2 files changed, 20 insertions(+), 8 deletions(-)
Now than all QOM users provides the input clock, do not allow
using a CPS without input clock connected.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/cps.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index c332609f7b3..f044e500b8c 100644
--- a/hw/m
TIMER_PERIOD value of '10 ns' can be explained looking at
commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz
and CP0 default count rate is half the frequency of the
CPU. Document that.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cp0_timer.c | 12 +++-
1 file changed, 11
Instead of directly aborting, display a hint to help the developer
figure out the problem (likely trying to connect a clock to a device
pre-dating the Clock API, thus not expecting clocks).
Reviewed-by: Luc Michel
Reviewed-by: Damien Hedde
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe
The CPU frequency is normally provided by the firmware in the
"cpuclock" environment variable. The 2E board can handles up
to 660MHz, but be conservative and take the same value used
by the Linux kernel: 533 MHz.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/fuloong2e.c | 8 +++-
1 file
The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61
CPU at ~134 MHz.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/jazz.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 47723093b63..a506cacd5a7 100644
--- a/h
Name variables holding nanoseconds with the '_ns' suffix.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cp0_timer.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
The MIPSsim machine CPU frequency is too fast running at 200 MHz,
while it should be 12 MHz for the 24K and 6 MHz for the 5K core.
Ref: Linux commit c78cbf49c4ed
("Support for MIPSsim, the cycle accurate MIPS simulator.")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/mipssim.c | 12
Since commit 9f2ff99c7f2 ("qdev-monitor: print the device's clock
with info qtree") we can display the clock frequencies in the
monitor. Use the recently introduced freq_to_str() to display
the frequencies using the closest SI unit (human friendlier).
Before:
(qemu) info qtree
[...]
dev: xi
From: Luc Michel
This function creates a clock and parents it to another object with a given
name. It calls clock_setup_canonical_path before returning the new
clock.
This function is useful to create clocks in devices when one doesn't
want to expose it at the qdev level (as an input or an outpu
Since its introduction in commit 6af0bf9c7c3,
the 'r4k' machine runs at 200 MHz.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/r4k.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/mips/r4k.c b/hw/mips/r4k.c
index 3487013a4a1..6d550c637c6 100644
--- a/hw/mips/r4
The get_random() helper uses the CP0_Wired register, which is
unrelated to the CP0_Count register use as timer.
Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file")
incorrectly moved this get_random() helper with timer specific
code. Move it back to generic CP0 helpers.
Reviewed-by: A
Introduce freq_to_str() to convert frequency values in human
friendly units using the SI units for Hertz.
Suggested-by: Luc Michel
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/cutils.h | 12
util/cutils.c | 1
The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.c
All the MIPS cores emulated by QEMU provides the Coproc#0
'Count' register which can be used as a free running timer.
Since it's introduction in 2005 this timer uses a fixed
frequency of 100 MHz (for a CPU freq of 200 MHz).
While this is not an issue with Linux guests, it makes
some firmwares beha
On 10/1/20 8:42 PM, Eduardo Habkost wrote:
On Thu, Oct 01, 2020 at 06:43:20PM +0200, Philippe Mathieu-Daudé wrote:
Introduce freq_to_str() to convert frequency values in human
friendly units using the SI units for Hertz.
Suggested-by: Luc Michel
Signed-off-by: Philippe Mathieu-Daudé
---
inc
I already queued this patch to COLO proxy tree, then I will send a series to
Jason.
Thanks
Chen
> -Original Message-
> From: Pan Nengyuan
> Sent: Saturday, October 10, 2020 6:55 PM
> To: Li Qiang
> Cc: Qemu Developers ; Zhang, Chen
> ; Jason Wang ;
> zhanghailiang ; Chen Qun
> ; qemu-t
On 10/10/20 3:57 PM, Luc Michel wrote:
Those reset values have been extracted from a Raspberry Pi 3 model B
v1.2, using the 2020-08-20 version of raspios. The dump was done using
the debugfs interface of the CPRMAN driver in Linux (under
'/sys/kernel/debug/clk'). Each exposed clock tree stage (PL
On 10/10/20 3:57 PM, Luc Michel wrote:
PLLs are composed of multiple channels. Each channel outputs one clock
signal. They are modeled as one device taking the PLL generated clock as
input, and outputting a new clock.
A channel shares the CM register with its parent PLL, and has its own
A2W_CTRL
On Sat, 2020-10-10 at 17:07 +1100, David Gibson wrote:
> On Fri, Oct 09, 2020 at 07:02:56AM -0700, Elena Afanasova wrote:
> > > From 09905773a00e417d3a37c12350d9e55466fdce8a Mon Sep 17 00:00:00
> > > 2001
> > From: Elena Afanasova
> > Date: Fri, 9 Oct 2020 06:41:36 -0700
> > Subject: [PATCH] hw/ne
On 10/10/20 3:57 PM, Luc Michel wrote:
A clock mux can be configured to select one of its 10 sources through
the CM_CTL register. It also embeds yet another clock divider, composed
of an integer part and a fractional part. The number of bits of each
part is mux dependent.
Tested-by: Philippe Mat
On 10/10/20 3:57 PM, Luc Michel wrote:
The nanosecond unit greatly limits the dynamic range we can display in
clock value traces, for values in the order of 1GHz and more. The
internal representation can go way beyond this value and it is quite
common for today's clocks to be within those ranges.
On 10/10/20 5:17 PM, Philippe Mathieu-Daudé wrote:
On 10/10/20 3:57 PM, Luc Michel wrote:
This function creates a clock and parents it to another object with a
given
name. It calls clock_setup_canonical_path before returning the new
clock.
This function is useful to create clocks in devices wh
On 10/10/20 3:57 PM, Luc Michel wrote:
This function creates a clock and parents it to another object with a given
name. It calls clock_setup_canonical_path before returning the new
clock.
This function is useful to create clocks in devices when one doesn't
want to expose it at the qdev level (a
Add some of these features for AVR GPIO:
- GPIO I/O : PORTx registers
- Data Direction : DDRx registers
- DDRx toggling : PINx registers
Following things are not supported yet:
- MCUR registers
Signed-off-by: Heecheol Yang
---
hw/avr/Kconfig | 1 +
hw/avr/atmega.c
Hi Mark,
could you please pick it up?
Regards,
Artyom
сб, 19 сент. 2020 г., 20:47 Henrik Carlqvist :
> Just wanted to check that my patch hasn't been forgotten... I was hoping
> that
> it would make it into some branch in git.
>
> Do you want me to do any more changes to the patch or the descri
Connect the 'uart-out' clock from the CPRMAN to the PL011 instance.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
hw/arm/bcm2835_peripherals.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 9d6190042d..
Those reset values have been extracted from a Raspberry Pi 3 model B
v1.2, using the 2020-08-20 version of raspios. The dump was done using
the debugfs interface of the CPRMAN driver in Linux (under
'/sys/kernel/debug/clk'). Each exposed clock tree stage (PLLs, channels
and muxes) can be observed b
This simple mux sits between the PLL channels and the DSI0E and DSI0P
clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel
and outputs the selected signal to source number 4 of DSI0E/P clock
muxes. It is controlled by the cm_dsi0hsck register.
Reviewed-by: Philippe Mathieu-Daudé
A clock mux can be configured to select one of its 10 sources through
the CM_CTL register. It also embeds yet another clock divider, composed
of an integer part and a fractional part. The number of bits of each
part is mux dependent.
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
--
A PLL channel is able to further divide the generated PLL frequency.
The divider is given in the CTRL_A2W register. Some channels have an
additional fixed divider which is always applied to the signal.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Miche
Add a clock input to the PL011 UART so we can compute the current baud
rate and trace it. This is intended for developers who wish to use QEMU
to e.g. debug their firmware or to figure out the baud rate configured
by an unknown/closed source binary.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-
PLLs are composed of multiple channels. Each channel outputs one clock
signal. They are modeled as one device taking the PLL generated clock as
input, and outputting a new clock.
A channel shares the CM register with its parent PLL, and has its own
A2W_CTRL register. A write to the CM register wil
The clock multiplexers are the last clock stage in the CPRMAN. Each mux
outputs one clock signal that goes out of the CPRMAN to the SoC
peripherals.
Each mux has at most 10 sources. The sources 0 to 3 are common to all
muxes. They are:
0. ground (no clock signal)
1. the main oscillator (xosc
The CPRMAN PLLs generate a clock based on a prescaler, a multiplier and
a divider. The prescaler doubles the parent (xosc) frequency, then the
multiplier/divider are applied. The multiplier has an integer and a
fractional part.
This commit also implements the CPRMAN CM_LOCK register. This register
The BCM2835 CPRMAN is the clock manager of the SoC. It is composed of a
main oscillator, and several sub-components (PLLs, multiplexers, ...) to
generate the BCM2835 clock tree.
This commit adds a skeleton of the CPRMAN, with a dummy register
read/write implementation. It embeds the main oscillato
There are 5 PLLs in the CPRMAN, namely PLL A, C, D, H and B. All of them
take the xosc clock as input and produce a new clock.
This commit adds a skeleton implementation for the PLLs as sub-devices
of the CPRMAN. The PLLs are instantiated and connected internally to the
main oscillator.
Each PLL
This function creates a clock and parents it to another object with a given
name. It calls clock_setup_canonical_path before returning the new
clock.
This function is useful to create clocks in devices when one doesn't
want to expose it at the qdev level (as an input or an output).
Suggested-by:
The nanosecond unit greatly limits the dynamic range we can display in
clock value traces, for values in the order of 1GHz and more. The
internal representation can go way beyond this value and it is quite
common for today's clocks to be within those ranges.
For example, a frequency between 500MHz
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Signed-off-by: Luc Michel
---
include/hw/clock.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/clock.h b/include/hw/clock.h
index d357594df9..c93e6113cd 100644
--- a/include/hw/clock.h
+++ b/include/hw/clock.h
@
v2 -> v3:
- patch 03: moved clock_new definition to hw/core/clock.c [Phil]
- patch 03: commit message typo [Clement]
- patch 10: clarifications around the CM_CTL/CM_DIBV mux registers.
reg_cm replaced with reg_ctl and reg_div. Add some
comments for clarity. [Phil]
The CPRMAN (clock controller) was mapped at the watchdog/power manager
address. It was also split into two unimplemented peripherals (CM and
A2W) but this is really the same one, as shown by this extract of the
Raspberry Pi 3 Linux device tree:
watchdog@7e10 {
compatible = "brc
On 10/10/20 3:06 AM, Yifei Jiang wrote:
> +++ b/target/riscv/cpu.h
> @@ -311,6 +311,10 @@ extern const char * const riscv_fpr_regnames[];
> extern const char * const riscv_excp_names[];
> extern const char * const riscv_intr_names[];
>
> +#ifndef CONFIG_USER_ONLY
> +extern const VMStateDescript
On 10/10/20 2:59 PM, Peter Maydell wrote:
On Wed, 7 Oct 2020 at 09:44, Huacai Chen wrote:
Update MIPS KVM type defintition from Linux 5.9-rc6.
Signed-off-by: Huacai Chen
---
Is this a sync using scripts/update-linux-headers.sh ?
(I vaguely had the idea of adding a --make-commit option to
On 11:04 Tue 06 Oct , Philippe Mathieu-Daudé wrote:
> On 10/5/20 9:56 PM, Luc Michel wrote:
> > A clock mux can be configured to select one of its 10 sources through
> > the CM_CTL register. It also embeds yet another clock divider, composed
> > of an integer part and a fractional part. The num
On 10/7/20 10:39 AM, Huacai Chen wrote:
From: Jiaxun Yang
LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
group of instructions by loongson-ext ASE.
This patch add implementation of these instructions:
gslbx: load 1 bytes to GPR
gslhx: load 2 bytes to GPR
gslwx: load 4 byte
On Wed, 7 Oct 2020 at 09:44, Huacai Chen wrote:
>
> Update MIPS KVM type defintition from Linux 5.9-rc6.
>
> Signed-off-by: Huacai Chen
> ---
Is this a sync using scripts/update-linux-headers.sh ?
(I vaguely had the idea of adding a --make-commit option to
that script so it would automatically
On Fri, 9 Oct 2020 at 23:36, Richard Henderson
wrote:
>
> On 10/9/20 1:48 PM, Peter Maydell wrote:
> > On Fri, 9 Oct 2020 at 15:47, Peter Maydell wrote:
> >> +tcg_gen_extr_i64_i32(t1, t2, p64);
> >
> > Oh, I forgot to mention, but it looks like extr_i64_i32
> > isn't documented in tcg/REA
On 13:33 Sat 10 Oct , Luc Michel wrote:
> On 10:40 Tue 06 Oct , Philippe Mathieu-Daudé wrote:
> > On 10/5/20 9:56 PM, Luc Michel wrote:
> > > The clock multiplexers are the last clock stage in the CPRMAN. Each mux
> > > outputs one clock signal that goes out of the CPRMAN to the SoC
> > > p
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