On 6/2/20 11:37 PM, Philippe Mathieu-Daudé wrote:
> Hi Guenter,
>
> On 6/3/20 7:24 AM, Guenter Roeck wrote:
>> The Linux kernel's IMX code now uses vendor specific commands.
>> This results in endless warnings when booting the Linux kernel.
>>
>> sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_
Hi Pan,
On 6/3/20 9:03 AM, Pan Nengyuan wrote:
> 'obj' forgot to free at the end of hmp_qom_get(). Fix that.
>
> The leak stack:
> Direct leak of 40 byte(s) in 1 object(s) allocated from:
> #0 0x7f4e3a779ae8 in __interceptor_malloc (/lib64/libasan.so.5+0xefae8)
> #1 0x7f4e398f91d5 in g_ma
100 run on bionic/eoan/focal -proposed `qemu-img convert` all
successful. No hang occurs. Thanks a lot.
** Tags removed: verification-needed verification-needed-eoan
verification-needed-focal
** Tags added: verification-done-bionic verification-done-eoan
verification-done-focal
** Changed in: k
On 2020/5/29 下午10:06, Cindy Lu wrote:
From: Tiwei Bie
Currently we have 2 types of vhost backends in QEMU: vhost kernel and
vhost-user. The above patch provides a generic device for vDPA purpose,
this vDPA device exposes to user space a non-vendor-specific configuration
interface for setting u
Hi Catherine,
On 6/3/20 7:23 AM, agrecascino...@gmail.com wrote:
> From: "Catherine A. Frederick"
>
> Signed-off-by: "Catherine A. Frederick"
> ---
> tcg/ppc/tcg-target.inc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
> i
On 2020/5/29 下午10:06, Cindy Lu wrote:
From: Tiwei Bie
Similar for this patch, you can change the git author and keep sobs for
both Tiwei and Ling Shan.
This patch set introduces a new net client type: vhost-vdpa.
vhost-vdpa net client will set up a vDPA device which is specified
by a
Hi Guenter,
On 6/3/20 7:24 AM, Guenter Roeck wrote:
> The Linux kernel's IMX code now uses vendor specific commands.
> This results in endless warnings when booting the Linux kernel.
>
> sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_clock_gate_off:
> card clock still not gate off in 10
Hi Guenter,
On 6/3/20 7:24 AM, Guenter Roeck wrote:
> Set vendor property to IMX to enable IMX specific functionality
> in sdhci code.
>
> Signed-off-by: Guenter Roeck
> ---
> hw/arm/fsl-imx25.c | 2 ++
> hw/arm/fsl-imx6.c | 2 ++
> hw/arm/fsl-imx6ul.c | 2 ++
> hw/arm/fsl-imx7.c | 2 ++
>
'obj' forgot to free at the end of hmp_qom_get(). Fix that.
The leak stack:
Direct leak of 40 byte(s) in 1 object(s) allocated from:
#0 0x7f4e3a779ae8 in __interceptor_malloc (/lib64/libasan.so.5+0xefae8)
#1 0x7f4e398f91d5 in g_malloc (/lib64/libglib-2.0.so.0+0x531d5)
#2 0x55c9fd9a3999
Little bit better the second version of the patch, difficult to sort
out things with mailing list :-)
>From ce857629697e8b6a2149fd3a1e16b7eea26aafca Mon Sep 17 00:00:00 2001
From: David Carlier
Date: Tue, 26 May 2020 21:35:27 +0100
Subject: [PATCH] util/oslib: current process full path resolution
Sorry it landed in the spam.
It does make things more accurate, thus a bit more than cosmetic, as
stated in the commit message, thr_self/_lwp_self represents the
current thread id in multi thread context.
For OpenBSD it is syscall(SYS_getthrid) I believe
https://man.openbsd.org/getthrid.2
On Wed
On 5/30/20 7:41 PM, Thomas Huth wrote:
> On 29/05/2020 18.54, Philippe Mathieu-Daudé wrote:
>> While replacing fprintf() by qemu_log_mask() in commit
>> 2b55f4d3504, we incorrectly used a 'tab = 4 spaces'
>> alignment, leading to misindented new code. Fix now.
>>
>> Reported-by: Peter Maydell
>> S
Cc'ing more developers.
On 5/26/20 10:40 PM, David CARLIER wrote:
> From b24a6702beb2a4e2a9c1c03b69c6d1dd07d4cf08 Mon Sep 17 00:00:00 2001
> From: David Carlier
> Date: Tue, 26 May 2020 21:35:27 +0100
> Subject: [PATCH] util/oslib: current process full path resolution on MacOS
>
> Using existing
Ping for review.
Also, as unicore32 is not very active, can this go via qemu-trivial?
On 5/24/20 6:45 PM, Philippe Mathieu-Daudé wrote:
> Replace some debug printf() calls by qemu_log_mask(LOG_GUEST_ERROR).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/dma/puv3_dma.c | 9 +++--
>
From: Pavel Dovgalyuk
Windows guest sometimes makes DMA requests with overlapping
target addresses. This leads to the following structure of iov for
the block driver:
addr size1
addr size2
addr size3
It means that three adjacent disk blocks should be read into the same
memory buffer. Windows do
The ADC region size is 256B, split as:
- [0x00 - 0x4f] defined
- [0x50 - 0xff] reserved
All registers are 32-bit (thus when the datasheet mentions the
last defined register is 0x4c, it means its address range is
0x4c .. 0x4f.
This model implementation is also 32-bit. Set MemoryRegionOps
'impl'
On 02.06.2020 18:54, Kevin Wolf wrote:
Am 30.04.2020 um 11:02 hat Pavel Dovgalyuk geschrieben:
From: Pavel Dovgalyuk
Windows guest sometimes makes DMA requests with overlapping
target addresses. This leads to the following structure of iov for
the block driver:
addr size1
addr size2
addr si
On 2020/6/3 12:27, Richard Henderson wrote:
On 5/21/20 2:43 AM, LIU Zhiwei wrote:
@@ -174,6 +175,9 @@ static int write_frm(CPURISCVState *env, int csrno,
target_ulong val)
env->mstatus |= MSTATUS_FS;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
+if (!riscv_cpu_set_roun
On Tue, Jun 02, 2020 at 09:55:28PM -0600, Alex Williamson wrote:
> On Tue, 2 Jun 2020 23:19:48 -0400
> Yan Zhao wrote:
>
> > On Tue, Jun 02, 2020 at 04:55:27PM -0600, Alex Williamson wrote:
> > > On Wed, 29 Apr 2020 20:39:50 -0400
> > > Yan Zhao wrote:
> > >
> > > > On Wed, Apr 29, 2020 at 05
Set vendor property to IMX to enable IMX specific functionality
in sdhci code.
Signed-off-by: Guenter Roeck
---
hw/arm/fsl-imx25.c | 2 ++
hw/arm/fsl-imx6.c | 2 ++
hw/arm/fsl-imx6ul.c | 2 ++
hw/arm/fsl-imx7.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/hw/arm/fsl-imx25.c b/hw/a
The Linux kernel's IMX code now uses vendor specific commands.
This results in endless warnings when booting the Linux kernel.
sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_clock_gate_off:
card clock still not gate off in 100us!.
Implement support for the vendor specific command impl
The Linux kernel's IMX code now uses vendor specific commands.
This results in endless warnings when booting the Linux kernel.
sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_clock_gate_off:
card clock still not gate off in 100us!.
Implement support for the vendor specific command impl
On Wed, Jun 3, 2020 at 10:54 AM Jason Wang wrote:
>
>
> On 2020/5/29 下午10:06, Cindy Lu wrote:
> > From: Tiwei Bie
>
>
> Consider the significant modification based on the original patch.
>
> I think you may change the other to yourslef and keep the sobs for both
> Tiwei and Lingshan.
>
> Thanks
>
Hi Jason,
On Wed, Jun 3, 2020 at 10:52 AM Jason Wang wrote:
>
>
> On 2020/5/29 下午10:06, Cindy Lu wrote:
> > From: Tiwei Bie
> >
> > Currently we have 2 types of vhost backends in QEMU: vhost kernel and
> > vhost-user. The above patch provides a generic device for vDPA purpose,
> > this vDPA devi
From: "Catherine A. Frederick"
Signed-off-by: "Catherine A. Frederick"
---
tcg/ppc/tcg-target.inc.c | 4
1 file changed, 4 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index ee1f9227c1..a5450a5e67 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-ta
ping for review?
On 5/24/20 6:48 PM, Philippe Mathieu-Daudé wrote:
> Convert APM_DPRINTF() to trace events and remove ifdef'ry.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/isa/apm.c| 15 +--
> hw/isa/trace-events | 4
> 2 files changed, 9 insertions(+), 10 del
ping?
On 5/26/20 9:29 AM, David CARLIER wrote:
> From 792fbcd9114f43bd80fd1ef5b25cd9935a536f9f Mon Sep 17 00:00:00 2001
> From: David Carlier
> Date: Tue, 26 May 2020 08:25:26 +0100
> Subject: [PATCH] util/oslib: Returns the real thread identifier on FreeBSD and
> NetBSD
>
> getpid is good enou
Patchew URL:
https://patchew.org/QEMU/20200603044701.10748-1-agrecascino...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200603044701.10748-1-agrecascino...@gmail.com
Subject: [PATCH] tcg: Sanitize shift constants on
Oh dear, it appears that git send-email ate the formatting, hang on.
On Wed, Jun 3, 2020 at 12:47 AM wrote:
>
> From: "Catherine A. Frederick"
>
> ---
> tcg/ppc/tcg-target.inc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
> in
ping?
On 5/18/20 12:39 PM, Philippe Mathieu-Daudé wrote:
> Update Fred Konrad email address to avoid emails bouncing.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> .mailmap | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/.mailmap b/.mailmap
> index 6412067bde..4c7f4b7d03 100644
>
On 5/18/20 9:43 AM, Thomas Huth wrote:
> The '\n' sneaked in by accident here, an "id" string should really
> not contain a newline character at the end.
>
> Fixes: 78cd6f7bf6b ('net: Add a new convenience option "--nic" ...')
> Signed-off-by: Thomas Huth
> ---
> net/net.c | 2 +-
> 1 file chang
On 5/5/20 4:28 PM, Philippe Mathieu-Daudé wrote:
> Drop superfluous parenthesis around VMPortReadFunc typedef
> (added in d67f679d99, missed to remove when moved in e595112985).
>
> Suggested-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i386/vmport.h | 2 +-
> 1 file
From: "Catherine A. Frederick"
---
tcg/ppc/tcg-target.inc.c | 4
1 file changed, 4 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index ee1f9227c1..a5450a5e67 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -790,21 +790,25 @@ static i
On 5/21/20 2:43 AM, LIU Zhiwei wrote:
> @@ -174,6 +175,9 @@ static int write_frm(CPURISCVState *env, int csrno,
> target_ulong val)
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
> +if (!riscv_cpu_set_rounding_mode(env, env->frm)) {
> +re
All autopkgtests for the newly accepted qemu (1:4.0+dfsg-0ubuntu9.7) for eoan
have finished running.
The following regressions have been reported in tests triggered by the package:
edk2/0~20190606.20d2e5a1-2ubuntu1.1 (amd64, armhf)
Please visit the excuses page listed below and investigate the
On 6/2/20 7:15 PM, no-re...@patchew.org wrote:
> This series seems to have some coding style problems.
Hmph, some of these are real.
I'll fix for v8, with other review.
r~
On Tue, 2 Jun 2020 23:19:48 -0400
Yan Zhao wrote:
> On Tue, Jun 02, 2020 at 04:55:27PM -0600, Alex Williamson wrote:
> > On Wed, 29 Apr 2020 20:39:50 -0400
> > Yan Zhao wrote:
> >
> > > On Wed, Apr 29, 2020 at 05:48:44PM +0800, Dr. David Alan Gilbert wrote:
> > >
> > > > > > > > > > > > >
On Tue, Jun 02, 2020 at 04:55:27PM -0600, Alex Williamson wrote:
> On Wed, 29 Apr 2020 20:39:50 -0400
> Yan Zhao wrote:
>
> > On Wed, Apr 29, 2020 at 05:48:44PM +0800, Dr. David Alan Gilbert wrote:
> >
> > > > > > > > > > > > > > > An mdev type is meant to define a software
> > > > > > > > > >
On 2020/5/29 下午10:06, Cindy Lu wrote:
From: Tiwei Bie
Consider the significant modification based on the original patch.
I think you may change the other to yourslef and keep the sobs for both
Tiwei and Lingshan.
Thanks
Currently we have 2 types of vhost backends in QEMU: vhost kerne
On 2020/5/29 下午10:06, Cindy Lu wrote:
From: Tiwei Bie
Currently we have 2 types of vhost backends in QEMU: vhost kernel and
vhost-user. The above patch provides a generic device for vDPA purpose,
this vDPA device exposes to user space a non-vendor-specific configuration
interface for setting
On 6/2/20 9:07 PM, Richard Henderson wrote:
On 6/2/20 6:36 PM, Eric Blake wrote:
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -176,11 +176,9 @@ extern unsigned long reserved_va;
* avoid setting bits at the top of guest addresses that might need
* to be used for tags.
*/
Patchew URL:
https://patchew.org/QEMU/20200603011317.473934-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200603011317.473934-1-richard.hender...@linaro.org
Subject: [PATCH v7 00/42] target/arm: I
On 6/2/20 7:02 PM, Ying Fang wrote:
> Virtual time adjustment was implemented for virt-5.0 machine type,
> but the cpu property was enabled only for host-passthrough and
> max cpu model. Let's add it for arm cpu which has the gernic
"generic"
> timer feature enabled.
>
>
> Signed-off-by: Ying F
On 6/2/20 6:36 PM, Eric Blake wrote:
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -176,11 +176,9 @@ extern unsigned long reserved_va;
> * avoid setting bits at the top of guest addresses that might need
> * to be used for tags.
> */
> -#if MIN(TARGET_VIRT_ADDR_SPACE_BITS
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cpu which has the gernic
timer feature enabled.
Signed-off-by: Ying Fang
---
v2:
- move kvm_arm_add_vcpu_properties into arm_cpu_
On Tue, Jun 2, 2020, at 5:55 AM, Stefan Hajnoczi wrote:
>
> Ping Colin. It would be great if you have time to share your thoughts on
> this discussion and explain how you are using this patch.
Yeah sorry about not replying in this thread earlier, this was just a quick
Friday side project for
I'm not aware of any immediate bugs in qemu where a second runtime
evalution of the arguments to MIN() or MAX() causes a problem, but
proactively preventing such abuse is easier than falling prey to an
unintended case down the road. At any rate, here's the conversation
that sparked the current pat
This "bit" is a particular value of the page's MemAttr.
Signed-off-by: Richard Henderson
---
v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes.
---
target/arm/helper.c | 43 +++
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/target/arm/help
D1.10 specifies that exception handlers begin with tag checks overridden.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Only set if MTE feature present.
---
target/arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
Because the elements are non-sequential, we cannot eliminate many
tests straight away like we can for sequential operations. But
we often have the PTE details handy, so we can test for Tagged.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 285
target/arm/sve
This is DC GVA and DC GZVA, and the tag check for DC ZVA.
Signed-off-by: Richard Henderson
---
v2: Use allocation_tag_mem + memset.
v3: Require pre-cleaned addresses.
v6: Move DCZ block size assert to cpu realize.
Perform a tag check for DC ZVA.
---
target/arm/cpu.h | 4 +++-
targ
Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 47 +++
target/arm/sve_helper.c| 95 --
target/arm/translate-
Look up the physical address for the given virtual address,
convert that to a tag physical address, and finally return
the host address that backs it.
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 128
1 file changed, 128 insertions(+)
d
Signed-off-by: Richard Henderson
---
v5: Assign cs->num_ases to the final value first.
Downgrade to ID_AA64PFR1.MTE=1 if tag memory is not available.
v6: Add secure tag memory for EL3.
---
target/arm/cpu.h | 6 ++
hw/arm/virt.c| 52
ta
Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 98
target/arm/sve_helper.c| 98 ++--
target/arm/translate-s
We now implement all of the components of MTE, without actually
supporting any tagged memory. All MTE instructions will work,
trivially, so we can enable support.
Signed-off-by: Richard Henderson
---
v6: Delay user-only cpu reset bits to the user-only patch set.
---
target/arm/cpu64.c | 1 +
1
Replace existing uses of check_data_tbi in translate-a64.c that
perform a single logical memory access. Leave the helper blank
for now to reduce the patch size.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 1 +
target/arm/internals.h | 8
target/arm/translate-a64
There are a number of paths by which the TBI is still intact
for user-only in the SVE helpers.
Because we currently always set TBI for user-only, we do not
need to pass down the actual TBI setting from above, and we
can remove the top byte in the inner-most primitives, so that
none are forgotten.
We will shortly need this in mte_helper.c as well.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 9 +
target/arm/helper.c| 9 -
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c36fcb151b..7c9
We still need to handle tbi for user-only when mte is inactive.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 1 +
target/arm/translate-a64.c | 2 +-
target/arm/translate-sve.c | 6 --
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64
Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 58 ++
target/arm/internals.h | 6 +
target/arm/sve_helper.c| 218 ++
Fill out the stub that was added earlier.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 47 +++
target/arm/mte_helper.c | 126 +++-
2 files changed, 172 insertions(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/ar
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index e515646db2..4b3b879815 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translat
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 1 +
target/arm/sve_helper.c| 63 ++-
target/arm/translate-sve.c | 88 ++
3 files changed, 94 insertions(+), 58 deletions(-)
diff --git a/target/arm/helper-sve.h b/t
Replace existing uses of check_data_tbi in translate-a64.c that
perform multiple logical memory access. Leave the helper blank
for now to reduce the patch size.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 1 +
target/arm/translate-a64.h | 2 ++
target/arm/mte_helper.c
We will shortly need this in mte_helper.c as well.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 36
target/arm/helper.c| 36
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/target/arm/
Use a special helper for DC_ZVA, rather than the more
general mte_checkN. Leave the helper blank for now.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 1 +
target/arm/mte_helper.c| 106 +
target/arm/translate-a64.c | 16 +-
3 f
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Handle atomicity, require pre-cleaned address.
v6: Fix constant offset shift, non-checked address, use pre-computed ata.
---
target/arm/translate-a64.c | 29 ++---
1 file changed, 26 insertions(+), 3 dele
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 2 +
target/arm/sve_helper.c| 70 +++-
target/arm/translate-sve.c | 93 --
3 files changed, 109 insertions(+), 56 deletions(-)
diff --git a/target/arm/helper-sve.h b
Like the regular data cache flushes, these are nops within qemu.
Signed-off-by: Richard Henderson
---
v6: Split out and handle el0 cache ops properly.
---
target/arm/helper.c | 65 +
1 file changed, 65 insertions(+)
diff --git a/target/arm/helper.c b/
Signed-off-by: Richard Henderson
---
v3: Require pre-cleaned addresses.
v6: Check full mte enabled. Reorg the helpers.
---
target/arm/helper-a64.h| 3 ++
target/arm/translate.h | 2 +
target/arm/mte_helper.c| 84 ++
target/arm/translate-a64.c | 7
We need this to raise unaligned exceptions from user mode.
Signed-off-by: Richard Henderson
---
v6: Use EXCP_UNALIGNED for user-only and update cpu_loop.c.
---
linux-user/aarch64/cpu_loop.c | 7 ++
linux-user/arm/cpu_loop.c | 7 ++
target/arm/cpu.c | 2 +-
target/arm/
Fill out the stub that was added earlier.
Signed-off-by: Richard Henderson
---
v7: Fix page crossing test (szabolcs nagy).
---
target/arm/internals.h | 1 +
target/arm/mte_helper.c | 165 +++-
2 files changed, 165 insertions(+), 1 deletion(-)
diff --git a/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Fix extraction length.
---
target/arm/translate-a64.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7d0b7d5b58..0ee2ef
We can simplify our DC_ZVA if we recognize that the largest BS
that we actually use in system mode is 64. Let us just assert
that it fits within TARGET_PAGE_SIZE.
For DC_GVA and STZGM, we want to be able to write whole bytes
of tag memory, so assert that BS is >= 2 * TAG_GRANULE, or 32.
Signed-o
Signed-off-by: Richard Henderson
---
v6: Inline the operation.
---
target/arm/translate-a64.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a18d71ad98..7d0b7d5b58 100644
--- a/target/arm/translate-a64.c
+++ b/tar
Raise an exception if the given virtual memory is not accessible.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 ++
target/arm/op_helper.c | 16
target/arm/translate-a64.c | 13 +
3 files changed, 31 insertions(+)
diff --git a/target/arm/h
Signed-off-by: Richard Henderson
---
v2: Update to 00eac5.
Merge choose_random_nonexcluded_tag into helper_irg since
that pseudo function no longer exists separately.
v6: Remove obsolete logical/physical tag distinction;
implement inline for !ATA.
---
target/arm/helper-a64.h| 2 +
Signed-off-by: Richard Henderson
---
v2: Split out allocation_tag_mem. Handle atomicity of stores.
v3: Add X[t] input to these insns; require pre-cleaned addresses.
v5: Fix !32-byte aligned operation of st2g.
v6: Fix op2 extract, stg pre/post-index, stores vs sp, commentary;
use pre-computed
Signed-off-by: Richard Henderson
---
v2: Shift offset in translate; use extract32.
v6: Implement inline for !ATA.
---
target/arm/helper-a64.h| 1 +
target/arm/internals.h | 9 +
target/arm/mte_helper.c| 10 ++
target/arm/translate-a64.c | 36 +
Now that we know that the operation is on a single page,
we need not loop over pages while probing.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 94 +++--
1 file changed, 25 insertions(+), 69 deletions(-)
diff --git a/target/arm/helper-a64.c
This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO.
Signed-off-by: Richard Henderson
---
v3: Add GMID; add access_mte.
v4: Define only TCO at mte_insn_reg.
v6: Define RAZ/WI version of TCO at mte_insn_reg;
honor TID5 for GMID_EL1; fix TFS crn/crm; re
Cache the composite ATA setting.
Cache when MTE is fully enabled, i.e. access to tags are enabled
and tag checks affect the PE. Do this for both the normal context
and the UNPRIV context.
Signed-off-by: Richard Henderson
---
v3: Remove stub helper_mte_check; moved to a later patch.
v6: Add mte0
Emphasize that the is_jmp option exits to the main loop.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 14 --
target/arm/translate-a64.c | 8
target/arm/translate-vfp.inc.c | 2 +-
target/arm/translate.c | 12 ++--
4 files change
Add an option that writes back the PC, like DISAS_UPDATE_EXIT,
but does not exit back to the main loop.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 2 ++
target/arm/translate-a64.c | 3 +++
target/arm/translate.c | 4
3 files changed, 9 insertions(+)
diff --git a/
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7862bf502d..f2ead07ead 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2021,6 +2021,9 @@ static void scr_write(CPUARMSt
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 677584e5da..f8ac11e73b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3814,6 +3814,16 @@ static inline bool isar_feature_aa64_b
Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.
Version 6 was back in March:
https://lists.nongnu.org/archive/html/qemu-devel/2020-03/msg03790.html
Version 7 is a rebase on master, which now contains all prereqs.
In addition, two bugs fixed, pointed out by users of the branch.
I've done light testing against
https://git.kernel.org/pub/scm/lin
This does not attempt to rectify all of the res0 bits, but does
clear the mte bits when not enabled. Since there is no high-part
mapping of SCTLR, aa32 mode cannot write to these bits.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 23 +--
1 file changed, 17 inse
From: Chen Gang
Another DRM_IOCTL_* commands will be done later.
Signed-off-by: Chen Gang
---
configure | 10
linux-user/ioctls.h| 5 ++
linux-user/syscall.c | 117 +
linux-user/syscall_defs.h | 15 +
linux-user/s
On 2020/6/1 20:41, Peter Maydell wrote:
On Sat, 30 May 2020 at 10:22, Ying Fang wrote:
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cortex series cpu which has
the gernic
>
> >> + * Hash/Crypto Engine
> >> + * PCI-Express 1 Controller
> >> + * Graphic Display Controller
> >> + * PECI Controller
> >> + * MCTP Controller
> >> + * Mailbox Controller
> >> + * Virtual UART
> >
> > Uh what is that? :)
>
> It is the host console.
>
To explain a little more, a 16550-c
A bug in pylint 2.5.1 and 2.5.2 causes false positives for
relative imports. This version is pinned at 2.5.0 until a fix is
available.
Signed-off-by: John Snow
---
python/Pipfile | 1 +
python/Pipfile.lock | 123
2 files changed, 124 insertions
pipenv is a tool used for managing virtual environments with precisely
specified dependencies. It is separate from the dependencies listed in
setup.py, which are (by 'best practices') not supposed to be pinned.
Note that pipenv is not required to install or use this module; this is
just a convenie
Versions older than 3.6.0 do not appear to work with either pylint 2.5.0
or the type hint syntax in general.
Signed-off-by: John Snow
---
python/Pipfile | 1 +
python/Pipfile.lock | 39 ++-
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/p
0.730 appears to be about the oldest version that works with the
features we want, including nice human readable output (to make sure
iotest 297 passes), and type-parameterized Popen generics.
Signed-off-by: John Snow
---
python/Pipfile | 1 +
python/Pipfile.lock | 37 +
NB: I am choosing Python 3.6 here. Although our minimum requirement is
3.5, this code is used only by iotests (so far) under which we have been
using a minimum version of 3.6.
3.6 is being preferred here for variable type hint capability, which
enables us to use mypy for this package.
RFC: This u
move python/qemu/*.py to python/qemu/core/*.py.
To create a namespace package, the 'qemu' directory itself shouldn't
have module files in it. Thus, these files will go under a 'lib' package
directory instead.
Bolster the core/__init__.py file a little bit, Make the top-level
classes and functions
Add a short readme that explains the package hierarchy, which will be
visible while browsing the source on e.g. gitlab/github.
Signed-off-by: John Snow
---
python/qemu/README.rst | 8
1 file changed, 8 insertions(+)
create mode 100644 python/qemu/README.rst
diff --git a/python/qemu/RE
1 - 100 of 347 matches
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