Re: [PATCH] msix: add valid.accepts methods to check address

+-- On Mon, 1 Jun 2020, Michael S. Tsirkin wrote --+ | IMHO this is just messed up, memory core needs to guarantee this. | I'm working on a patch to do that. Okay. Thank you. -- Prasad J Pandit / Red Hat Product Security Team 8685 545E B54C 486B C6EB 271E E285 8B5A F050 DE8D

Re: ia-32/ia-64 fxsave64 instruction behavior when saving mmx

Hi Robert. Top-posting is difficult to read on technical lists, it's better to reply inline. Cc'ing the X86 FPU maintainers: ./scripts/get_maintainer.pl -f target/i386/fpu_helper.c Paolo Bonzini (maintainer:X86 TCG CPUs) Richard Henderson (maintainer:X86 TCG CPUs) Eduardo Habkost (maintainer:

Re: [PATCH] msix: add valid.accepts methods to check address

On Mon, Jun 01, 2020 at 10:44:54AM +0530, P J P wrote: > From: Prasad J Pandit > > While doing msi-x mmio operations, a guest may send an address > that leads to an OOB access issue. Add valid.accepts methods to > ensure that ensuing mmio r/w operation don't go beyond regions. > > Reported-by: R

Re: [PATCH] msix: add valid.accepts methods to check address

On Mon, Jun 1, 2020 at 8:02 AM Philippe Mathieu-Daudé wrote: > On 6/1/20 7:14 AM, P J P wrote: > > From: Prasad J Pandit > > > > While doing msi-x mmio operations, a guest may send an address > > that leads to an OOB access issue. Add valid.accepts methods to > > ensure that ensuing mmio r/w oper

Re: [PATCH] msix: add valid.accepts methods to check address

On 6/1/20 7:14 AM, P J P wrote: > From: Prasad J Pandit > > While doing msi-x mmio operations, a guest may send an address > that leads to an OOB access issue. Add valid.accepts methods to > ensure that ensuing mmio r/w operation don't go beyond regions. > Fixes: CVE-2020-x > Reported-by:

Re: [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init

On Fri, May 29, 2020 at 6:22 AM Alistair Francis wrote: > > The PMP is enabled by default via the "pmp" property so there is no need > for us to set it in the init function. As all CPUs have PMP support just > remove the set_feature() call in the CPU init functions. > > Signed-off-by: Alistair Fra

Re: [PATCH v5 03/11] target/riscv: Disable the MMU correctly

On Fri, May 29, 2020 at 6:22 AM Alistair Francis wrote: > > Previously if we didn't enable the MMU it would be enabled in the > realize() function anyway. Let's ensure that if we don't want the MMU we > disable it. We also don't need to enable the MMU as it will be enalbed typo: enabled > in rea

[PATCH] msix: add valid.accepts methods to check address

From: Prasad J Pandit While doing msi-x mmio operations, a guest may send an address that leads to an OOB access issue. Add valid.accepts methods to ensure that ensuing mmio r/w operation don't go beyond regions. Reported-by: Ren Ding Reported-by: Hanqing Zhao Reported-by: Anatoly Trosinenko

Re: [PATCH v4 4/4] docs: deprecated: Update the -bios documentation

On Fri, May 29, 2020 at 6:24 AM Alistair Francis wrote: > > Update the -bios deprecation documentation to describe the new > behaviour. > > Signed-off-by: Alistair Francis > --- > docs/system/deprecated.rst | 28 +--- > 1 file changed, 13 insertions(+), 15 deletions(-) >

Re: [PATCH v4 3/4] target/riscv: Drop support for ISA spec version 1.09.1

On Fri, May 29, 2020 at 6:24 AM Alistair Francis wrote: > > The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since > 4.1. It's not commonly used so let's remove support for it. > > Signed-off-by: Alistair Francis > --- > docs/system/deprecated.rst| 20 +-- > ta

Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs

On Fri, May 29, 2020 at 6:24 AM Alistair Francis wrote: > > Signed-off-by: Alistair Francis > Reviewed-by: Bin Meng > --- > docs/system/deprecated.rst | 33 ++--- > target/riscv/cpu.h | 7 --- > target/riscv/cpu.c | 28

[PATCH] migration: Count new_dirty instead of real_dirty

DIRTY_LOG_INITIALLY_ALL_SET feature is on the queue. This fixs the dirty rate calculation for this feature. After introducing this feature, real_dirty_pages is equal to total memory size at begining. This causing wrong dirty rate and false positive throttling. BTW, real dirty rate is not suitable

Re: [PATCH v1 11/12] util: Added tsan annotate for thread name.

On Fri, May 29, 2020 at 09:23:41 -0400, Robert Foley wrote: > This allows us to see the name of the thread in tsan > warning reports such as this: > > Thread T7 'CPU 1/TCG' (tid=24317, running) created by main thread at: > > Signed-off-by: Robert Foley Reviewed-by: Emilio G. Cota Thanks,

Re: [PATCH v4 05/11] rules.mak: Add base-arch() rule

On 5/22/20 9:37 AM, Philippe Mathieu-Daudé wrote: > + $(if $(call startwith,risc,$1),risc,\ Should be "riscv" not "risc". Especially the substitution. > + $(if $(call startwith,aarch64,$1),arm,\ > + $(if $(call startwith,x86_64,$1),i386

Re: Adding a RISC-V board to QEMU

On Sun, May 31, 2020 at 10:33 AM Yash Jain wrote: > > Hi, > I'm Yash. I'm a 3rd year college undergraduate student, currently interning > in IIT Madras in Project Shakti. We have built RISC-V boards and I have been > assigned the task to add these boards as machines to QEMU. > I am absolutely n

Re: [RFC v3 8/8] vhost-vdpa: introduce vhost-vdpa net client

On Fri, May 29, 2020 at 10:23 PM Eric Blake wrote: > > On 5/29/20 9:06 AM, Cindy Lu wrote: > > From: Tiwei Bie > > > > This patch set introduces a new net client type: vhost-vdpa. > > vhost-vdpa net client will set up a vDPA device which is specified > > by a "vhostdev" parameter. > > > > Co-auth

according what does the qemu know to exit current TB and find helper functions from environment?

Hi folks: a questions puzzles me during review the qemu code of 5.0.0, take vexpress emulation arm A9 on RTOS for example. the emulated RTOS has its own "printf" implementations, so during the qemu emulations, it would find helper_le_stl_mmu() store_helper()

Re: ia-32/ia-64 fxsave64 instruction behavior when saving mmx

Here's additional information. All of the remill tests of the legacy MMX instructions fail. These instructions work on 64-bit registers aliased with the lower 64-bits of the x87 fp80 registers. The tests fail because remill expects the fxsave64 instruction to deliver 16 bits of 1's (infinity o

Re: [PULL 0/2] m68k coldfire machine cleanup patches

On Sat, 30 May 2020 at 08:53, Thomas Huth wrote: > > Hi Peter, > > the following changes since commit c86274bc2e34295764fb44c2aef3cf29623f9b4b: > > Merge remote-tracking branch > 'remotes/stsquad/tags/pull-testing-tcg-plugins-270520-1' into staging > (2020-05-29 17:41:45 +0100) > > are availa

Re: [PATCH 0/8] hw: Fix some incomplete memory region size

On Sun, 31 May 2020 at 18:38, Philippe Mathieu-Daudé wrote: > > memory_region_set_size() handle the 16 Exabytes limit by > special-casing the UINT64_MAX value. > This is not a problem for the 32-bit maximum, 4 GiB, but > in some places we incorrectly use UINT32_MAX instead of > 4 GiB, and end up m

Re: [PULL v3 00/11] bitmaps patches for 2020-05-26

On Thu, 28 May 2020 at 19:19, Eric Blake wrote: > > The following changes since commit a20ab81d22300cca80325c284f21eefee99aa740: > > Merge remote-tracking branch > 'remotes/huth-gitlab/tags/pull-request-2020-05-28' into staging (2020-05-28 > 16:18:06 +0100) > > are available in the Git reposit

Re: [PATCH 4/6] exec/cpu-common: Do not restrict CPU to 32-bit memory access maximum

On Sun, 31 May 2020 at 18:54, Philippe Mathieu-Daudé wrote: > > Most CPUs can do 64-bit operations. Update the CPUReadMemoryFunc > and CPUWriteMemoryFunc prototypes. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/exec/cpu-common.h | 4 ++-- > hw/usb/hcd-musb.c | 12 ++

Re: [PATCH 3/6] hw/sd/allwinner-sdhost: Do DMA accesses via DMA address space

On 5/31/20 7:54 PM, Philippe Mathieu-Daudé wrote: > The DMA operations should not use the CPU address space, but > the DMA address space. Add support for a DMA address space, > and replace the cpu_physical_memory API calls by equivalent > dma_memory_read/write calls. > > Signed-off-by: Philippe Ma

[Bug 1881506] [NEW] TCG doesn't support a lot of features that should be supported

Public bug reported: This is quite odd, and I'm not sure about how to get around it. I'm writing an OS in Rust and require APIC support. When I boot my kernel with qemu-system-x86_64, however, it dumps out a [lot] of warnings; it claims that TCG doesn't support FMA, X2APIC, AVX, F16C, AVX2, RDS

Re: [RFC PATCH 6/6] memory: Use CPU register size as default access_size_max

On Sun, 31 May 2020 at 18:54, Philippe Mathieu-Daudé wrote: > > Do not restrict 64-bit CPU to 32-bit max access by default. > > Signed-off-by: Philippe Mathieu-Daudé > --- > RFC because this probably require an audit of all devices > used on 64-bit targets. > But if we find such problematic devic

Re: [PATCH 5/6] exec: Restrict 32-bit CPUs to 32-bit address space

On Sun, 31 May 2020 at 18:54, Philippe Mathieu-Daudé wrote: > > It is pointless to have 32-bit CPUs see a 64-bit address > space, when they can only address the 32 lower bits. > > Only create CPU address space with a size it can address. > This makes HMP 'info mtree' command easier to understand >

[Bug 1377095] Re: KVM guest VM does not reattach a throughpassed USB printer from Host after switching printer off and on

Thanks Thomas for Your suggestion. Unfortunately I cannot achieve the reconnection: KVM runs with following parameters: -usb -device usb-host,vendorid=0x04e8,productid=0x3242,id=drucker -monitor unix:qemu-monitor-socket,server,nowait With the Unix socket, I can now pipe commands to the qemu moni

Re: [PATCH 0/6] exec/memory: Rework some address and access size limits

Patchew URL: https://patchew.org/QEMU/20200531175425.10329-1-f4...@amsat.org/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/

[PATCH 5/6] exec: Restrict 32-bit CPUs to 32-bit address space

It is pointless to have 32-bit CPUs see a 64-bit address space, when they can only address the 32 lower bits. Only create CPU address space with a size it can address. This makes HMP 'info mtree' command easier to understand (on 32-bit CPUs). Signed-off-by: Philippe Mathieu-Daudé --- This is par

[PATCH 4/6] exec/cpu-common: Do not restrict CPU to 32-bit memory access maximum

Most CPUs can do 64-bit operations. Update the CPUReadMemoryFunc and CPUWriteMemoryFunc prototypes. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-common.h | 4 ++-- hw/usb/hcd-musb.c | 12 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/e

[PATCH 1/6] target/s390x/mmu_helper: Use address_space_rw() in place

In an effort to remove the cpu_physical_memory_rw() API, update s390_cpu_virt_mem_rw() to use a more recent address_space_rw() API. Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/mmu_helper.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/mmu_helpe

[RFC PATCH 6/6] memory: Use CPU register size as default access_size_max

Do not restrict 64-bit CPU to 32-bit max access by default. Signed-off-by: Philippe Mathieu-Daudé --- RFC because this probably require an audit of all devices used on 64-bit targets. But if we find such problematic devices, they should instead enforce their access_size_max = 4 rather than expect

[PATCH 0/6] exec/memory: Rework some address and access size limits

These patches are extracted from a bigger series which - remove generic ISA space, restricting it to the hw that really has it (mostly PCI-ISA bridges) - allow QTest/GDB to use any address space - make I/O address space target-specific (only X86 and AVR have a CPU connected to it) - better hand

[PATCH 2/6] hw/dma/rc4030: Use DMA address space to do DMA accesses

The DMA device should not use the CPU address space to do its operation, but its own address space. Replace cpu_physical_memory_write() by dma_memory_read() since we already have the DMA address space available. Signed-off-by: Philippe Mathieu-Daudé --- hw/dma/rc4030.c | 3 ++- 1 file changed, 2

[PATCH 3/6] hw/sd/allwinner-sdhost: Do DMA accesses via DMA address space

The DMA operations should not use the CPU address space, but the DMA address space. Add support for a DMA address space, and replace the cpu_physical_memory API calls by equivalent dma_memory_read/write calls. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/allwinner-sdhost.h | 4

[PATCH 8/8] target/i386/cpu: Use the IEC binary prefix definitions

IEC binary prefixes ease code review: the unit is explicit. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3733d9a279..33ce4861fb 100644 --- a/target/i386/cpu.c +++ b/targ

[PATCH 7/8] hw/i386/xen/xen-hvm: Use the IEC binary prefix definitions

IEC binary prefixes ease code review: the unit is explicit. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/xen/xen-hvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 82ece6b9e7..679d74e6a3 100644 --- a/hw/i386/xen/xe

[PATCH 2/8] hw/pci-host/prep: Correct RAVEN bus bridge memory region size

memory_region_set_size() handle the 16 Exabytes limit by special-casing the UINT64_MAX value. This is not a problem for the 32-bit maximum, 4 GiB. By using the UINT32_MAX value, the bm-raven MemoryRegion ends up missing 1 byte: $ qemu-system-ppc -M prep -S -monitor stdio -usb memory-region: bm

[PATCH 4/8] hw/pci/pci_bridge: Use the IEC binary prefix definitions

IEC binary prefixes ease code review: the unit is explicit. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci/pci_bridge.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 3ba3203f72..3789c17edc 100644 --- a/hw/pci/pci_bridge.

[PATCH 1/8] hw/arm/aspeed: Correct DRAM container region size

memory_region_set_size() handle the 16 Exabytes limit by special-casing the UINT64_MAX value. This is not a problem for the 32-bit maximum, 4 GiB. By using the UINT32_MAX value, the aspeed-ram-container MemoryRegion ends up missing 1 byte: $ qemu-system-arm -M ast2600-evb -S -monitor stdio (qemu

[PATCH 5/8] hw/pci-host: Use the IEC binary prefix definitions

IEC binary prefixes ease code review: the unit is explicit. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/i440fx.c| 3 ++- hw/pci-host/q35.c | 2 +- hw/pci-host/versatile.c | 5 +++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/i440fx.c b/hw/pci-h

[PATCH 3/8] hw/pci/pci_bridge: Correct pci_bridge_io memory region size

memory_region_set_size() handle the 16 Exabytes limit by special-casing the UINT64_MAX value. This is not a problem for the 32-bit maximum, 4 GiB. By using the UINT32_MAX value, the pci_bridge_io MemoryRegion ends up missing 1 byte: (qemu) info mtree memory-region: pci_bridge_io 00

[PATCH 6/8] hw/hppa/dino: Use the IEC binary prefix definitions

IEC binary prefixes ease code review: the unit is explicit. Signed-off-by: Philippe Mathieu-Daudé --- hw/hppa/dino.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c index 2b1b38c58a..7290f23962 100644 --- a/hw/hppa/dino.c +++ b/hw/hppa/dino

[PATCH 0/8] hw: Fix some incomplete memory region size

memory_region_set_size() handle the 16 Exabytes limit by special-casing the UINT64_MAX value. This is not a problem for the 32-bit maximum, 4 GiB, but in some places we incorrectly use UINT32_MAX instead of 4 GiB, and end up missing 1 byte in the memory region. This series fixes the cases I encoun

Adding a RISC-V board to QEMU

Hi, I'm Yash. I'm a 3rd year college undergraduate student, currently interning in IIT Madras in Project Shakti. We have built RISC-V boards and I have been assigned the task to add these boards as machines to QEMU. I am absolutely new to this and have no idea how to go about this. Please help me

Re: [PATCH-for-5.0] gdbstub: Use correct address space with Qqemu.PhyMemMode packet

On Sun, 31 May 2020 at 17:42, Jon Doron wrote: > > On 31/05/2020, Philippe Mathieu-Daudé wrote: > >On 3/30/20 6:41 PM, Peter Maydell wrote: > >> PS: do we have any documentation of this new command ? > >> ab4752ec8d9 has the implementation but no documentation... > > > >Jon, do you have documentat

[PULL 23/25] tests/acceptance: allow console interaction with specific VMs

From: Pavel Dovgalyuk Console interaction in avocado scripts was possible only with single default VM. This patch modifies the function parameters to allow passing a specific VM as a parameter to interact with it. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Willian Rampazzo Reviewed-by: Alex B

Re: [PATCH 00/10] Add RX hardware emulation

On 5/31/20 6:24 PM, Yoshinori Sato wrote: > Hello. > > This series add to hardware emulation module for RX target. > > Details below. > Interrupt controller, 8bit timer, 16bit comapare match timer and > SCI is RX62N integrated peripheral. > rx-virt - RX62N MCU and external RAM. It like gdb simula

[PULL 22/25] tests/acceptance/migration.py: Wait for both sides

From: "Dr. David Alan Gilbert" When the source finishes migration the destination will still be receiving the data sent by the source, so it might not have quite finished yet, so won't quite have reached 'completed'. This lead to occasional asserts in the next few checks. After the source has fi

[PULL 25/25] tests/acceptance: refactor boot_linux to allow code reuse

From: Pavel Dovgalyuk This patch moves image downloading functions to the separate class to allow reusing them from record/replay tests. Signed-off-by: Pavel Dovgalyuk Tested-by: Philippe Mathieu-Daudé Message-Id: <159073593167.20809.17582679291556188984.stgit@pasha-ThinkPad-X280> Signed-off-b

Re: [PATCH-for-5.0] gdbstub: Use correct address space with Qqemu.PhyMemMode packet

On 31/05/2020, Philippe Mathieu-Daudé wrote: On 3/30/20 6:41 PM, Peter Maydell wrote: On Mon, 30 Mar 2020 at 17:21, Philippe Mathieu-Daudé wrote: On 3/30/20 6:08 PM, Peter Maydell wrote: On Mon, 30 Mar 2020 at 16:30, Philippe Mathieu-Daudé wrote: Since commit 3f940dc98, we added support fo

[PULL 21/25] tests/migration/guestperf: Use Python 3 interpreter

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: John Snow Reviewed-by: Kevin Wolf Message-Id: <20200512103238.7078-7-phi...@redhat.com> --- tests/migration/guestperf-batch.py | 2 +- tests/migration/guestperf-plot.py | 2 +- tests/migration/guestperf.py | 2 +- 3 files changed, 3 inse

[PULL 11/25] python/qemu: delint; add flake8 config

From: John Snow Mostly, ignore the "no bare except" rule, because flake8 is not contextual and cannot determine if we re-raise. Pylint can, though, so always prefer pylint for that. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200528222129.23826-5-js...@redhat.co

[PULL 19/25] tests/vm: Add ability to select QEMU from current build

From: Robert Foley Added a new special variable QEMU_LOCAL=1, which will indicate to take the QEMU binary from the current build. Signed-off-by: Robert Foley Reviewed-by: Peter Puhov Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-Id: <

[PULL 24/25] tests/acceptance: refactor boot_linux_console test to allow code reuse

From: Pavel Dovgalyuk This patch splits code in BootLinuxConsole class into two different classes to allow reusing it by record/replay tests. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Alex Bennée Tested-by: Philippe Mathieu-Daudé Message-Id: <159073588490.20809.13942096070255577558.stgit@pa

[PULL 20/25] tests/vm: allow wait_ssh() to specify command

From: Robert Foley This allows for waiting for completion of arbitrary commands. Signed-off-by: Robert Foley Reviewed-by: Peter Puhov Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-Id: <20200529203458.1038-7-robert.fo...@linaro.org> Si

[PULL 08/25] python/qemu/machine: add kill() method

From: Vladimir Sementsov-Ogievskiy Add method to hard-kill vm, without any quit commands. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Andrey Shinkevich Message-Id: <20200217150246.29180-19-vsement...@virtuozzo.com> Signed-off-by: Philippe Mathieu-Daudé --- python/qemu/machine.py

[PULL 18/25] tests/vm: Pass --debug through for vm-boot-ssh

From: Robert Foley This helps debug issues that occur during the boot sequence. Signed-off-by: Robert Foley Reviewed-by: Peter Puhov Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-Id: <20200529203458.1038-5-robert.fo...@linaro.org> Sig

[PULL 17/25] python/qemu/qtest: Check before accessing _qtest

From: John Snow It can be None; so add assertions or exceptions where appropriate to guard the access accordingly. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200514055403.18902-30-js...@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- python/qemu/qtest.p

[PULL 16/25] python/qemu/qmp: assert sockfile is not None

From: John Snow In truth, if you don't do this, you'll just get a TypeError exception. Now, you'll get an AssertionError. Is this tangibly better? No. Does mypy complain less? Yes. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200514055403.18902-21-js...@redhat.c

[PULL 06/25] scripts/qmp: Fix shebang and imports

From: John Snow There's more wrong with these scripts; They are in various stages of disrepair. That's beyond the scope of this current patchset. This just mechanically corrects the imports and the shebangs, as part of ensuring that the python/qemu/lib refactoring didn't break anything needlessl

[PULL 13/25] python/qemu: fix socket.makefile() typing

From: John Snow Note: A bug in typeshed (https://github.com/python/typeshed/issues/3977) misinterprets the type of makefile(). Work around this by explicitly stating that we are opening a text-mode file. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200514055403.

[PULL 15/25] python/qemu/qmp: use True/False for non/blocking modes

From: John Snow The type system doesn't want integers. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200514055403.18902-15-js...@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- python/qemu/qmp.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) d

[PULL 12/25] python/qemu: remove Python2 style super() calls

From: John Snow Use the Python3 style instead. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200514055403.18902-12-js...@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- python/qemu/machine.py | 2 +- python/qemu/qtest.py | 15 +++ 2 files ch

[PULL 05/25] scripts/modules/module_block: Use Python 3 interpreter & add pseudo-main

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: John Snow Reviewed-by: Kevin Wolf Message-Id: <20200512103238.7078-6-phi...@redhat.com> --- scripts/modules/module_block.py | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/scripts/modules/modu

[PULL 10/25] python/qemu: delint and add pylintrc

From: John Snow Bring our these files up to speed with pylint 2.5.0. Add a pylintrc file to formalize which pylint subset we are targeting. The similarity ignore is there to suppress similarity reports across imports, which for typing constants, are going to trigger this report erroneously. Sig

[PULL 14/25] python/qemu: Adjust traceback typing

From: John Snow mypy considers it incorrect to use `bool` to statically return false, because it will assume that it could conceivably return True, and gives different analysis in that case. Use a None return to achieve the same effect, but make mypy happy. Note: Pylint considers function signat

[PULL 02/25] scripts/qemu-gdb: Use Python 3 interpreter

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: John Snow Reviewed-by: Kevin Wolf Message-Id: <20200512103238.7078-3-phi...@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- scripts/qemu-gdb.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dif

[PULL 04/25] scripts/kvm/vmxcap: Use Python 3 interpreter and add pseudo-main()

Signed-off-by: Philippe Mathieu-Daudé Acked-by: Paolo Bonzini Reviewed-by: John Snow Reviewed-by: Kevin Wolf Message-Id: <20200512103238.7078-5-phi...@redhat.com> --- scripts/kvm/vmxcap | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/scripts/kvm/vmxcap b/scripts/kvm/

[PULL 07/25] python: remove more instances of sys.version_info

From: John Snow We guarantee 3.5+ everywhere; remove more dead checks. In general, try to avoid using version checks and instead prefer to attempt behavior when possible. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200514035230.25756-1-js...@redhat.com> Signed-o

[PULL 00/25] python-next patches for 2020-05-31

u.git tags/python-next-20200531 for you to fetch changes up to 1c80c87c8c2489e4318c93c844aa29bc1d014146: tests/acceptance: refactor boot_linux to allow code reuse (2020-05-31 18:25= :31 +0200) Python queue: * migration acceptanc

[PULL 03/25] scripts/qmp: Use Python 3 interpreter

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: John Snow Reviewed-by: Kevin Wolf Message-Id: <20200512103238.7078-4-phi...@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- scripts/qmp/qom-get | 2 +- scripts/qmp/qom-list | 2 +- scripts/qmp/qom-set | 2

[PULL 01/25] scripts/qemugdb: Remove shebang header

From: Philippe Mathieu-Daudé These scripts are loaded as plugin by GDB (and they don't have any __main__ entry point). Remove the shebang header. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alex Bennée Reviewed-by: John Snow Reviewed-by: Kevin Wolf Message-Id: <20200512103238.7078-2-phi.

[PULL 09/25] python/qemu/machine: remove logging configuration

From: John Snow Python 3.5 and above do not print a warning when logging is not configured. As a library, it's best practice to leave logging configuration to the client executable. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200514055403.18902-22-js...@redhat.c

[PATCH 04/10] hw/char: Renesas SCI module.

This module supported SCI / SCIa / SCIF. Hardware manual. SCI / SCIF https://www.renesas.com/us/en/doc/products/mpumcu/001/r01uh0457ej0401_sh7751.pdf SCIa https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/char/

[PATCH 08/10] hw/char: remove sh_serial.c

SH4 SCI module convert to renesas_sci.c. This file is obsolute. Signed-off-by: Yoshinori Sato --- hw/char/sh_serial.c | 431 1 file changed, 431 deletions(-) delete mode 100644 hw/char/sh_serial.c diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial

[PATCH 05/10] hw/rx: RX MCU and target

rx62n - RX62N MCU. rx-virt - RX QEMU virtual target. This has the same specifications as the gdb simulator. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx.h| 7 ++ include/hw/rx/rx62n.h | 91 hw/rx/rx-virt.c | 143 + hw/rx/rx62n.c

[PATCH 02/10] hw/timer: Renesas 8bit timer module.

8bit or 16bit timer. This implementation support only internal clock mode. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_8timer.h | 61 hw/timer/renesas_8timer.c

[PATCH 03/10] hw/timer: Renesas TMU/CMT module.

TMU - SH4 Timer module. CMT - Compare and match timer used by some Renesas MCUs. The two modules have similar interfaces and have been merged. Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_timer.h | 59 + hw/timer/renesas_timer.c | 421 +++

[PATCH 01/10] hw/intc: RX62N interrupt controller (ICUa)

This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/intc/rx_icu.h | 56 ++ hw/intc/rx_icu.c | 379 +++ hw/

[PATCH 07/10] hw/sh4: Convert renesas_sci.

Using new implementation SCI module. Signed-off-by: Yoshinori Sato --- include/hw/sh4/sh.h | 11 --- hw/sh4/sh7750.c | 45 + hw/sh4/Kconfig | 1 + 3 files changed, 42 insertions(+), 15 deletions(-) diff --git a/include/hw/sh4/sh.h b/

[PATCH 06/10] Add rx-softmmu

Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Yoshinori Sato Message-Id: <20190607091116.49044-17-ys...@users.sourceforge.jp> Signed-off-by: Richard Henderson pick ed65c02993 target/rx: Add RX to SysEmuTarget pick 01372568ae tests: Add rx to machine-none-t

[PATCH 10/10] hw/timer: remove sh_timer.c

SH4 TMU using new module. This file is obsolute. Signed-off-by: Yoshinori Sato --- hw/timer/sh_timer.c | 341 1 file changed, 341 deletions(-) delete mode 100644 hw/timer/sh_timer.c diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c deleted file

[PATCH 00/10] Add RX hardware emulation

Hello. This series add to hardware emulation module for RX target. Details below. Interrupt controller, 8bit timer, 16bit comapare match timer and SCI is RX62N integrated peripheral. rx-virt - RX62N MCU and external RAM. It like gdb simulator. The compare match timer has a CPU interface similar

[PATCH 09/10] hw/sh4: Convert to renesas_timer.c

Using unified TMU/CMT module. Signed-off-by: Yoshinori Sato --- include/hw/sh4/sh.h| 10 - hw/sh4/sh7750.c| 47 +- hw/sh4/Kconfig | 2 +- hw/timer/Makefile.objs | 1 - 4 files changed, 38 insertions(+), 22 deletions(-) diff -

Re: [PATCH-for-5.0] gdbstub: Use correct address space with Qqemu.PhyMemMode packet

On 3/30/20 6:41 PM, Peter Maydell wrote: > On Mon, 30 Mar 2020 at 17:21, Philippe Mathieu-Daudé > wrote: >> On 3/30/20 6:08 PM, Peter Maydell wrote: >>> On Mon, 30 Mar 2020 at 16:30, Philippe Mathieu-Daudé >>> wrote: Since commit 3f940dc98, we added support for vAttach packet to

Re: [PATCH v3 00/11] Record/replay acceptance tests

On 5/29/20 9:04 AM, Pavel Dovgalyuk wrote: > The following series adds record/replay tests to the acceptance group. > Test pass successfully with the latest submitted record/replay fixes: > - replay: notify the main loop when there are no instructions > - replay: synchronize on every virtual time

[PATCH v2 0/1] Check for page crossings in use_goto_tb() for rx target

Hi, After discussion on v1 of this series, the conclusion was that page crossings must be done for all targets and for both user and system mode. This series deals with rx target, that is the only target that does not perform this check in system mode. In version two of this series, the original

[PATCH v2 1/1] target/rx: Check for page crossings in use_goto_tb()

Add the page crossings check in use_goto_tb(). If this check is not applied, a number of bugs may occasionally occur during target rx system mode emulation. Also, this check is needed in user mode related to emulation of system call mmap(). rx target does not currently support user mode, but it is

[Bug 1881450] Re: Emulation of a math function fails for m68k Linux user mode

Fix available. Execution doesn't fail anymore: Profiling function expm1f(): Elapsed time: 41 ms Control result: 71805.108342 Control result matches real hardware one: Profiling function expm1f(): Elapsed time: 2152 ms Control result: 71805.108342 ** Changed in: qemu

[Bug 1881450] Re: Emulation of a math function fails for m68k Linux user mode

** Patch added: "0001-target-m68k-implement-opcode-fetoxm1x.patch" https://bugs.launchpad.net/qemu/+bug/1881450/+attachment/5379012/+files/0001-target-m68k-implement-opcode-fetoxm1x.patch -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to

[PATCH] target/m68k: implement opcode fetoxm1

Example provided in the launchpad bug fails with: qemu: uncaught target signal 4 (Illegal instruction) - core dumped Illegal instruction (core dumped) It appears fetoxm1 is not implemented: IN: expm1f 0x85cc: fetoxm1x %fp2,%fp0 Disassembler disagrees with translator over instr

Re: [PATCH] target/m68k: implement fmove.l #,FPCR

Hi Laurent! On 5/31/20 2:09 PM, Laurent Vivier wrote: > I guess you are using my q800-dev branch? That's what I initially did, then I pulled from upstream. > In this branch, there is an attempt to manage unnormalized numbers that > seems to trigger this lock up. > > You can either use master +

[Bug 1881450] Re: Emulation of a math function fails for m68k Linux user mode

Tracing gives me: IN: expm1f 0x85cc: fetoxm1x %fp2,%fp0 Disassembler disagrees with translator over instruction decoding Please report this to qemu-devel@nongnu.org (gdb) x/2hx 0x85cc 0x85cc: 0xf200 0x0808 The instruction is not implemented in qemu. I fix that. -- You receive

Re: [PATCH] target/m68k: implement fmove.l #,FPCR

Le 31/05/2020 à 13:23, John Paul Adrian Glaubitz a écrit : > Hi Laurent! > > On 5/31/20 1:02 PM, Laurent Vivier wrote: >> The immediate value mode was ignored and instruction execution >> ends to an invalid access mode. >> >> This was found running 'R' that set FPSR to 0 at startup with >> a 'fmov

Re: [PATCH v3 10/11] tests/acceptance: refactor boot_linux to allow code reuse

On 5/29/20 9:05 AM, Pavel Dovgalyuk wrote: > This patch moves image downloading functions to the separate class to allow > reusing them from record/replay tests. > > Signed-off-by: Pavel Dovgalyuk > --- > 0 files changed > > diff --git a/tests/acceptance/boot_linux.py b/tests/acceptance/boot_li

Re: [PATCH] tests/acceptance/migration.py: Wait for both sides

On 5/28/20 1:24 PM, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > When the source finishes migration the destination will still be > receiving the data sent by the source, so it might not have quite > finished yet, so won't quite have reached 'completed'. > This lead to

Re: [PATCH v8 00/12] tests/vm: Add support for aarch64 VMs

On 5/29/20 10:34 PM, Robert Foley wrote: > This is version 8 of the patch series to > add support for aarch64 VMs in the vm-build infrastructure. > - Ubuntu 18.04 aarch64 VM > - CentOS 8 aarch64 VM > > v7: https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg05286.html > > Changes in v8: >

Re: [PATCH v8 12/12] tests/vm: Add workaround to consume console

On 5/29/20 10:34 PM, Robert Foley wrote: > This adds support to basevm.py so that we always > drain the console chars. This makes use of > support added in an earlier commit that allows > QEMUMachine to use the ConsoleSocket. > > This is a workaround we found was needed since > there is a known i

Re: [PATCH v8 06/12] tests/vm: allow wait_ssh() to specify command

On 5/29/20 10:34 PM, Robert Foley wrote: > This allows for waiting for completion of arbitrary commands. > > Signed-off-by: Robert Foley > Reviewed-by: Peter Puhov > Reviewed-by: Alex Bennée > --- > tests/vm/basevm.py | 14 +++--- > 1 file changed, 7 insertions(+), 7 deletions(-) > >

  1   2   >