On 19.05.2020 18:42, Philippe Mathieu-Daudé wrote:
On 5/19/20 12:38 PM, Pavel Dovgalyuk wrote:
On 19.05.2020 13:32, Alex Bennée wrote:
Pavel Dovgalyuk writes:
On 19.05.2020 11:11, Alex Bennée wrote:
Pavel Dovgalyuk writes:
On 18.05.2020 18:56, Alex Bennée wrote:
Philippe Mathieu-Daud
On 5/20/20 8:27 AM, Markus Armbruster wrote:
> I figure this replaces my "[PATCH 05/24] aspeed: Don't create unwanted
> "cortex-a7-arm-cpu" devices". Correct?
>
> Let's mention it gets rid of unrealized CPUs then. Let me try.
>
> Cédric Le Goater writes:
>
>> Commit ece09beec457 ("aspeed: int
On 19/05/20 16:54, Markus Armbruster wrote:
> Paolo recently suggested "to move the bus argument (and thus
> qdev_set_parent_bus) to qdev_init"[1], and that it "would be quite
> large but hopefully scriptable"[2]. Nerd sniped!
>
> The series is big, but at least the bigger patches are all mechani
On 19/05/20 16:55, Markus Armbruster wrote:
> So far, qdev_realize() supports only devices that plug into a bus:
> argument @bus cannot be null. Extend it to support bus-less devices,
> too.
>
> qdev_realize_and_unref() remains restricted, because its reference
> counting would become rather conf
Cédric Le Goater writes:
> The AST2400 and AST2500 SoCs have two MACs but only the first MAC0 is
> active on the Aspeed machines using these SoCs. The AST2600 has four
> MACs. The AST2600 EVB machine activates MAC1, MAC2 and MAC3 and the
> Tacoma BMC machine activates MAC2.
>
> Introduce a bit-fi
On 19/05/20 16:55, Markus Armbruster wrote:
> expression bus, type_name, dev;
> @@
> -dev = qdev_create(bus, type_name);
> +dev = qdev_new(type_name);
> ...
> -qdev_init_nofail(dev);
> +qdev_realize_and_unref(dev, bus, &error_fatal);
>
> The first
I figure this replaces my "[PATCH 05/24] aspeed: Don't create unwanted
"cortex-a7-arm-cpu" devices". Correct?
Let's mention it gets rid of unrealized CPUs then. Let me try.
Cédric Le Goater writes:
> Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
> per machine") was a co
On 19/05/20 16:55, Markus Armbruster wrote:
> @@ -493,6 +493,11 @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error
> **errp)
> return !err;
> }
>
> +void qdev_unrealize(DeviceState *dev)
> +{
> +object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
> +}
> +
>
On 19/05/20 16:54, Markus Armbruster wrote:
> +
> +object_ref(OBJECT(dev));
> +object_property_set_bool(OBJECT(dev), true, "realized", &err);
> +if (err) {
> +error_propagate_prepend(errp, err,
> +"Initialization of device %s failed: ",
> +
20.05.2020 00:48, Eric Blake wrote:
On 5/19/20 4:13 PM, Vladimir Sementsov-Ogievskiy wrote:
19.05.2020 23:41, Eric Blake wrote:
On 5/19/20 2:54 PM, Vladimir Sementsov-Ogievskiy wrote:
bdrv_co_block_status_above has several problems with handling short
backing files:
1. With want_zeros=true, i
On 20/05/2020 01.06, John Snow wrote:
>
>
> On 5/19/20 5:04 AM, Daniel P. Berrangé wrote:
>> On Mon, May 18, 2020 at 03:56:36PM -0400, John Snow wrote:
>>>
>>>
>>> On 5/15/20 6:23 AM, Daniel P. Berrangé wrote:
On Fri, May 15, 2020 at 12:11:17PM +0200, Thomas Huth wrote:
> On 07/04/2020 1
On 5/19/20 11:31 PM, Alistair Francis wrote:
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/opentitan.h | 13 +
hw/riscv/opentitan.c | 24 ++--
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/include/hw/risc
On 5/19/20 11:31 PM, Alistair Francis wrote:
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/opentitan.h | 3 +++
hw/riscv/opentitan.c | 19 +--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b
On 5/19/20 11:31 PM, Alistair Francis wrote:
Currently every c file that includes boot.h also includes loader.h
before it. Which is why the build works fine. We should be able to
include just boot.h though so this is a small fixup to allow that.
What about:
'As the functions declared in this h
On 5/19/20 8:56 PM, Richard Henderson wrote:
Executable guest pages are never directly executed by
the host, but do need to be readable for translation.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/linux-user/
On 5/19/20 10:02 PM, Zhang Chen wrote:
From: Derek Su
The patch is to fix the "pkt" memory leak in packet_enqueue().
The allocated "pkt" needs to be freed if the colo compare
primary or secondary queue is too big.
Replace the error_report of full queue with a trace event.
Signed-off-by: Derek
On Mon, May 18, 2020 at 8:34 AM Peter Maydell
wrote:
> On Tue, 12 May 2020 at 07:50, Paul Zimmerman wrote:
> >
>
> > +static void dwc2_reset(DeviceState *dev)
> > +{
> > +DWC2State *s = DWC2_USB(dev);
> > +int i;
> > +
> > +trace_usb_dwc2_reset();
> > +timer_del(s->frame_timer);
On 5/19/20 7:37 PM, LIU Zhiwei wrote:
> On 2020/5/12 1:40, Richard Henderson wrote:
>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>> + # sequence of li rd, 0x1234567887654321
>>> + #
>>> + # 0: 002471b7 lui rd,0x247
>>> + # 4: 8ad1819b addiw rd,rd,
On 5/19/20 7:41 PM, LIU Zhiwei wrote:
>> Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
>> sp, and not gp and tp as well?
> When I test the patch set, I find gp and tp will be the same in slave and
> master，
> so they can be used as source register.
Ah, try again wit
On 5/19/20 10:02 PM, Zhang Chen wrote:
From: Lukas Straub
This will be needed in the next patch.
Can you reword to something clearer, maybe:
"To be able to convert compare_chr_send to a coroutine in the
next commit, use qemu_co_sleep_ns if in coroutine."
Reviewed-by: Philippe Mathieu-Daudé
On Tue, May 19, 2020 at 9:26 PM Markus Armbruster wrote:
>
> Alistair Francis writes:
>
> > On Tue, May 19, 2020 at 8:11 AM Markus Armbruster wrote:
> >>
> >> We commonly plug devices into their bus right when we create them,
> >> like this:
> >>
> >> dev = qdev_create(bus, type_name);
> >>
On Mon, May 18, 2020 at 09:46:36 -0400, Robert Foley wrote:
> We re-ran the numbers with the latest re-based series.
>
> We used an aarch64 ubuntu VM image with a host CPU:
> Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz, 2 CPUs, 10 cores/CPU,
> 20 Threads/CPU. 40 cores total.
>
> For the bare hard
Patchew URL:
https://patchew.org/QEMU/20200519200207.17773-1-chen.zh...@intel.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
ex
Alistair Francis writes:
> On Tue, May 19, 2020 at 8:11 AM Markus Armbruster wrote:
>>
>> We commonly plug devices into their bus right when we create them,
>> like this:
>>
>> dev = qdev_create(bus, type_name);
>>
>> Note that @dev is a weak reference. The reference from @bus to @dev
>> is
Hi, Any update about this issue?
Thanks,
Feng Li
Li Feng 于2020年5月14日周四 下午11:49写道：
>
> Dr. David Alan Gilbert 于2020年5月14日周四 下午11:31写道：
> >
> > * Li Feng (fen...@smartx.com) wrote:
> > > Dr. David Alan Gilbert 于2020年5月14日周四 下午11:16写道：
> > > >
> > > > * Li Feng (fen...@smartx.com) wrote:
> > > >
@igor Did you get a chance to look?
On May 15, 2020, 22:57 +0530, Ani Sinha , wrote:
> A new option "acpi-pci-hotplug" is introduced for PIIX which will
> globally disable hot-plugging of both hot plugged and
> cold plugged PCI devices. This will prevent
> hot-plugging and hot un-plugging of device
On Mon, May 18, 2020 at 11:43:09AM +0530, Kirti Wankhede wrote:
<...>
> +
> +static int vfio_save_buffer(QEMUFile *f, VFIODevice *vbasedev)
> +{
> +VFIOMigration *migration = vbasedev->migration;
> +VFIORegion *region = &migration->region;
> +uint64_t data_offset = 0, data_size = 0;
>
On Tue, May 19, 2020 at 10:58:04AM -0600, Alex Williamson wrote:
> Hi folks,
>
> My impression is that we're getting pretty close to a workable
> implementation here with v22 plus respins of patches 5, 6, and 8. We
> also have a matching QEMU series and a proposal for a new i40e
> consumer, as we
On 2020/5/20 上午4:02, Zhang Chen wrote:
From: Zhang Chen
Hi Jason, this series include latest COLO related patches.
I have finish basic test and review.
If no other comments, please check and merge this series.
Applied.
Thanks
Derek Su (1):
colo-compare: Fix memory leak in packet_en
On 2020/5/12 0:39, Richard Henderson wrote:
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
+LUI RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
I think it would be helpful to add a function for this. e.g. greg($rd) and
gbase($rs1) (including $0). It would keep the co
On 2020/5/12 1:40, Richard Henderson wrote:
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
+# sequence of li rd, 0x1234567887654321
+#
+# 0: 002471b7lui rd,0x247
+# 4: 8ad1819baddiw rd,rd,-1875
+# 8: 00c19193sllird,rd
On 2020/5/20 9:45, LIU Zhiwei wrote:
On 2020/5/12 2:06, Richard Henderson wrote:
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
+++ b/configure
@@ -58,6 +58,8 @@ guess_arch() {
ARCH="m68k"
elif check_define __powerpc64__ ; then
ARCH="ppc64"
+ elif check_define __riscv ;
For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g
Icelake and Tigerlake, expose it to the guest VM.
Signed-off-by: Chenyi Qiang
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i
Add some missing VMX features in Skylake-Server, Cascadelake-Server and
Icelake-Server CPU models based on the output of Paolo's script.
Signed-off-by: Chenyi Qiang
---
target/i386/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.
Add the missing VMX features in Skylake-Server, Cascadelake-Server and
Icelake-Server CPU models. In Icelake-Server CPU model, it lacks sha_ni,
avx512ifma, rdpid and fsrm. The model number of Icelake-Server also needs
to be fixed.
Remove the Icelake-Client CPU model due to no Icelake Desktop produc
There are no Icelake Desktop products in the market. Remove the
Icelake-Client CPU model.
Signed-off-by: Chenyi Qiang
---
hw/i386/pc.c | 1 -
target/i386/cpu.c | 113 --
2 files changed, 114 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
According to the Intel Icelake family list, Icelake-Server uses model
number 106(0x6A).
Signed-off-by: Chenyi Qiang
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b4697b0148..d59698710e 100644
--- a/target/i38
Add the missing features(sha-ni, avx512ifma, rdpid, fsrm) in the
Icelake-Server CPU model.
Signed-off-by: Chenyi Qiang
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 52f5aa5418..b4697b0148 100644
--- a/target/i386
one changes:
Guest VM is Red Hat Enterprise Linux 8.1 (Ootpa).
there is no issue once guest VM is RHEL7.6.
--
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https://bugs.launchpad.net/bugs/1879425
Title:
The thread of "CPU 0 /KVM" ke
From: Stefano Stabellini
This reverts commit 16724a173049ac29c7b5ade741da93a0f46edff7.
It causes https://bugs.launchpad.net/bugs/1877688.
Signed-off-by: Stefano Stabellini
---
hw/9pfs/9p.c | 33 +++--
hw/9pfs/9p.h | 2 +-
hw/9pfs/virtio-
From: Stefano Stabellini
Instead of truncating replies, which is problematic, wait until the
client reads more data and frees bytes on the reply ring.
Do that by calling qemu_coroutine_yield(). The corresponding
qemu_coroutine_enter_if_inactive() is called from xen_9pfs_bh upon
receiving the nex
Hi all,
This short series reverts commit 16724a173049ac29c7b5ade741da93a0f46edff
becauses it is the cause for https://bugs.launchpad.net/bugs/1877688.
The original issue addressed by 16724a173049ac29c7b5ade741da93a0f46edff
is solved differently in this series by using qemu_coroutine_yield() to
wa
On 2020/5/12 2:06, Richard Henderson wrote:
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
+++ b/configure
@@ -58,6 +58,8 @@ guess_arch() {
ARCH="m68k"
elif check_define __powerpc64__ ; then
ARCH="ppc64"
+elif check_define __riscv ; then
+ARCH="riscv64"
else
Public bug reported:
Using boot command:
qemu-system-sparc64 -M niagara -L /home/chrisp/sparc/S10image/
-nographic -m 256 -drive
if=pflash,readonly=on,file=/home/chrisp/sparc/S10image/disk.s10hw2
After I log into solaris system I see no network devices other than the
loopback device.
All the do
This is with qemu-system-aarch64 - forgot to mention it explicitly. So,
it will only affect qemu for ARM 64-bit.
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You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1879587
Title:
Register number in ESR
Public bug reported:
I am running into a situation where I have:
- A hypervisor running in EL2, AA64
- A guest running in EL1, AA32
We trap certain accesses to special registers such as DACR (via
HCR.TVM). One instruction that is trapped is:
ee03ef10 ->mcr 15, 0, lr, cr3, cr0, {0}
The
On 05/19/20 20:20, Philippe Mathieu-Daudé wrote:
> Example of use to dump:
>
> $ qemu-system-x86_64 -S \
> -object tls-cipher-suites,id=mysuite,priority=@SYSTEM,verbose=yes
> Cipher suites for @SYSTEM:
> - TLS_AES_256_GCM_SHA3840x13, 0x02
> TLS1.3
>
On 5/19/20 10:51 AM, Philippe Mathieu-Daudé wrote:
> Missing "Signed-off-by: Gerd Hoffmann ",
> otherwise:
>
> Reviewed-by: Philippe Mathieu-Daudé
>
> On 5/15/20 5:04 PM, Gerd Hoffmann wrote:
If you add the S-O-B:
Acked-by: John Snow
>> ---
>> include/hw/block/fdc.h | 1 +
>> include/
On 5/19/20 5:04 AM, Daniel P. Berrangé wrote:
> On Mon, May 18, 2020 at 03:56:36PM -0400, John Snow wrote:
>>
>>
>> On 5/15/20 6:23 AM, Daniel P. Berrangé wrote:
>>> On Fri, May 15, 2020 at 12:11:17PM +0200, Thomas Huth wrote:
On 07/04/2020 12.59, Philippe Mathieu-Daudé wrote:
> Hello,
On 05/19/20 20:20, Philippe Mathieu-Daudé wrote:
> Since our format is consumable by the fw_cfg device,
> we can implement the FW_CFG_DATA_GENERATOR interface.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> crypto/tls-cipher-suites.c | 19 +++
> 1 file changed, 19 insertions(+
On 05/19/20 20:20, Philippe Mathieu-Daudé wrote:
> This is to silent:
>
> $ qemu-system-x86_64 \
> -object tls-cipher-suites,id=ciphersuite0,priority=@SYSTEM \
> -fw_cfg name=etc/edk2/https/ciphers,blob_id=ciphersuite0
> qemu-system-x86_64: -fw_cfg
> name=etc/edk2/https/ciphers,blob_i
On 05/19/20 20:20, Philippe Mathieu-Daudé wrote:
> The 'blob_id' argument refers to a QOM object able to produce
> data consumable by the fw_cfg device. The producer object must
> implement the FW_CFG_DATA_GENERATOR interface.
OK, this answers my OBJECT_CHECK() question under patch #1 (in the
nega
On Mon, May 18, 2020 at 10:08 PM Markus Armbruster wrote:
>
> Alistair Francis writes:
>
> > On Sun, May 17, 2020 at 10:06 PM Markus Armbruster
> > wrote:
> >>
> >> stm32f405_soc_initfn() creates six such devices, but
> >> stm32f405_soc_realize() realizes only one. Affects machine
> >> netduin
Patchew URL:
https://patchew.org/QEMU/20200519164957.26920-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200519164957.26920-1-richard.hender...@linaro.org
Subject: [PULL 00/10] softfloat misc clea
> -Original Message-
> From: Stefan Weil
> Sent: Thursday, February 20, 2020 11:54 PM
> To: Justin Terry (SF) ; Philippe Mathieu-Daudé
> ; Sunil Muthuswamy
> ; Eduardo Habkost ; Paolo
> Bonzini ; Richard
> Henderson
> Cc: qemu-devel@nongnu.org
> Subject: Re: [EXTERNAL] Re: [PATCH] WHP
On 05/19/20 20:20, Philippe Mathieu-Daudé wrote:
> The FW_CFG_DATA_GENERATOR allow any object to product
(1) I suggest:
s/allow/allows/
s/product/produce/
> blob of data consumable by the fw_cfg device.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/nvram/fw_cfg.h | 49 +
On 5/15/20 10:08 AM, Philippe Mathieu-Daudé wrote:
> +++ b/hw/semihosting/Kconfig
> @@ -1,3 +1,5 @@
>
> +# default is 'n'
> config SEMIHOSTING
> - bool
> +bool
> +depends on TCG
> diff --git a/target/arm/Kconfig b/target/arm/Kconfig
> new file mode 100644
> index 00..3224ca
On 5/15/20 10:08 AM, Philippe Mathieu-Daudé wrote:
> Allow use of target-specific Kconfig file.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Makefile | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 5/19/20 4:25 PM, Vladimir Sementsov-Ogievskiy wrote:
$ ./qemu-img map --output=json top.qcow2
[{ "start": 0, "length": 1048576, "depth": 2, "zero": false, "data":
true, "offset": 327680},
{ "start": 1048576, "length": 1048576, "depth": 0, "zero": true,
"data": false}]
I think what we real
On 5/15/20 10:07 AM, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé
>
> The TCG helpers where added in b92e5a22ec3 in softmmu_template.h.
> probe_write() was added in there in 3b4afc9e75a to be moved out
> to accel/tcg/cputlb.c in 3b08f0a9254, and was later refactored
> as probe_acc
On 5/19/20 4:13 PM, Vladimir Sementsov-Ogievskiy wrote:
19.05.2020 23:41, Eric Blake wrote:
On 5/19/20 2:54 PM, Vladimir Sementsov-Ogievskiy wrote:
bdrv_co_block_status_above has several problems with handling short
backing files:
1. With want_zeros=true, it may return ret with BDRV_BLOCK_ZERO
Signed-off-by: Alistair Francis
---
target/riscv/pmp.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 0e6b640fbd..607a991260 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -233,12 +233,16 @@ bool pmp_ha
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/opentitan.h | 13 +
hw/riscv/opentitan.c | 24 ++--
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/opentitan.h | 3 +++
hw/riscv/opentitan.c | 19 +--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 15a3d87ed0..8d
This is the initial commit of the Ibex UART device. Serial TX is
working, while RX has been implemeneted but untested.
This is based on the documentation from:
https://docs.opentitan.org/hw/ip/uart/doc/
Signed-off-by: Alistair Francis
---
include/hw/char/ibex_uart.h | 110
hw/char/ibex
Ibex is a small and efficient, 32-bit, in-order RISC-V core with
a 2-stage pipeline that implements the RV32IMC instruction set
architecture.
For more details on lowRISC see here:
https://github.com/lowRISC/ibex
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.h | 1
The Ibex core contains a PLIC that although similar to the RISC-V spec
is not RISC-V spec compliant.
This patch implements a Ibex PLIC in a somewhat generic way.
As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex
PLIC move towards spec compliance this PLIC implementation can
Currently every c file that includes boot.h also includes loader.h
before it. Which is why the build works fine. We should be able to
include just boot.h though so this is a small fixup to allow that.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
This adds a barebone OpenTitan machine to QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 11 +-
include/hw/riscv/opentitan.h| 63 +++
hw/riscv/opentitan.c| 169 +
The reset vector is set in the init function don't set it again in
realize.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..5eb3c02735 100644
--- a/target/riscv/
OpenTitan is an open source silicon Root of Trust (RoT) project. This
series adds initial support for the OpenTitan machine to QEMU.
This series add the Ibex CPU to the QEMU RISC-V target. It then adds the
OpenTitan machine, the Ibex UART and the Ibex PLIC.
The UART has been tested sending and re
On Tue, May 19, 2020 at 8:29 AM Markus Armbruster wrote:
>
> All remaining conversions to qdev_realize() are for bus-less devices.
> Coccinelle script:
>
> // only correct for bus-less @dev!
>
> @@
> expression errp;
> expression dev;
> @@
> -qdev_init_nofail(dev);
>
On Tue, May 19, 2020 at 8:22 AM Markus Armbruster wrote:
>
> I'm converting from qdev_set_parent_bus()/realize to qdev_realize();
> recent commit "qdev: Convert uses of qdev_set_parent_bus() with
> Coccinelle" explains why.
>
> sysbus_init_child_obj() is a wrapper around
> object_initialize_child_
On Fri, May 15, 2020 at 11:39 PM Anup Patel wrote:
>
> We extend CLINT emulation to allow multiple instances of CLINT in
> a QEMU RISC-V machine. To achieve this, we remove first HART id
> zero assumption from CLINT emulation.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistai
On Fri, May 15, 2020 at 11:40 PM Anup Patel wrote:
>
> This series adds multi-socket support for RISC-V virt machine and
> RISC-V spike machine. The multi-socket support will help us improve
> various RISC-V operating systems, firmwares, and bootloader to
> support RISC-V NUMA systems.
>
> These p
20.05.2020 00:13, Eric Blake wrote:
On 5/19/20 2:55 PM, Vladimir Sementsov-Ogievskiy wrote:
These cases are fixed by previous patches around block_status and
is_allocated.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/274 | 20
tests/qemu-iotests/274.ou
On Tue, May 19, 2020 at 8:25 AM Markus Armbruster wrote:
>
> Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
> argument to sysbus_realize(), sysbus_realize_and_unref().
>
> Coccinelle script:
>
> @@
> expression dev, errp;
> @@
> -qdev_realize(DEVICE(dev),
Do not explicitly store zero to the NEON high part
when we can pass !is_q to clear_vec_high.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 53 +++---
1 file changed, 32 insertions(+), 21 deletions(-)
diff --git a/targ
On Tue, May 19, 2020 at 8:04 AM Markus Armbruster
wrote:
>
> All users of object_initialize_child() pass the obvious child size
> argument. Almost all pass &error_abort and no properties. Tiresome.
>
> Rename object_initialize_child() to
> object_initialize_child_with_props() to free the name.
The 8-byte store for the end a !is_q operation can be
merged with the other stores. Use a no-op vector move
to trigger the expand_clr portion of tcg_gen_gvec_mov.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 10 ++
1 file changed, 2 inserti
Version 3 fixes the reported bug in EXT.
I should make sure I have fixed the bug wherein RISU prints a
mismatch and still exits with success, which hid this problem
in the scrollback.
r~
Richard Henderson (2):
target/arm: Use tcg_gen_gvec_mov for clear_vec_high
target/arm: Use clear_vec_hi
On Tue, May 19, 2020 at 8:04 AM Markus Armbruster wrote:
>
> The callers of object_initialize_child() commonly pass either
> &child, sizeof(child), or pchild, sizeof(*pchild). Tidy up the few
> that don't, mostly to keep the next commit simpler.
>
> Signed-off-by: Markus Armbruster
Reviewed-by
On Thu, May 7, 2020 at 12:19 PM Alistair Francis
wrote:
>
> v2:
> - Remove the CPUs and ISA seperatley
>
> Alistair Francis (3):
> hw/riscv: spike: Remove deprecated ISA specific machines
> target/riscv: Remove the deprecated CPUs
> target/riscv: Drop support for ISA spec version 1.09.1
An
On Tue, May 19, 2020 at 8:06 AM Markus Armbruster wrote:
>
> Cc: Alistair Francis
> Signed-off-by: Markus Armbruster
Reviewed-by: Alistair Francis
Alistair
> ---
> include/hw/ssi/ssi.h | 1 -
> hw/ssi/ssi.c | 5 -
> 2 files changed, 6 deletions(-)
>
> diff --git a/include/hw/ssi
On 5/18/20 7:53 PM, Richard Henderson wrote:
> +if (master_header.magic != RISU_MAGIC ||
> +master_header.risu_op != op ||
> +master_header.size != extra_size) {
> +res = RES_MISMATCH_HEAD;
> +goto fail_header;
> }
Hmm. This isn't ideal.
Consider e.g. an
On Tue, May 19, 2020 at 8:14 AM Markus Armbruster wrote:
>
> ssi_auto_connect_slaves(parent, cs_line, bus) iterates over @parent's
> QOM children @dev of type TYPE_SSI_SLAVE. It puts these on @bus, and
> sets cs_line[] to qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0).
>
> Suspicious: there is no pr
On Tue, May 19, 2020 at 8:19 AM Markus Armbruster wrote:
>
> Replace
>
> dev = ssi_create_slave_no_init(bus, type_name);
> ...
> qdev_init_nofail(dev);
>
> by
>
> dev = qdev_new(type_name);
> ...
> qdev_realize_and_unref(dev, bus, &error_fatal);
>
> Recent commit "qdev: New
On 5/19/20 2:55 PM, Vladimir Sementsov-Ogievskiy wrote:
These cases are fixed by previous patches around block_status and
is_allocated.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/274 | 20
tests/qemu-iotests/274.out | 65 ++
19.05.2020 23:41, Eric Blake wrote:
On 5/19/20 2:54 PM, Vladimir Sementsov-Ogievskiy wrote:
bdrv_co_block_status_above has several problems with handling short
backing files:
1. With want_zeros=true, it may return ret with BDRV_BLOCK_ZERO but
without BDRV_BLOCK_ALLOCATED flag, when actually sho
On Tue, May 19, 2020 at 8:11 AM Markus Armbruster wrote:
>
> We commonly plug devices into their bus right when we create them,
> like this:
>
> dev = qdev_create(bus, type_name);
>
> Note that @dev is a weak reference. The reference from @bus to @dev
> is the only strong one.
>
> We realize
On Tue, May 19, 2020 at 8:03 AM Markus Armbruster wrote:
>
> Same transformation as in the previous commit. Manual, because
> convincing Coccinelle to transform this case is not worthwhile.
>
> Cc: Alistair Francis
> Signed-off-by: Markus Armbruster
Looks sane.
Acked-by: Alistair Francis
Al
On 5/19/20 2:55 PM, Vladimir Sementsov-Ogievskiy wrote:
bdrv_is_allocated_above wrongly handles short backing files: it reports
after-EOF space as UNALLOCATED which is wrong,
You haven't convinced me of that claim.
as on read the data is
generated on the level of short backing file (if all ov
On 5/19/20 2:54 PM, Vladimir Sementsov-Ogievskiy wrote:
bdrv_co_block_status_above has several problems with handling short
backing files:
1. With want_zeros=true, it may return ret with BDRV_BLOCK_ZERO but
without BDRV_BLOCK_ALLOCATED flag, when actually short backing file
which produces these
Thanks Jan. I had some new hardware/software issues combined with the
QEMU 5.0.. issues that had my Windows VM crash after some minutes.
I totally overlooked the following:
So I guess you posted to answer to this:
https://www.reddit.com/r/VFIO/comments/erwzrg/think_i_found_a_workaround_
19.05.2020 23:21, Eric Blake wrote:
On 5/19/20 2:54 PM, Vladimir Sementsov-Ogievskiy wrote:
This leads to the following effect:
./qemu-img create -f qcow2 base.qcow2 2M
./qemu-io -c "write -P 0x1 0 2M" base.qcow2
./qemu-img create -f qcow2 -b base.qcow2 mid.qcow2 1M
./qemu-img create -f qcow2
On 5/19/20 2:54 PM, Vladimir Sementsov-Ogievskiy wrote:
This leads to the following effect:
./qemu-img create -f qcow2 base.qcow2 2M
./qemu-io -c "write -P 0x1 0 2M" base.qcow2
./qemu-img create -f qcow2 -b base.qcow2 mid.qcow2 1M
./qemu-img create -f qcow2 -b mid.qcow2 top.qcow2 2M
Region 1M
From: Lukas Straub
Else the log will be flooded if there is a lot of network
traffic.
Signed-off-by: Lukas Straub
Reviewed-by: Zhang Chen
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Zhang Chen
---
net/colo-compare.c | 10 ++
1 file changed,
On Tue, May 19, 2020 at 01:41:08PM -0500, Eric Blake wrote:
> On 5/19/20 12:56 PM, Masayoshi Mizuma wrote:
> > Hello,
> >
> > I would like to discard any changes while the qemu guest OS is done.
> > I can do that with snapshot and drive option.
> > However, snapshot option doesn't work for the dev
From: Derek Su
The patch is to fix the "pkt" memory leak in packet_enqueue().
The allocated "pkt" needs to be freed if the colo compare
primary or secondary queue is too big.
Replace the error_report of full queue with a trace event.
Signed-off-by: Derek Su
Reviewed-by: Zhang Chen
Signed-off-
From: Lukas Straub
In colo_compare_complete, insert CompareState into net_compares
only after everything has been initialized.
In colo_compare_finalize, remove CompareState from net_compares
before anything is deinitialized.
Signed-off-by: Lukas Straub
Reviewed-by: Zhang Chen
Signed-off-by: Zh
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