On 12/2/19 10:09 PM, Niek Linnenbank wrote:
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interface
On Tue, Dec 10, 2019 at 05:16:08AM +0800, Alex Williamson wrote:
> On Mon, 9 Dec 2019 01:22:12 -0500
> Yan Zhao wrote:
>
> > On Fri, Dec 06, 2019 at 11:20:38PM +0800, Alex Williamson wrote:
> > > On Fri, 6 Dec 2019 01:04:07 -0500
> > > Yan Zhao wrote:
> > >
> > > > On Fri, Dec 06, 2019 at 07:
On 12/10/19 1:52 AM, Andrew Jeffery wrote:
The AST2600 includes a second cut-down version of the SD/MMC controller
found in the AST2500, named the eMMC controller. It's cut down in the
sense that it only supports one slot rather than two, but it brings the
total number of slots supported by the A
On 12/10/19 8:14 AM, pannengy...@huawei.com wrote:
From: Pan Nengyuan
Fix a minor memory leak in riscv_sifive_u_soc_realize()
Reported-by: Euler Robot
Signed-off-by: Pan Nengyuan
---
hw/riscv/sifive_u.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sif
On 12/10/19 8:20 AM, Thomas Huth wrote:
In our downstream distribution of QEMU, we need more fine-grained
control on the set of CCID card devices that we want to include.
So let's introduce some proper Kconfig switches that it is easier
to disable them without modifying the corresponding Makefile
Vladimir Sementsov-Ogievskiy writes:
> Make error_append_security_model_hint and
> error_append_socket_sockfd_hint hint append helpers well formed:
> switch errp paramter to Error *const * type, as it has uncommon
> behavior: not change the pointer to return error, but operate on
> already existe
In our downstream distribution of QEMU, we need more fine-grained
control on the set of CCID card devices that we want to include.
So let's introduce some proper Kconfig switches that it is easier
to disable them without modifying the corresponding Makefile.objs.
Signed-off-by: Thomas Huth
---
h
Vladimir Sementsov-Ogievskiy writes:
> Make kvmppc_hint_smt_possible hint append helper well formed:
> switch errp paramter to Error *const * type, as it has uncommon
> behavior: not change the pointer to return error, but operate on
> already existent error object.
> Rename function to be kvmppc
You are right. See at the bottom of the file. There is a comment about it
Sent from my cell phone, please ignore typos
On Tue, Dec 10, 2019, 6:21 AM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Monday, December 9, 2019, Michael Rolnik wrote:
>
>> Hi Aleksandar.
>>
>> 1. al
From: Pan Nengyuan
Fix a minor memory leak in riscv_sifive_u_soc_realize()
Reported-by: Euler Robot
Signed-off-by: Pan Nengyuan
---
hw/riscv/sifive_u.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95..0e12b3c 100644
--- a/hw/riscv/si
Markus Armbruster writes:
> Vladimir Sementsov-Ogievskiy writes:
>
>> Make qbus_list_bus and qbus_list_dev hint append helpers well formed:
>> switch errp paramter to Error *const * type, as it has uncommon
>> behavior: not change the pointer to return error, but operate on
>> already existent e
On 2019-12-01, Fangrui Song wrote:
Thanks for reviewing this patch!
On 2019-12-01, Richard Henderson wrote:
On 11/27/19 6:36 PM, Fangrui Song wrote:
On 2019-11-20, Fangrui Song wrote:
On 2019-11-15, Fangrui Song wrote:
For lld, --image-base is the preferred way to set the base address.
lld
On Tue, Dec 10, 2019 at 04:05:36PM +1100, David Gibson wrote:
> On Tue, Dec 10, 2019 at 03:03:01PM +1100, Alexey Kardashevskiy wrote:
> >
> >
> > On 10/12/2019 14:50, Bharata B Rao wrote:
> > > On Tue, Dec 10, 2019 at 02:28:51PM +1100, David Gibson wrote:
> > >> On Mon, Dec 09, 2019 at 12:30:12PM
Hi
We would like to give a short update to the community about the multi-process
project.
Firstly, we appreciate the feedback and all productive discussions we had
at KVM 2019 forum.
As an outcome of the conference, we have switched gears and are investigating
the ways of using the muser frame
On Tue, Dec 03, 2019 at 04:06:46PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 03/12/2019 14:44, Alexey Kardashevskiy wrote:
> >
> >
> > On 29/11/2019 12:35, David Gibson wrote:
> >> Move the calculation of the Real Mode Area (RMA) size into a helper
> >> function. While we're there clean it u
On Tue, Dec 10, 2019 at 12:32 AM Eduardo Habkost wrote:
>
> On Tue, Dec 03, 2019 at 09:07:15PM +0200, Yuri Benditovich wrote:
> > If the redirected device has this capability, Windows guest may
> > place the device into D2 and expect it to wake when the device
> > becomes active, but this will nev
On Tue, Dec 03, 2019 at 02:44:06PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 29/11/2019 12:35, David Gibson wrote:
> > Move the calculation of the Real Mode Area (RMA) size into a helper
> > function. While we're there clean it up and correct it in a few ways:
> > * Add comments making it cl
On Tue, Nov 12, 2019 at 08:58:01AM -0500, Wainer dos Santos Moschetta wrote:
> On linux_initrd and empty_cpu_model tests the same effect of
> calling QEMU through run() to inspect the terminated process is
> achieved with a sequence of set_qmp_monitor() / launch() / wait()
> commands on an QEMUMach
On Tue, Dec 03, 2019 at 03:18:37PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 29/11/2019 12:35, David Gibson wrote:
> > The Real Mode Area (RMA) needs to fit within Node 0 in NUMA configurations.
> > We use a helper function spapr_node0_size() to calculate this.
> >
> > But that function doesn'
On Tue, Dec 10, 2019 at 03:03:01PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 10/12/2019 14:50, Bharata B Rao wrote:
> > On Tue, Dec 10, 2019 at 02:28:51PM +1100, David Gibson wrote:
> >> On Mon, Dec 09, 2019 at 12:30:12PM +0530, Bharata B Rao wrote:
> >>> A pseries guest can be run as a secure
On Tue, Nov 12, 2019 at 08:58:00AM -0500, Wainer dos Santos Moschetta wrote:
> The QEMUMachine VM has a monitor setup on which an QMP
> connection is always attempted on _post_launch() (executed
> by launch()). In case the QEMU process immediatly exits
> then the qmp.accept() (used to establish the
On Monday, December 9, 2019, Michael Rolnik wrote:
> Hi Aleksandar.
>
> 1. all instructions are 16 bit long except CALL & JMP they are 32 bit long
>
Accordingto the doc, LDS and STS also have 32-bit coding.
> 2. next_word_used is set to true by next_word when called by append_16
> when CALL &
On Mon, Dec 02, 2019 at 07:18:52PM +0100, Cédric Le Goater wrote:
> > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> > index c77f9848ec..09b3bd6443 100644
> > --- a/target/ppc/kvm.c
> > +++ b/target/ppc/kvm.c
> > @@ -2101,7 +2101,7 @@ void kvmppc_hint_smt_possible(Error **errp)
> >
> >
> >
On Thu, Nov 28, 2019 at 02:46:53PM +0100, Cédric Le Goater wrote:
> Hello,
>
> This is a resend of Suraj's series adding KVM support to the QEMU
> PowerNV machine under TCG :
>
> http://patchwork.ozlabs.org/cover/1094658/
>
> I have addressed the comments and kept for later the final patch
>
On 10/12/2019 14:50, Bharata B Rao wrote:
> On Tue, Dec 10, 2019 at 02:28:51PM +1100, David Gibson wrote:
>> On Mon, Dec 09, 2019 at 12:30:12PM +0530, Bharata B Rao wrote:
>>> A pseries guest can be run as a secure guest on Ultravisor-enabled
>>> POWER platforms. When such a secure guest is rese
On Thu, Dec 05, 2019 at 07:44:51PM +0100, Cédric Le Goater wrote:
> This is an empty shell with the XSCOM bus and cores. The chip controllers
> will come later.
>
> Signed-off-by: Cédric Le Goater
> ---
> include/hw/ppc/pnv.h | 33
> include/hw/ppc/pnv_xscom.h | 19 +
> hw/p
On Thu, Dec 05, 2019 at 07:44:49PM +0100, Cédric Le Goater wrote:
> Hello,
>
> The POWER10 and POWER9 processors are very similar and this series
> adds the basic framework for a POWER10 chip and a machine using this
> chip. The PSI and LPC models are provided first because there are no
> changes.
On Tue, Dec 10, 2019 at 02:28:51PM +1100, David Gibson wrote:
> On Mon, Dec 09, 2019 at 12:30:12PM +0530, Bharata B Rao wrote:
> > A pseries guest can be run as a secure guest on Ultravisor-enabled
> > POWER platforms. When such a secure guest is reset, we need to
> > release/reset a few resources
On Mon, Dec 09, 2019 at 02:28:00PM +0100, Greg Kurz wrote:
> PPCVirtualHypervisor is an interface instance. It should never be
> dereferenced. Drop the dummy type definition for extra safety, which
> is the common practice with QOM interfaces.
>
> Signed-off-by: Greg Kurz
Applied to ppc-for-5.0.
On Mon, Dec 09, 2019 at 12:30:12PM +0530, Bharata B Rao wrote:
> A pseries guest can be run as a secure guest on Ultravisor-enabled
> POWER platforms. When such a secure guest is reset, we need to
> release/reset a few resources both on ultravisor and hypervisor side.
> This is achieved by invoking
On Fri, Dec 06, 2019 at 09:27:23AM -0500, Cleber Rosa wrote:
> On Wed, Nov 27, 2019 at 02:10:38PM +0400, Marc-André Lureau wrote:
> > Use int.from_bytes() from python 3.2 instead.
> >
> > Signed-off-by: Marc-André Lureau
> > ---
> > scripts/analyze-migration.py | 35 +++--
> > > > Currently, yes, i40e has build dependency on vfio-pci.
> > > > It's like this, if i40e decides to support SRIOV and compiles in vf
> > > > related code who depends on vfio-pci, it will also have build dependency
> > > > on vfio-pci. isn't it natural?
> > >
> > > No, this is not natural.
On Mon, Dec 09, 2019 at 12:43:22PM -0200, Wainer dos Santos Moschetta wrote:
>
> On 12/6/19 2:54 PM, Cleber Rosa wrote:
> > On Fri, Dec 06, 2019 at 09:00:11AM -0500, Wainer dos Santos Moschetta wrote:
> > > QEMU 4.0 onward is able to boot an uncompressed kernel
> > > image by using the x86/HVM dir
On 2019/12/10 0:58, Michael S. Tsirkin wrote:
> On Mon, Dec 09, 2019 at 11:43:20AM -0500, Michael S. Tsirkin wrote:
>> On Wed, Dec 04, 2019 at 03:31:54PM +0800, pannengy...@huawei.com wrote:
>>> From: Pan Nengyuan
>>>
>>> Devices tend to maintain vq pointers, allow deleting them trough a vq
>>
On Fri, Dec 06, 2019 at 04:34:33PM -0500, Wainer dos Santos Moschetta wrote:
> This adds a method to check if the tcg accelerator is enabled
> in the QEMU binary.
>
> Signed-off-by: Wainer dos Santos Moschetta
> Reviewed-by: Alex Bennée
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> python/qemu
On Fri, Dec 06, 2019 at 04:34:32PM -0500, Wainer dos Santos Moschetta wrote:
> Currently kvm_available() checks for the presence of kvm module
> and, if target and host arches don't mismatch. This patch adds
> an 3rd checking: if QEMU binary was compiled with kvm
> support.
>
> Signed-off-by: Wain
Initialise another SDHCI model instance for the AST2600's eMMC
controller and use the SDHCI's num_slots value introduced previously to
determine whether we should create an SD card instance for the new slot.
Signed-off-by: Andrew Jeffery
---
hw/arm/aspeed.c | 13 +
hw/arm
On Fri, Dec 06, 2019 at 04:34:31PM -0500, Wainer dos Santos Moschetta wrote:
> Since commit cbe6d6365a48 the command `qemu -accel help` returns
> the list of accelerators enabled in the QEMU binary. This adds
> the list_accel() method which return that same list.
>
> Signed-off-by: Wainer dos Sant
The AST2600 includes a second cut-down version of the SD/MMC controller
found in the AST2500, named the eMMC controller. It's cut down in the
sense that it only supports one slot rather than two, but it brings the
total number of slots supported by the AST2600 to three.
The existing code assumed t
Hello,
The AST2600 has an additional SDHCI intended for use as an eMMC boot source.
These two patches rework the existing ASPEED SDHCI model to accommodate the
single-slot nature of the eMMC controller and wire it into the AST2600 SoC.
Please review!
Andrew
Andrew Jeffery (2):
hw/sd: Configur
On Fri, Dec 06, 2019 at 04:34:30PM -0500, Wainer dos Santos Moschetta wrote:
> This creates the 'accel' Python module to be the home for
> utilities that deal with accelerators. Also moved kvm_available()
> from __init__.py to this new module.
>
> Signed-off-by: Wainer dos Santos Moschetta
> Revi
On 12/9/2019 5:08 PM, Paolo Bonzini wrote:
On 08/12/19 18:52, Zhang, Chen wrote:
Hi All~
No news for a long time.
Please give me more comments about this series.
Sorry, people were probably busy with the QEMU release candidates.
Even before looking at the code, the series is completely mis
On Sun, 8 Dec 2019 22:42:25 -0500
Yan Zhao wrote:
> On Sat, Dec 07, 2019 at 05:22:26AM +0800, Alex Williamson wrote:
> > On Fri, 6 Dec 2019 02:56:55 -0500
> > Yan Zhao wrote:
> >
> > > On Fri, Dec 06, 2019 at 07:55:19AM +0800, Alex Williamson wrote:
> > > > On Wed, 4 Dec 2019 22:25:36 -050
On Mon, Dec 9, 2019 at 2:55 PM Aleksandar Markovic
wrote:
>
>
>
> On Monday, December 9, 2019, Alistair Francis
> wrote:
>>
>> This patch series adds the RISC-V Hypervisor extension v0.5. This is the
>> latest draft spec of the Hypervisor extension.
>>
>
> Hi, Alistair,
>
> I have a question for
On Thu, Dec 05, 2019 at 03:48:47PM +0100, David Hildenbrand wrote:
> On 05.12.19 15:35, Eduardo Habkost wrote:
> > On Mon, Dec 02, 2019 at 10:15:12AM +0100, David Hildenbrand wrote:
> >>
> Say the user has the option to select a model (zEC12, z13, z14), upper
> layers always want to have
On 12/9/19 9:55 PM, Greg Kurz wrote:
On Mon, 9 Dec 2019 20:12:09 +1100
Gavin Shan wrote:
On 12/9/19 7:36 PM, Greg Kurz wrote:
On Sun, 8 Dec 2019 00:14:00 +1100
Gavin Shan wrote:
On 12/7/19 3:50 AM, Greg Kurz wrote:
On Fri, 6 Dec 2019 17:36:42 +1100
Gavin Shan wrote:
object_dynamic_cas
Patchew URL:
https://patchew.org/QEMU/1575903705-12925-1-git-send-email-pbonz...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v2 00/18] Complete the implementation of -accel
Type: series
Message-id: 1575903705-129
On Monday, December 9, 2019, Alistair Francis
wrote:
> This patch series adds the RISC-V Hypervisor extension v0.5. This is the
> latest draft spec of the Hypervisor extension.
>
>
Hi, Alistair,
I have a question for you:
Let's say this series is accepted. And let's say, next year, the draft sp
Patchew URL:
https://patchew.org/QEMU/1575903705-12925-1-git-send-email-pbonz...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRI
On Tue, Dec 03, 2019 at 09:07:15PM +0200, Yuri Benditovich wrote:
> If the redirected device has this capability, Windows guest may
> place the device into D2 and expect it to wake when the device
> becomes active, but this will never happen. For example, when
> internal Bluetooth adapter is redire
On Friday, December 6, 2019, Peter Maydell wrote:
> On Tue, 3 Dec 2019 at 19:32, Niek Linnenbank
> wrote:
> > Indeed that sounds like an interesting combination. Are there plans to
> build a multi-arch/single-binary QEMU?
>
> This is in the category of "it would be nice in theory to
> support mu
On 12/9/19 11:58 AM, Max Reitz wrote:
On 09.12.19 17:30, Max Reitz wrote:
On 02.12.19 15:09, Vladimir Sementsov-Ogievskiy wrote:
Hi again!
Still forgotten bug-fix :(
Is it too late for 4.2?
Sorry. :-/
Yes, I think I just forgot it. I don’t think it’s too important for
4.2, so, well, it is
On 12/9/19 11:03 AM, John Snow wrote:
Did you mean to mark this as [PULL] ?
Probably - that's the curse of hand-editing a mail sent in-reply-to the
cover letter after the fact, instead of sending a v2 of the overall pull
request. At any rate, the correct commit made it in (f56281abd9).
O
Hi Philippe,
On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > Dear QEMU developers,
> >
> > Hereby I would like to contribute the following set of patches to QEMU
> > which add support for the Allwinner H3 System on Chip and the
> > O
On 07/12/2019 21:56, bilalwasim...@gmail.com wrote:
> From: Bilal Wasim
>
> This addition ensures that the IP does NOT boot up in
> promiscuous mode by default, and so the software only receives the desired
> packets(Unicast, Broadcast, Unicast / Multicast hashed) by default. The
> software runn
On Mon, 9 Dec 2019 01:22:12 -0500
Yan Zhao wrote:
> On Fri, Dec 06, 2019 at 11:20:38PM +0800, Alex Williamson wrote:
> > On Fri, 6 Dec 2019 01:04:07 -0500
> > Yan Zhao wrote:
> >
> > > On Fri, Dec 06, 2019 at 07:55:30AM +0800, Alex Williamson wrote:
> > > > On Wed, 4 Dec 2019 22:26:50 -050
Virtqueue notifications are not necessary during polling, so we disable
them. This allows the guest driver to avoid MMIO vmexits.
Unfortunately the virtio-blk and virtio-scsi handler functions re-enable
notifications, defeating this optimization.
Fix virtio-blk and virtio-scsi emulation so they l
The 1.13.0 version of SeaBIOS has now been released. For more
information on the release, please see:
http://seabios.org/Releases
New in this release:
* Support for reading logical CHS drive information from QEMU
* Workaround added for misbehaving optionroms that grab "int19"
* The TPM 2 "PCR
On Mon, 9 Dec 2019 16:42:39 +
Peter Maydell wrote:
> On Mon, 9 Dec 2019 at 16:28, Greg Kurz wrote:
> >
> > On Mon, 9 Dec 2019 15:02:38 +0100
> > Philippe Mathieu-Daudé wrote:
> >
> > > On 12/9/19 2:28 PM, Greg Kurz wrote:
> > > > PPCVirtualHypervisor is an interface instance. It should neve
On Mon, 9 Dec 2019 19:21:43 +0100
Cornelia Huck wrote:
> On Mon, 09 Dec 2019 18:55:12 +0100
> Greg Kurz wrote:
>
> > Each cpu subclass overloads the reset method of its parent class with
> > its own. But since it needs to call the parent method as well, it keeps
> > a parent_reset pointer to do
+Markus
On Tue, Dec 03, 2019 at 03:43:03PM +0100, Igor Mammedov wrote:
> On Tue, 3 Dec 2019 09:56:15 +0100
> Thomas Huth wrote:
>
> > On 02/12/2019 22.00, Eduardo Habkost wrote:
> > > On Mon, Dec 02, 2019 at 08:39:48AM +0100, Igor Mammedov wrote:
> > >> On Fri, 29 Nov 2019 18:46:12 +0100
> > >
On 12/09/19 14:09, Igor Mammedov wrote:
> Firmware can enumerate present at boot APs by broadcasting wakeup IPI,
> so that woken up secondary CPUs could register them-selves.
> However in CPU hotplug case, it would need to know architecture
> specific CPU IDs for possible and hotplugged CPUs so it
On 12/09/19 14:09, Igor Mammedov wrote:
> Document work-flows for
> * enabling/detecting modern CPU hotplug interface
> * finding a CPU with pending 'insert/remove' event
> * enumerating present and possible CPUs
>
> Signed-off-by: Igor Mammedov
> ---
> v2:
> - fix indent of "other values"
On 12/09/19 14:09, Igor Mammedov wrote:
> No functional change in practice, patch only aims to properly
> document (in spec and code) intended usage of the reserved space.
>
> The new field is to be used for 2 purposes:
> - detection of modern CPU hotplug interface using
> CPHP_GET_NEXT_CPU_
On 12/09/19 14:46, Igor Mammedov wrote:
> test lockable SMRAM at default SMBASE feature, introduced by
> patch "q35: implement 128K SMRAM at default SMBASE address"
>
> Signed-off-by: Igor Mammedov
> ---
> v3:
> - a bunch of spelling fixes
>(Christophe de Dinechin )
Since I've run git-range-
On 12/09/19 14:08, Igor Mammedov wrote:
> It's not what real HW does, implementing which would be overkill [**]
> and would require complex cross stack changes (QEMU+firmware) to make
> it work.
> So considering that SMRAM is owned by MCH, for simplicity (ab)use
> reserved Q35 register, which allow
On Sunday, December 8, 2019, Michael Rolnik wrote:
> Signed-off-by: Michael Rolnik
> ---
> qemu-doc.texi | 10 ++
> 1 file changed, 10 insertions(+)
>
>
Very good!!
You can add these nice 5-6 examples that you mentioned in yor cover letter.
Just a heads up, if we change mcu/device mo
On Monday, December 9, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Sunday, December 8, 2019, Michael Rolnik wrote:
>
>> This includes:
>> - encoding of all 16 bit instructions
>> - encoding of all 32 bit instructions
>>
>> Signed-off-by: Michael Rolnik
>> Tested-by:
On Sunday, December 8, 2019, Michael Rolnik wrote:
> This includes:
> - encoding of all 16 bit instructions
> - encoding of all 32 bit instructions
>
> Signed-off-by: Michael Rolnik
> Tested-by: Philippe Mathieu-Daudé
> ---
> target/avr/insn.decode | 194 +++
Patchew URL:
https://patchew.org/QEMU/20191209143723.6368-1-alex.ben...@linaro.org/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
Patchew URL:
https://patchew.org/QEMU/20191209110759.35227-1-stefa...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
Patchew URL:
https://patchew.org/QEMU/20191209110759.35227-1-stefa...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ==
Patchew URL: https://patchew.org/QEMU/20191209134552.27733-1-phi...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
Patchew URL: https://patchew.org/QEMU/20191209134552.27733-1-phi...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#
Patchew URL: https://patchew.org/QEMU/20191209095002.32194-1-phi...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
Hi Aleksandar.
1. all instructions are 16 bit long except CALL & JMP they are 32 bit long
2. next_word_used is set to true by next_word when called by append_16 when
CALL & JMP are parsed
Regards,
Michael Rolnik
On Mon, Dec 9, 2019 at 8:10 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wr
On Monday, December 9, 2019, Michael Rolnik wrote:
> :)
>
> no idea. all other machines / CPUs have it, so I added as well
>
>>
>>
lol
> On Mon, Dec 9, 2019 at 8:13 PM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Sunday, December 8, 2019, Michael Rolnik wrote:
>>
>
Patchew URL: https://patchew.org/QEMU/20191209125248.5849-1-th...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#! /
Patchew URL: https://patchew.org/QEMU/20191209095002.32194-1-phi...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#
Patchew URL: https://patchew.org/QEMU/20191209125248.5849-1-th...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/
I will check again.
On Mon, Dec 9, 2019 at 8:30 PM Michael Rolnik wrote:
> Yes, I did compile other platforms.
>
> On Mon, Dec 9, 2019 at 8:24 PM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Sunday, December 8, 2019, Michael Rolnik wrote:
>>
>>> A simple board setup
I prefer to remove it, as nobody uses it. what do you think? the full list
is in target/avr/cpu.h file
On Mon, Dec 9, 2019 at 8:16 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Sunday, December 8, 2019, Michael Rolnik wrote:
>
>> Add AVR related definitions into QEMU
>>
>
On Sunday, December 8, 2019, Michael Rolnik wrote:
> A simple board setup that configures an AVR CPU to run a given firmware
> image.
> This is all that's useful to implement without peripheral emulation as AVR
> CPUs include a lot of on-board peripherals.
>
> NOTE: this is not a real board
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 43c6629014..aa033b8590 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -841,6 +841,8
On Fri, 06 Dec 2019 08:17:27 +0100
Markus Armbruster wrote:
> Cornelia Huck writes:
>
> > On Thu, 5 Dec 2019 14:05:19 +0100
> > Philippe Mathieu-Daudé wrote:
> >
> >> Hi Cornelia,
> >>
> >> On 12/5/19 12:53 PM, Cornelia Huck wrote:
> >> > The Posix implementation of guest-set-time invokes
On Mon, 09 Dec 2019 18:55:12 +0100
Greg Kurz wrote:
> Each cpu subclass overloads the reset method of its parent class with
> its own. But since it needs to call the parent method as well, it keeps
> a parent_reset pointer to do so. This causes the same not very explicit
> boiler plate to be dupl
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8667e5ffce..43c6629014 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
---
target/riscv/cpu.c | 5 +
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ac8f53a49d..f087bc2c8b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@
Yes, I did compile other platforms.
On Mon, Dec 9, 2019 at 8:24 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Sunday, December 8, 2019, Michael Rolnik wrote:
>
>> A simple board setup that configures an AVR CPU to run a given firmware
>> image.
>> This is all that's usefu
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 193 ++
2 files changed, 175 insertions(+), 19 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index eb089fbdb6..b411a1f900 100644
--- a/target
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 6 ++
target/riscv/cpu.h| 7 +++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 7 +++
target/riscv/csr.c| 25 +
target/riscv/op_helper.c | 4
6 files cha
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_privileged.inc.c | 5 -
2 files changed, 6 deletions(-)
diff --git a/target/riscv/ins
:)
no idea. all other machines / CPUs have it, so I added as well
On Mon, Dec 9, 2019 at 8:13 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Sunday, December 8, 2019, Michael Rolnik wrote:
>
>> Signed-off-by: Michael Rolnik
>> Tested-by: Philippe Mathieu-Daudé
>> Review
Mark both sstatus and vsstatus as dirty (3).
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
---
target/riscv/translate.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1a379bd2ae..1d879b34db 100644
--- a/t
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 39 ++-
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2040fc0208..8b234790a7 100644
--- a/target/riscv/cpu_helper.c
+++
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
---
target/riscv/insn32.decode| 23 ++-
.../riscv/insn_trans/trans_privileged.inc.c | 40 +++
2 files changed, 54 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32.decode b/tar
On Mon, 09 Dec 2019 18:55:30 +0100
Greg Kurz wrote:
> Convert all targets to use cpu_class_set_parent_reset() with the following
> coccinelle script:
>
> @@
> type CPUParentClass;
> CPUParentClass *pcc;
> CPUClass *cc;
> identifier parent_fn;
> identifier child_fn;
> @@
> +cpu_class_set_parent_r
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 5 +
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 66
1 file changed, 54 insertions(+), 12 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index beb34e705b..e5128570e6 100644
--- a/ta
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 65 +--
1 file changed, 55 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1b747abf93..2c6d2bc3a3 100644
--- a/
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