Am 07.12.19 um 03:33 schrieb Cameron Esfahani via:
> Signed-off-by: Cameron Esfahani
> ---
> target/i386/machine.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/i386/machine.c b/target/i386/machine.c
> index 2699eed94e..f21823f179 100644
> --- a/target/i38
On Friday, December 6, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Friday, December 6, 2019, Philippe Mathieu-Daudé
> wrote:
>
>> Hi Aleksandar,
>>
>> On 8/19/19 4:47 PM, Aleksandar Rikalo wrote:
>>
>>> From: Aleksandar Markovic
>>> > Sent: Monday, August 19, 2019 2
That file IS present and its contents are:
prefix=/usr
exec_prefix=${prefix}
libdir=${prefix}/lib/x86_64-linux-gnu
includedir=${prefix}/include
Name: GThread
Description: Thread support for GLib
Requires: glib-2.0
Version: 2.50.3
Libs: -L${libdir} -lgthread-2.0 -pthread
Cflags: -pthread
Let me k
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1623998
Title:
pulseaudio
Signed-off-by: Cameron Esfahani
---
target/i386/machine.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 2699eed94e..f21823f179 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -261,7 +261,7 @@ static
Patchew URL:
https://patchew.org/QEMU/1575627817-24625-1-git-send-email-catherine.h...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH] target/i386: skip kvm_msr_entry_add when kvm_vmx_basic is 0
Type: series
Message-
On 12/4/19 9:25 PM, Yan Zhao wrote:
when vfio-pci is bound to a physical device, almost all the hardware
resources are passthroughed.
The intent is obvious, but it sounds awkward to a native speaker.
s/passthroughed/passed through/
Sometimes, vendor driver of this physcial device may want to
14.05.2019 23:19, John Snow wrote:
> Shift from looking at every root BDS to *every* BDS. This will migrate
> bitmaps that are attached to blockdev created nodes instead of just ones
> attached to emulated storage devices.
>
> Note that this will not migrate anonymous or internal-use bitmaps, as
>
Hi Philippe,
On Fri, Dec 6, 2019 at 6:41 AM Philippe Mathieu-Daudé
wrote:
> On 12/5/19 11:15 PM, Niek Linnenbank wrote:
> > Hello Philippe,
> >
> > On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daudé
> > mailto:phi...@redhat.com>> wrote:
> >
> > On 12/2/19 10:09 PM, Niek Linnenbank wrote:
This creates the 'accel' Python module to be the home for
utilities that deal with accelerators. Also moved kvm_available()
from __init__.py to this new module.
Signed-off-by: Wainer dos Santos Moschetta
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
python/qemu/__init__.py |
On Fri, 6 Dec 2019 18:25:14 +0100
Philippe Mathieu-Daudé wrote:
> Add the INTEL_IGD_PASSTHROUGH Kconfig option.
>
> Since it is implied by the PCI_I440FX option, this does not change
> the default selection. However users are now able to deselelect it.
>
> Signed-off-by: Philippe Mathieu-Daudé
Since commit cbe6d6365a48 the command `qemu -accel help` returns
the list of accelerators enabled in the QEMU binary. This adds
the list_accel() method which return that same list.
Signed-off-by: Wainer dos Santos Moschetta
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
pytho
Currently kvm_available() checks for the presence of kvm module
and, if target and host arches don't mismatch. This patch adds
an 3rd checking: if QEMU binary was compiled with kvm
support.
Signed-off-by: Wainer dos Santos Moschetta
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
-
This adds a method to check if the tcg accelerator is enabled
in the QEMU binary.
Signed-off-by: Wainer dos Santos Moschetta
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
python/qemu/accel.py | 8
1 file changed, 8 insertions(+)
diff --git a/python/qemu/accel.py b/
On commit abf0bf998dcb John Snow moved some code out of __init__.py
to machine.py. kvm_available() remained in though. So on patch 01
I continue his work by creating a home for that method (the new
'accel' module). Honestly I was unsure about whether move the code
to any existing module or make a n
On Fri, 6 Dec 2019 02:56:55 -0500
Yan Zhao wrote:
> On Fri, Dec 06, 2019 at 07:55:19AM +0800, Alex Williamson wrote:
> > On Wed, 4 Dec 2019 22:25:36 -0500
> > Yan Zhao wrote:
> >
> > > when vfio-pci is bound to a physical device, almost all the hardware
> > > resources are passthroughed.
> >
Hey Peter, Philippe,
On Fri, Dec 6, 2019 at 5:35 PM Philippe Mathieu-Daudé
wrote:
> On 12/6/19 3:27 PM, Peter Maydell wrote:
> > On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank
> wrote:
> >>
> >> The Security Identifier device in Allwinner H3 System on Chip
> >> gives applications a per-board uniq
Hey Peter,
On Fri, Dec 6, 2019 at 3:25 PM Peter Maydell
wrote:
> On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank
> wrote:
> >
> > This change ensures that the FPU can be accessed in Non-Secure mode
> > when the CPU core is reset using the arm_set_cpu_on() function call.
> > The NSACR.{CP11,CP10} b
06.12.2019 22:43, Cleber Rosa wrote:
> On Tue, Nov 26, 2019 at 06:48:45PM +0300, Vladimir Sementsov-Ogievskiy wrote:
>> Hi all!
>>
>> Here is simple benchmarking utility, to generate performance
>> comparison tables, like the following:
>>
>> -- - - -
* Laurent Vivier (lviv...@redhat.com) wrote:
> Commit 1bd71dce4bf2 tries to prevent a finishmigrate -> prelaunch
> transition by exiting at the beginning of the main_loop_should_exit()
> function if the state is already finishmigrate.
>
> As the finishmigrate state is set in the migration thread i
On 12/6/19 1:02 PM, John Snow wrote:
I'm afraid that the only thing is not remove persistent bitmaps, which
were never synced to the image. So, instead the sequence above, we need
1. create persistent bitmap A
2. shutdown vm
3. start vm
4. create persistent bitmap B
5. remember, that we want t
On Friday, December 6, 2019, Philippe Mathieu-Daudé
wrote:
> Hi Aleksandar,
>
> On 8/19/19 4:47 PM, Aleksandar Rikalo wrote:
>
>> From: Aleksandar Markovic
>> > Sent: Monday, August 19, 2019 2:07 PM
>> > To: qemu-devel@nongnu.org
>> > Cc: phi...@redhat.com ; Aleksandar Markovic <
>> amarko..
On Tue, Nov 26, 2019 at 06:48:45PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Hi all!
>
> Here is simple benchmarking utility, to generate performance
> comparison tables, like the following:
>
> -- - - -
> backup-1 backup-2
On Fri, 6 Dec 2019 at 18:51, Richard Henderson
wrote:
>
> On 12/6/19 8:03 AM, Peter Maydell wrote:
> > So I *think* what the code is doing is:
> >
> > When VHE is enabled, the exception level below EL2 is
> > not EL1, but EL0, and so to identify the entry vector
> > offset for exceptions target
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> Include definitions for all of the bits in ID_MMFR3.
> We already have a definition for ID_AA64MMFR1.PAN.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> Since v8.0, the CPSR_RESERVED bits have been allocated.
> We are not yet implementing ARMv8.4-DIT; retain CPSR_RESERVED,
> since that overlaps with our current hack for AA32 single step.
>
> Signed-off-by: Richard Henderson
> ---
> target
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> In target/arm we will shortly have "too many" mmu_idx.
> The current minimum barrier is caused by the way in which
> tlb_flush_page_by_mmuidx is coded.
>
> We can remove this limitation by allocating memory for
> consumption by the worker.
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> If we have a PAN-enforcing mmu_idx, set prot == 0 if user_rw != 0.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/internals.h | 13 +
> target/arm/helper.c| 3 +++
> 2 files changed, 16 insertions(+)
>
> diff --g
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> This includes enablement of ARMv8.1-PAN.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
Each cpu subclass overloads the reset method of its parent class with
its own. But since it needs to call the parent method as well, it keeps
a parent_reset pointer to do so. This causes the same not very explicit
boiler plate to be duplicated all around the place:
pcc->parent_reset = cc->rese
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> Examine the PAN bit for EL1, EL2, and Secure EL1 to
> determine if it applies.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/target/arm/helper.c b/target
On Fri, 6 Dec 2019 at 16:23, Philippe Mathieu-Daudé wrote:
>
> Make the gic a field in the machine state, and instead of filling
> an array of qemu_irq and passing it around, directly call
> qdev_get_gpio_in() on the gic field.
>
> Signed-off-by: Philippe Mathieu-Daudé
Applied to target-arm.nex
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> For aarch64, there's a dedicated msr (imm, reg) insn.
> For aarch32, this is done via msr to cpsr; and writes
> from el0 are ignored.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 2 ++
> target/arm/helper.c
On 12/6/19 5:37 AM, Vladimir Sementsov-Ogievskiy wrote:
> 06.12.2019 1:37, John Snow wrote:
>> This has come up in the past, and I believe we discussed this at KVM
>> Forum, too:
>>
>> There have been requests from oVirt (via Nir Soffer) to add some offline
>> bitmap manipulation functionality.
On Tue, 3 Dec 2019 at 23:42, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 6 ++
> target/arm/helper.c| 21 +
> target/arm/translate-a64.c | 14 ++
> 3 files changed, 41 insertions(+)
>
> diff --git
On 12/6/19 9:36 AM, Eric Blake wrote:
> [adding in Peter Maydell, as there is now potential talk of other
> 4.2-worthy patches]
>
> On 12/6/19 4:18 AM, Vladimir Sementsov-Ogievskiy wrote:
>> 05.12.2019 23:16, John Snow wrote:
>>>
>>>
>>> On 12/5/19 3:09 PM, Eric Blake wrote:
On 12/5/19 1:3
On Tue, Dec 03, 2019 at 02:07:32PM +, Alex Bennée wrote:
>
> Cleber Rosa writes:
>
> > RFC: QEMU Gating CI
> > ===
> >
> > This RFC attempts to address most of the issues described in
> > "Requirements/GatinCI"[1]. An also relevant write up is the "State of
> > QEMU CI as we
On 12/6/19 10:30 AM, Peter Maydell wrote:
>> +if (cpu_isar_feature(aa64_uao, cpu)) {
>> +static const ARMCPRegInfo uao_reginfo[] = {
>> +{ .name = "UAO", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
>> + .typ
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> Use a common predicate for querying stage1-ness.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/internals.h | 11 +++
> target/arm/helper.c| 8 +++-
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --
Peter Maydell writes:
> On Fri, 6 Dec 2019 at 12:22, Alex Bennée wrote:
>>
>> For system emulation we need to check the state of the GIC before we
>> report the value. However this isn't relevant to exporting of the
>> value to linux-user and indeed breaks the exported value as set by
>> modif
On Tue, 3 Dec 2019 at 23:42, Richard Henderson
wrote:
>
> Add definitions for all of the fields, up to ARMv8.5.
> Convert the existing RESERVED register to a full register.
> Query KVM for the value of the register for the host.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h|
On 12/6/19 10:41 AM, Peter Maydell wrote:
> On Fri, 6 Dec 2019 at 18:36, Richard Henderson
> wrote:
>
+static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+CPWriteFn *writefn;
+
+if (redirect_for_e
On 12/6/19 7:46 AM, Peter Maydell wrote:
> On Tue, 3 Dec 2019 at 02:29, Richard Henderson
> wrote:
>>
>> The EL1&0 regime is the only one that uses 2-stage translation.
>
> ...now what happens when we support secure EL2 and we need a
> secure stage 2 MMUIdx ?
ARMMMUIdx_SStage2?
Or probably some
On 12/6/19 8:03 AM, Peter Maydell wrote:
> So I *think* what the code is doing is:
>
> When VHE is enabled, the exception level below EL2 is
> not EL1, but EL0, and so to identify the entry vector
> offset for exceptions targeting EL2 we need to look
> at the width of EL0, not of EL1.
>
> Is
On 12/6/19 7:45 AM, Peter Maydell wrote:
> On Tue, 3 Dec 2019 at 02:29, Richard Henderson
> wrote:
>>
>> This is part of a reorganization to the set of mmu_idx.
>> This emphasizes that they apply to the EL1&0 regime.
>
> It loses the important point that they are stage 1&2
> translations rather t
Use it in include/hw/core/cpu.h and convert all targets to use it as
well with:
perl -pi \
-e 's/void\s+\(\*(parent_reset)\)\(CPUState\s+\*\w+\)/CPUReset \1/;' \
$(git ls-files 'target/*.h')
Signed-off-by: Greg Kurz
---
include/hw/core/cpu.h |4 +++-
target/alpha/cpu-qom.h |
On 12/6/19 7:29 AM, Peter Maydell wrote:
> On Fri, 6 Dec 2019 at 12:22, Alex Bennée wrote:
>>
>> For system emulation we need to check the state of the GIC before we
>> report the value. However this isn't relevant to exporting of the
>> value to linux-user and indeed breaks the exported value as
Convert all targets to use cpu_class_set_parent_reset() with the following
coccinelle script:
@@
type CPUParentClass;
CPUParentClass *pcc;
CPUClass *cc;
identifier parent_fn;
identifier child_fn;
@@
+cpu_class_set_parent_reset(cc, child_fn, &pcc->parent_fn);
-pcc->parent_fn = cc->reset;
...
-cc->r
Similarly to what we already do with qdev, use a helper to overload the
reset QOM methods of the parent in children classes, for clarity.
Signed-off-by: Greg Kurz
---
hw/core/cpu.c |8
include/hw/core/cpu.h |4
2 files changed, 12 insertions(+)
diff --git a/hw/core
Test overflows for MEM_ACESS and SW_INCR events. Also tests
overflows with 64-bit events.
Signed-off-by: Eric Auger
---
arm/pmu.c | 133 +-
arm/unittests.cfg | 6 +++
2 files changed, 138 insertions(+), 1 deletion(-)
diff --git a/arm/pmu.c b
On Fri, 6 Dec 2019 at 18:36, Richard Henderson
wrote:
> >> +static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
> >> + uint64_t value)
> >> +{
> >> +CPWriteFn *writefn;
> >> +
> >> +if (redirect_for_e2h(env)) {
> >> +/* Switch to the saved
ipi_enable() code would be reusable for other interrupts
than IPI. Let's rename it setup_irq() and pass an interrupt
handler pointer. We also export it to use it in other tests
such as the PMU's one.
Signed-off-by: Eric Auger
---
arm/gic.c | 24 +++-
lib/arm/asm/gic.h
On 12/6/19 9:24 AM, Peter Maydell wrote:
>> +union {
>> +/*
>> + * Offsets of the secure and non-secure fields in CPUARMState for
>> + * the register if it is banked. These fields are only used during
>> + * the static registration of a register. During hashing
We can use a i440FX without the IGD passthrough host bridge.
Extract it into a new file, 'hw/pci-host/igd_pt.c'.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/i440fx.c | 84 --
hw/pci-host/igd_pt.c | 120 ++
MAINTAIN
We don't enforce the -Wsign-conversion CPPFLAG, but it doesn't hurt
to avoid this warning:
warning: implicit conversion changes signedness: 'int' to 'size_t' (aka
'unsigned long') [-Wsign-conversion]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/i440fx.c | 5 ++---
1 file changed, 2
On Tue, 3 Dec 2019 at 23:42, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 9399253b4c..03377084e3 100644
> --- a/target/arm/cpu64.c
> +++ b/targ
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> Several of the EL1/0 registers are redirected to the EL2 version when in
> EL2 and HCR_EL2.E2H is set. Many of these registers have side effects.
> Link together the two ARMCPRegInfo structures after they have been
> properly instantiated.
On Tue, 3 Dec 2019 at 23:42, Richard Henderson
wrote:
>
> We need only override the current condition under which
> TBFLAG_A64.UNPRIV is set.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 41 +
> 1 file changed, 21 insertions(+), 20 de
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 33 ++---
> 1 file changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 2a4d4c2c0d..b059d9f
On 12/6/19 7:47 AM, Peter Maydell wrote:
> On Tue, 3 Dec 2019 at 02:29, Richard Henderson
> wrote:
>>
>> This is part of a reorganization to the set of mmu_idx.
>> The EL1&0 regime is the only one that uses 2-stage translation.
>> Spelling out Stage avoids confusion with Secure.
>
> If you didn't
On Fri, Dec 06, 2019 at 04:55:37PM +, aijaz.b...@protonmail.com wrote:
> Here is the content of config.log: https://pastebin.com/6zrSXWAG
>
> I am configuring it for 'arm-softmmu' as can be seen from the above paste
Looks like it is failing on
$ pkg-config --atleast-version=2.40 gthread-
06.12.2019 18:58, Markus Armbruster wrote:
> Eric Blake writes:
>
>> On 12/5/19 11:46 AM, Vladimir Sementsov-Ogievskiy wrote:
>>> The local_err parameter is not here to return information about
>>> nbd_iter_channel_error failure. Instead it's assumed to be filled when
>>> passed to the function.
On Fri, 6 Dec 2019 at 18:00, Richard Henderson
wrote:
>
> On 12/6/19 7:45 AM, Peter Maydell wrote:
> > On Tue, 3 Dec 2019 at 02:29, Richard Henderson
> > wrote:
> >>
> >> This is part of a reorganization to the set of mmu_idx.
> >> This emphasizes that they apply to the EL1&0 regime.
> >
> > It l
On 12/6/19 6:08 AM, Peter Maydell wrote:
>> DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64)
>> DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64)
>> DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
>> +
>> +DEF_HELPER_3(check_hcr_el2_trap, void, env, i32, i32)
Hi Aleksandar,
On 8/19/19 4:47 PM, Aleksandar Rikalo wrote:
From: Aleksandar Markovic
> Sent: Monday, August 19, 2019 2:07 PM
> To: qemu-devel@nongnu.org
> Cc: phi...@redhat.com ; Aleksandar Markovic
; Aleksandar Rikalo
> Subject: [EXTERNAL][PATCH v8 15/37] target/mips: Style improvement
On Fri, 6 Dec 2019 17:33:37 +1100
Gavin Shan wrote:
> The @cpu_option shouldn't be NULL, otherwise assertion from g_strsplit()
> should be raised as below message indicates. So it's meaningless to validate
> @model_pices[0] in parse_cpu_option() as it shouldn't be NULL either.
>
>qemu-syste
Hi,
On 12/6/19 5:27 PM, Eric Auger wrote:
> From: Andrew Jones
>
> Sometimes we need to test access to system registers which are
> missing assembler mnemonics.
>
> Signed-off-by: Andrew Jones
> ---
> lib/arm64/asm/sysreg.h | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/l
Make the gic a field in the machine state, and instead of filling
an array of qemu_irq and passing it around, directly call
qdev_get_gpio_in() on the gic field.
Signed-off-by: Philippe Mathieu-Daudé
---
v2: make DeviceState *gic a field in SBSAMachineState (Peter)
---
hw/arm/sbsa-ref.c | 86
From: Andre Przywara
A common theme when accessing per-IRQ parameters in the GIC distributor
is to set fields of a certain bit width in a range of MMIO registers.
Examples are the enabled status (one bit per IRQ), the level/edge
configuration (2 bits per IRQ) or the priority (8 bits per IRQ).
Ad
---
arm/pmu.c | 125 +-
arm/unittests.cfg | 6 +++
2 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/arm/pmu.c b/arm/pmu.c
index e185809..47d46a2 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -116,6 +116,7 @@ static void test_basic_ev
If event counters are implemented check the common events
required by the PMUv3 are implemented.
Some are unconditionally required (SW_INCR, CPU_CYCLES,
either INST_RETIRED or INST_SPEC). Some others only are
required if the implementation implements some other features.
Check those wich are unco
On 11/29/19 8:00 PM, Peter Maydell wrote:
> On Fri, 18 Oct 2019 at 16:07, Damien Hedde wrote:
>>
>> Signed-off-by: Damien Hedde
>
> Subject line still says ".txt".
>
>> ---
>>
>> +Polling the reset state
>> +...
>> +
>> +Resettable interface provides the ``resettable_is_i
As we intend to introduce more PMU tests, let's add
a sub-test parameter that will allow to categorize
them. Existing tests are in the cycle-counter category.
Signed-off-by: Eric Auger
---
arm/pmu.c | 22 ++
arm/unittests.cfg | 7 ---
2 files changed, 18 insertio
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> Apart from the wholesale redirection that HCR_EL2.E2H performs
> for EL2, there's a separate redirection specific to the timers
> that happens for EL0 when running in the EL2&0 regime.
>
> Signed-off-by: Richard Henderson
> ---
> target/a
On 12/6/19 4:34 PM, Peter Maydell wrote:
On Fri, 6 Dec 2019 at 07:23, Philippe Mathieu-Daudé wrote:
Instead of filling an array of qemu_irq and passing it around,
directly call qdev_get_gpio_in() on the GIC.
Signed-off-by: Philippe Mathieu-Daudé
---
I accept better patch subject suggestions
From: Andrew Jones
Sometimes we need to test access to system registers which are
missing assembler mnemonics.
Signed-off-by: Andrew Jones
---
lib/arm64/asm/sysreg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/lib/arm64/asm/sysreg.h b/lib/arm64/asm/sysreg.h
index a03830b..
Add 2 tests exercising chained counters. The first one uses
CPU_CYCLES and the second one uses SW_INCR.
Signed-off-by: Eric Auger
---
arm/pmu.c | 125 ++
arm/unittests.cfg | 12 +
2 files changed, 137 insertions(+)
diff --git a/arm/pmu.c
Adds the following tests:
- event-counter-config: test event counter configuration
- basic-event-count:
- programs counters #0 and #1 to count 2 required events
(resp. CPU_CYCLES and INST_RETIRED). Counter #0 is preset
to a value close enough to the 32b
overflow limit so that we check the o
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> Since we only support a single ASID, flush the tlb when it changes.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper
On Fri, 6 Dec 2019 17:40:02 +0800
Jason Wang wrote:
> On 2019/12/6 下午4:22, Yan Zhao wrote:
> > On Thu, Dec 05, 2019 at 09:05:54PM +0800, Jason Wang wrote:
> >> On 2019/12/5 下午4:51, Yan Zhao wrote:
> >>> On Thu, Dec 05, 2019 at 02:33:19PM +0800, Jason Wang wrote:
> Hi:
>
> On
On Fri, 6 Dec 2019 at 15:04, Paolo Bonzini wrote:
>
> The following changes since commit 1bdc319ab5d289ce6b822e06fb2b13666fd9278e:
>
> Update version for v4.2.0-rc4 release (2019-12-03 17:56:30 +)
>
> are available in the Git repository at:
>
> git://github.com/bonzini/qemu.git tags/for-up
This series implements tests exercising the PMUv3 event counters.
It tests both the 32-bit and 64-bit versions. Overflow interrupts
also are checked. Those tests only are written for arm64.
It allowed to reveal some issues related to SW_INCR implementation
(esp. related to 64-bit implementation),
Add the INTEL_IGD_PASSTHROUGH Kconfig option.
Since it is implied by the PCI_I440FX option, this does not change
the default selection. However users are now able to deselelect it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/Kconfig | 4
hw/pci-host/Makefile.objs | 2 +-
2
On Fri, Dec 06, 2019 at 09:00:11AM -0500, Wainer dos Santos Moschetta wrote:
> QEMU 4.0 onward is able to boot an uncompressed kernel
> image by using the x86/HVM direct boot ABI. It needs
> Linux >= 4.21 built with CONFIG_PVH=y.
>
> This introduces an acceptance test which checks an
> uncompresse
Use definitions from "hw/pci/pci_regs.h".
This also helps when using git-grep.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/i440fx.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index 0cc80b276d..414138595
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> When VHE is enabled, we need to take the aa32-ness of EL0
> from PSTATE not HCR_EL2, which is controlling EL1.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(
This struct aims at storing information potentially used by
all tests such as the pmu version, the read-only part of the
PMCR, the number of implemented event counters, ...
Signed-off-by: Eric Auger
---
arm/pmu.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> When TGE+E2H are both set, CPACR_EL1 is ignored.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
Make the PCII440FXState structure public, so it can be used out of
this source file. This will allow us to extract the IGD Passthrough
Host Bridge, which is a children of the TYPE_I440FX_PCI_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci-host/i440fx.h | 19 +--
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> The fall through organization of this function meant that we
> would raise an interrupt, then might overwrite that with another.
> Since interrupt prioritization is IMPLEMENTATION DEFINED, we
> can recognize these in any order we choose.
>
Introduce a kconfig selector to allow builds without Intel
Integrated Graphics Device GPU PCIe passthrough.
We keep the default as enabled.
v2:
- do not mix with vfio code (Alex)
- extract to different file to avoid #ifdef (Thomas)
Philippe Mathieu-Daudé (6):
hw/pci-host/i440fx: Correct the he
On 2019/12/6 16:56, Amit Shah wrote:
> On Fri, 2019-12-06 at 10:17 +0800, Pan Nengyuan wrote:
>> On 2019/12/6 0:45, Amit Shah wrote:
>>> On Wed, 2019-12-04 at 15:31 +0800, pannengy...@huawei.com wrote:
From: Pan Nengyuan
>>>
>>> Shouldn't this be From: mst?
>>>
>>> I didn't find a ref to th
Missed during the refactor in commits 14a026dd58 and 0f25d865a,
this file is now only about the i440FX chipset.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/i440fx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index f27
Vladimir Sementsov-Ogievskiy writes:
> Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Markus Armbruster
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> For ARMv8.1, op1 == 5 is reserved for EL2 aliases of
> EL1 and EL0 registers.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/target/arm/helper.
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> The TGE bit routes all asynchronous exceptions to EL2.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index b059d
Vladimir Sementsov-Ogievskiy writes:
> Mostly, Error ** is for returning error from the function, so the
> callee sets it. However these three functions get already filled errp
> parameter. They dont change the pointer itself, only change the
> internal state of referenced Error object. So we can
On Fri, 6 Dec 2019 17:36:42 +1100
Gavin Shan wrote:
> object_dynamic_cast() should return machine (or GPIO) state instad of NMI
> state in do_nmi(). So it's wrong to convert it to NMI state unconditionally.
>
object_dynamic_cast() returns either its first argument if it can be cast
to the give
On Tue, 3 Dec 2019 at 02:29, Richard Henderson
wrote:
>
> The EL1&0 regime is the only one that uses 2-stage translation.
...now what happens when we support secure EL2 and we need a
secure stage 2 MMUIdx ?
thanks
-- PMM
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
wrote:
>
> From: Alex Bennée
>
> According to ARM ARM we should only trap from the EL1&0 regime.
>
> Signed-off-by: Alex Bennée
> Signed-off-by: Richard Henderson
> ---
> target/arm/pauth_helper.c | 5 -
Reviewed-by: Peter Maydell
thanks
--
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