Cornelia Huck writes:
> On Sat, 30 Nov 2019 20:42:36 +0100
> Markus Armbruster wrote:
>
> I don't really want to restart the discussion :), but what about:
>
>> cpu_model_from_info() is a helper for qmp_query_cpu_model_expansion(),
>> qmp_query_cpu_model_comparison(), qmp_query_cpu_model_baselin
On 12/3/19 8:29 AM, Thomas Huth wrote:
It's been deprecated since QEMU v3.1. The 40p machine should be
used nowadays instead.
Signed-off-by: Thomas Huth
---
.gitmodules| 3 -
MAINTAINERS| 1 -
Makefile | 2 +-
docs/interop/firmware.js
On 12/2/19 11:49 PM, Markus Armbruster wrote:
> Yury Kotov writes:
>
>> Hi!
>>
>> 29.11.2019, 11:22, "Markus Armbruster" :
>>> Yury Kotov writes:
>>>
The monitor_can_read (as a callback of qemu_chr_fe_set_handlers)
should return size of buffer which monitor_qmp_read or monitor_read
>>
It's been deprecated since QEMU v3.1. The 40p machine should be
used nowadays instead.
Signed-off-by: Thomas Huth
---
.gitmodules| 3 -
MAINTAINERS| 1 -
Makefile | 2 +-
docs/interop/firmware.json | 3 +-
hw/ppc/ppc.c | 18
David Hildenbrand writes:
> [...]
>
>> First search hit. Here's my second one:
>>
>> Q: What are latent bugs?
>>
>> A: These bugs do not cause problems today. However, they are lurking
>> just waiting to reveal themselves later. The Ariane 5 rocket
>> failure was caused by a f
David Hildenbrand writes:
> On 30.11.19 20:42, Markus Armbruster wrote:
>> s390x-cpu property setters set_feature() and set_feature_group() crash
>> when the visitor fails and its @errp argument is null. Messed up in
>> commit 0754f60429 "s390x/cpumodel: expose features and feature groups
>> as
Greg Kurz writes:
> On Fri, 29 Nov 2019 16:08:01 +0100
> Paolo Bonzini wrote:
>
>> Libcap was dropped from virtio-9p, so remove it from the dockerfiles as well.
>>
>> Signed-off-by: Paolo Bonzini
>> ---
>
> Similarly to what was discussed in these threads:
>
> 20191129111632.22840-2-pbonz...
"Michael S. Tsirkin" writes:
> On Tue, Dec 03, 2019 at 07:00:53AM +0100, Markus Armbruster wrote:
>> "Michael S. Tsirkin" writes:
>>
>> > On Tue, Dec 03, 2019 at 08:53:30AM +0800, Tao Xu wrote:
>> >> Hi Michael,
>> >>
>> >> Could this patch series be queued?
>> >> Thank you very much!
>> >>
>
On 03.12.19 06:53, Liang Yan wrote:
>
> On 12/2/19 1:16 AM, Jan Kiszka wrote:
>> On 27.11.19 18:19, Jan Kiszka wrote:
>>> Hi Liang,
>>>
>>> On 27.11.19 16:28, Liang Yan wrote:
On 11/11/19 7:57 AM, Jan Kiszka wrote:
> To get the ball rolling after my presentation of the topic at
On 12/3/2019 2:25 PM, Michael S. Tsirkin wrote:
On Tue, Dec 03, 2019 at 07:00:53AM +0100, Markus Armbruster wrote:
"Michael S. Tsirkin" writes:
On Tue, Dec 03, 2019 at 08:53:30AM +0800, Tao Xu wrote:
Hi Michael,
Could this patch series be queued?
Thank you very much!
Tao
QEMU is in freez
On 12/3/19 3:29 AM, Richard Henderson wrote:
The value computed is fully boolean; using int8_t is odd.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/t
On 12/3/19 3:29 AM, Richard Henderson wrote:
Avoid redundant computation of cpu state by passing it in
from the caller, which has already computed it for itself.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 22 --
1 file
On 12/3/19 3:29 AM, Richard Henderson wrote:
This inline function has one user in cpu.c, and need not be exposed
otherwise. Code movement only, with fixups for checkpatch.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/cpu.h | 111 ---
On Tue, Dec 03, 2019 at 07:00:53AM +0100, Markus Armbruster wrote:
> "Michael S. Tsirkin" writes:
>
> > On Tue, Dec 03, 2019 at 08:53:30AM +0800, Tao Xu wrote:
> >> Hi Michael,
> >>
> >> Could this patch series be queued?
> >> Thank you very much!
> >>
> >> Tao
> >
> > QEMU is in freeze, so not
On 12/3/19 3:29 AM, Richard Henderson wrote:
Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants.
Keep the definitions short by referencing previous symbols.
Nice trick :)
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 16 ++
On 12/3/19 3:29 AM, Richard Henderson wrote:
No functional change, but unify code sequences.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Easier to review in 2 patches: vae1_tlbmask first, then vmalle1_tlbmask.
If you need to respin, the 2 patches are welcome. Regardless:
Revie
On 12/3/19 5:14 AM, Andrew Jeffery wrote:
This matches the configuration set by u-boot on the AST2600.
Signed-off-by: Andrew Jeffery
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast2600.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/aspeed
On 12/3/19 5:14 AM, Andrew Jeffery wrote:
The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On
recent firmwares this is at 1125MHz, which is considerably quicker than
the assumed 62.5MHz of the current generic timer implementation. The
delta between the value as read from CNTFRQ an
On 2019/12/3 13:37, Michael S. Tsirkin wrote:
> On Tue, Dec 03, 2019 at 08:53:42AM +0800, pannengyuan wrote:
>>
>>
>> On 2019/12/2 21:58, Laurent Vivier wrote:
>>> On 02/12/2019 12:15, pannengy...@huawei.com wrote:
From: PanNengyuan
ivqs/ovqs/c_ivq/c_ovq is forgot to cleanup in
>
On 2019/12/3 13:34, Michael S. Tsirkin wrote:
> On Tue, Dec 03, 2019 at 09:44:19AM +0800, pannengy...@huawei.com wrote:
>> From: PanNengyuan
>>
>> ivq/dvq/svq/free_page_vq is forgot to cleanup in
>> virtio_balloon_device_unrealize, the memory leak stack is as follow:
>>
>> Direct leak of 14336
On 12/3/19 5:14 AM, Andrew Jeffery wrote:
Prepare for SoCs such as the ASPEED AST2600 whose firmware configures
CNTFRQ to values significantly larger than the static 62.5MHz value
currently derived from GTIMER_SCALE. As the OS potentially derives its
timer periods from the CNTFRQ value the lack o
On 12/3/19 5:14 AM, Andrew Jeffery wrote:
Hello,
This is a v2 of the belated follow-up from a few of my earlier attempts to fix
up the ARM generic timer for correct behaviour on the ASPEED AST2600 SoC. The
AST2600 clocks the generic timer at the rate of HPLL, which is configured to
1125MHz. Thi
"Michael S. Tsirkin" writes:
> On Tue, Dec 03, 2019 at 08:53:30AM +0800, Tao Xu wrote:
>> Hi Michael,
>>
>> Could this patch series be queued?
>> Thank you very much!
>>
>> Tao
>
> QEMU is in freeze, so not yet. Please ping after the release.
Just to avoid confusion: it's Michael's personal pr
On 12/3/2019 1:35 PM, Michael S. Tsirkin wrote:
On Tue, Dec 03, 2019 at 08:53:30AM +0800, Tao Xu wrote:
Hi Michael,
Could this patch series be queued?
Thank you very much!
Tao
QEMU is in freeze, so not yet. Please ping after the release.
OK, Thank you!
On Tue, Dec 03, 2019 at 08:53:42AM +0800, pannengyuan wrote:
>
>
> On 2019/12/2 21:58, Laurent Vivier wrote:
> > On 02/12/2019 12:15, pannengy...@huawei.com wrote:
> >> From: PanNengyuan
> >>
> >> ivqs/ovqs/c_ivq/c_ovq is forgot to cleanup in
> >> virtio_serial_device_unrealize, the memory leak
On Tue, Dec 03, 2019 at 08:53:30AM +0800, Tao Xu wrote:
> Hi Michael,
>
> Could this patch series be queued?
> Thank you very much!
>
> Tao
QEMU is in freeze, so not yet. Please ping after the release.
--
MST
On Tue, Dec 03, 2019 at 09:44:19AM +0800, pannengy...@huawei.com wrote:
> From: PanNengyuan
>
> ivq/dvq/svq/free_page_vq is forgot to cleanup in
> virtio_balloon_device_unrealize, the memory leak stack is as follow:
>
> Direct leak of 14336 byte(s) in 2 object(s) allocated from:
> #0 0x7f99f
On 03/12/2019 14:44, Alexey Kardashevskiy wrote:
>
>
> On 29/11/2019 12:35, David Gibson wrote:
>> Move the calculation of the Real Mode Area (RMA) size into a helper
>> function. While we're there clean it up and correct it in a few ways:
>> * Add comments making it clearer where the vario
On Mon, Dec 02, 2019 at 08:05:13AM +0100, Cédric Le Goater wrote:
> On 29/11/2019 06:33, David Gibson wrote:
> > This series contains several cleanups to the handling of the
> > ibm,client-architecture-support firmware call used for boot time
> > feature negotiation between the guest OS and the fir
On 29/11/2019 12:35, David Gibson wrote:
> The Real Mode Area (RMA) needs to fit within Node 0 in NUMA configurations.
> We use a helper function spapr_node0_size() to calculate this.
>
> But that function doesn't actually get the size of Node 0, it gets the
> minimum size of all nodes, ever si
Prepare for SoCs such as the ASPEED AST2600 whose firmware configures
CNTFRQ to values significantly larger than the static 62.5MHz value
currently derived from GTIMER_SCALE. As the OS potentially derives its
timer periods from the CNTFRQ value the lack of support for running
QEMUTimers at the appr
The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On
recent firmwares this is at 1125MHz, which is considerably quicker than
the assumed 62.5MHz of the current generic timer implementation. The
delta between the value as read from CNTFRQ and the true rate of the
underlying QEMUTimer
This matches the configuration set by u-boot on the AST2600.
Signed-off-by: Andrew Jeffery
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast2600.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 931
Hello,
This is a v2 of the belated follow-up from a few of my earlier attempts to fix
up the ARM generic timer for correct behaviour on the ASPEED AST2600 SoC. The
AST2600 clocks the generic timer at the rate of HPLL, which is configured to
1125MHz. This is significantly quicker than the currentl
The corner-case codepath was adjusting nexttick such that overflow
wouldn't occur when timer_mod() scaled the value back up. Remove a use
of GTIMER_SCALE and avoid unnecessary operations by calling
timer_mod_ns() directly.
Signed-off-by: Andrew Jeffery
Reviewed-by: Richard Henderson
Reviewed-by:
On 29/11/2019 12:35, David Gibson wrote:
> Move the calculation of the Real Mode Area (RMA) size into a helper
> function. While we're there clean it up and correct it in a few ways:
> * Add comments making it clearer where the various constraints come from
> * Remove a pointless check that
On 2019/11/27 22:17, Beata Michalska wrote:
> On Wed, 27 Nov 2019 at 13:03, Igor Mammedov wrote:
>>
>> On Wed, 27 Nov 2019 20:47:15 +0800
>> Xiang Zheng wrote:
>>
>>> Hi Beata,
>>>
>>> Thanks for you review!
>>>
>>> On 2019/11/22 23:47, Beata Michalska wrote:
Hi,
On Mon, 11 Nov 2
On 2019/11/27 22:17, Beata Michalska wrote:
> Hi
>
> On Wed, 27 Nov 2019 at 12:47, Xiang Zheng wrote:
>>
>> Hi Beata,
>>
>> Thanks for you review!
>>
> YAW
>
>> On 2019/11/22 23:47, Beata Michalska wrote:
>>> Hi,
>>>
>>> On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote:
From: Dongji
On 29/11/2019 12:35, David Gibson wrote:
> The Real Mode Area (RMA) is the part of memory which a guest can access
> when in real (MMU off) mode. Of course, for a guest under KVM, the MMU
> isn't really turned off, it's just in a special translation mode - Virtual
> Real Mode Area (VRMA) - whic
On 29/11/2019 12:35, David Gibson wrote:
> This function calculates the maximum size of the RMA as implied by the
> host's page size of structure of the VRMA (there are a number of other
> constraints on the RMA size which will supersede this one in many
> circumstances).
>
> The current interf
From: Alex Bennée
According to ARM ARM we should only trap from the EL1&0 regime.
Signed-off-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/pauth_helper.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_help
The fall through organization of this function meant that we
would raise an interrupt, then might overwrite that with another.
Since interrupt prioritization is IMPLEMENTATION DEFINED, we
can recognize these in any order we choose.
Unify the code to raise the interrupt in a block at the end.
Sign
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index a39d6fcea3..009411813f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -670,6 +670,7 @@ static void aarch64_max_initfn(Object *obj)
Prepare for, but do not yet implement, the EL2&0 regime.
This involves adding the new MMUIdx enumerators and adjusting
some of the MMUIdx related predicates to match.
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 128 ++
This inline function has one user in cpu.c, and need not be exposed
otherwise. Code movement only, with fixups for checkpatch.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 111 ---
target/arm/cpu.c | 119
The TGE bit routes all asynchronous exceptions to EL2.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b059d9f81a..e0b8c81c5f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helpe
The EL2&0 translation regime is affected by Load Register (unpriv).
The code structure used here will facilitate later changes in this
area for implementing UAO and NV.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/translate.h | 2 ++
target/arm/helper.
The value computed is fully boolean; using int8_t is odd.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7a1177b883..a366448c6d 100644
--- a/target/arm/cpu.c
+++ b/target/ar
When TGE+E2H are both set, CPACR_EL1 is ignored.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 53 -
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e0b8c81c5f..3e025eb22e 100
Since we only support a single ASID, flush the tlb when it changes.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9df55a8d6b..2a4d4c2c0d 100644
--- a/target/arm/helper.c
+++ b/
Several of the EL1/0 registers are redirected to the EL2 version when in
EL2 and HCR_EL2.E2H is set. Many of these registers have side effects.
Link together the two ARMCPRegInfo structures after they have been
properly instantiated. Install common dispatch routines to all of the
relevant registe
When VHE is enabled, we need to take the aa32-ness of EL0
from PSTATE not HCR_EL2, which is controlling EL1.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f2d18
Avoid redundant computation of cpu state by passing it in
from the caller, which has already computed it for itself.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cp
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 102 +++-
1 file changed, 81 insertions(+), 21 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a4a7f82661..023b8963cf 100644
--- a/target/arm/helper.c
+++ b/target/arm/hel
Apart from the wholesale redirection that HCR_EL2.E2H performs
for EL2, there's a separate redirection specific to the timers
that happens for EL0 when running in the EL2&0 regime.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 191 +---
1 file
Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants.
Keep the definitions short by referencing previous symbols.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 16
target/arm/helper.c| 23 ++-
target/arm/translate-a64.c | 3 +--
3 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
ind
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 1 +
target/arm/cpu.h | 11 +
target/arm/cpu.c | 2 ++
target/arm/helper.c | 57
4 files changed, 66 insertions(+), 5 deletions(-)
diff --git a/ta
The comment that we don't support EL2 is somewhat out of date.
Update to include checks against HCR_EL2.TDZ.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/h
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2a4d4c2c0d..b059d9f81a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -412
Update to include checks against HCR_EL2.TID2.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ffa82b5509..9ad5015d5c 100644
--- a/target/arm/h
Use the correct sctlr for EL2&0 regime. Due to header ordering,
and where arm_mmu_idx_el is declared, we need to move the function
out of line. Use the function in many more places in order to
select the correct control.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm
For ARMv8.1, op1 == 5 is reserved for EL2 aliases of
EL1 and EL0 registers.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 023b8963cf..1812588fa1 100644
--- a/target/
We are about to expand the number of mmuidx to 10, and so need 4 bits.
For the benefit of reading the number out of -d exec, align it to the
penultimate nibble.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/
Return the indexes for the EL2&0 regime when the appropriate bits
are set within HCR_EL2.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 27adf24fa6..c6b4c0a25
This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 2 +-
target/arm/h
This is part of a reorganization to the set of mmu_idx.
The EL3 regime only has a single stage translation, and
is always secure.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 2 +-
target/arm/helper.c| 14 +++---
target/arm/translat
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8
target/arm/internals.h | 4 ++--
target/arm/helper.c| 40 +++---
Define via macro expansion, so that renumbering of the base ARMMMUIdx
symbols is automatically reflexed in the bit definitions.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 39 +++
1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/targ
This is part of a reorganization to the set of mmu_idx.
The EL1&0 regime is the only one that uses 2-stage translation.
Spelling out Stage avoids confusion with Secure.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 6 +++---
target/arm/helper.c
This is part of a reorganization to the set of mmu_idx.
The Secure regimes all have a single stage translation;
there is no point in pointing out that the idx is for stage1.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8
target/arm/internals.h | 4 ++--
targe
The virtual offset may be 0 depending on EL, E2H and TGE.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 40 +---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
ind
We had completely run out of TBFLAG bits.
Split A- and M-profile bits into two overlapping buckets.
This results in 4 free bits.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 52 ---
target/arm/helper.c| 17 ++---
target/arm/transla
Rather than call to a separate function and re-compute any
parameters for the flush, simply use the correct flush
function directly.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 52 +
1 file changed, 24 insertion
The EL1&0 regime is the only one that uses 2-stage translation.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 +--
target/arm/internals.h | 2 +-
target/arm/helper.c| 57 --
target/arm/translate-a64.c | 2 +-
target/arm/tra
At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/tar
No functional change, but unify code sequences.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 118 ++--
1 file changed, 37 insertions(+), 81 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7
Not all of the breakpoint types are supported, but those that
only examine contextidr are extended to support the new register.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 50 +--
target/arm/helper.c | 11 ++
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 7 ---
target/arm/helper.c | 6 +-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 994cad2014..9729e62d2c 100644
--- a/target/arm/cpu.h
+++ b/targe
Version 3 was posted back in August. Though quite a lot has changed
and perhaps there's no use in comparing. I haven't done a list.
Against master, it is the first version that can actually boot a
nested kernel under kvm, so that's certainly a change for the better.
It's not even particularly s
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 83a809d4ba..994cad2014 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3632,6 +3632,11 @@ static inline bool
On 2019/12/3 2:27, Peter Maydell wrote:
>> application within guest, host does not know which application encounters
>> errors.
>>
>> For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify
>> userspace.
>> After user space gets the notification, it will record the CPER into guest
>>
On Tuesday, December 3, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Tuesday, December 3, 2019, Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Monday, December 2, 2019, Aleksandar Markovic <
>> aleksandar.m.m...@gmail.com> wrote:
>>
>>>
>>>
>>
From: PanNengyuan
ivq/dvq/svq/free_page_vq is forgot to cleanup in
virtio_balloon_device_unrealize, the memory leak stack is as follow:
Direct leak of 14336 byte(s) in 2 object(s) allocated from:
#0 0x7f99fd9d8560 in calloc (/usr/lib64/libasan.so.3+0xc7560)
#1 0x7f99fcb20015 in g_malloc0
On Tuesday, December 3, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Monday, December 2, 2019, Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Monday, December 2, 2019, Michael Rolnik wrote:
>>
>>> how can I get this elf flags from within QEMU
On 2019/12/2 21:58, Laurent Vivier wrote:
> On 02/12/2019 12:15, pannengy...@huawei.com wrote:
>> From: PanNengyuan
>>
>> ivqs/ovqs/c_ivq/c_ovq is forgot to cleanup in
>> virtio_serial_device_unrealize, the memory leak stack is as bellow:
>>
>> Direct leak of 1290240 byte(s) in 180 object(s) al
Hi Michael,
Could this patch series be queued?
Thank you very much!
Tao
On 11/29/2019 3:56 PM, Xu, Tao3 wrote:
This series of patches will build Heterogeneous Memory Attribute Table (HMAT)
according to the command line. The ACPI HMAT describes the memory attributes,
such as memory side cache a
Public bug reported:
So I have installed FreeDOS on my USB thumbdrive, by using Rufus.
Everything goes as expected so far. That's good.
When I run QEMU with this command line:
qemu-system-x86_64.exe -drive file=\\.\PhysicalDrive1
it of course is read-only, just like the resulting console message
On Mon, Dec 02, 2019 at 05:44:11PM +, Peter Maydell wrote:
> On Mon, 2 Dec 2019 at 16:08, Richard Henderson
> wrote:
> >
> > On 12/1/19 6:08 AM, David Gibson wrote:
> > >
> > > -for (i = 0; i < s->num_cpu; i++) {
> > > +/*
> > > + * This clues in gcc that our on-stack buffers do, i
If an area is non-RAM and non-ROMD, then remove mappings so accesses
will trap and can be emulated. Change hvf_find_overlap_slot() to take
a size instead of an end address: it wouldn't return a slot because
callers would pass the same address for start and end. Don't always
map area as read/write
The existing code in QEMU's HVF support to attempt to synchronize TSC
across multiple cores is not sufficient. TSC value on other cores
can go backwards. Until implementation is fixed, remove calls to
hv_vm_sync_tsc(). Pass through TSC to guest OS.
Signed-off-by: Cameron Esfahani
Signed-off-by
More accurately match SDM when setting CR0 and PDPTE registers.
Clear PDPTE registers when resetting vcpus.
Signed-off-by: Cameron Esfahani
Signed-off-by: Paolo Bonzini
---
target/i386/hvf/hvf.c | 8
target/i386/hvf/vmx.h | 18 ++
2 files changed, 18 insertions(+), 8
The following patches fix stability issues with running QEMU on Apple
Hypervisor Framework (HVF):
- non-RAM, non-ROMD areas need to trap so accesses can be correctly
emulated.
- Current TSC synchronization implementation is insufficient: when
running with more than 1 core, TSC values can go bac
Previous implementation in hvf_inject_interrupts() would always inject
VMCS_INTR_T_SWINTR even when VMCS_INTR_T_HWINTR was required. Now
correctly determine when VMCS_INTR_T_HWINTR is appropriate versus
VMCS_INTR_T_SWINTR.
Make sure to clear ins_len and has_error_code when ins_len isn't
valid and
In real x86 processors, the REX prefix must come after legacy prefixes.
REX before legacy is ignored. Update the HVF emulation code to properly
handle this. Fix some spelling errors in constants. Fix some decoder
table initialization issues found by Coverity.
Signed-off-by: Cameron Esfahani
Si
On Tue, 3 Dec 2019, at 04:42, Peter Maydell wrote:
> On Thu, 28 Nov 2019 at 05:44, Andrew Jeffery wrote:
> >
> > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures
> > CNTFRQ to values significantly larger than the static 62.5MHz value
> > currently derived from GTIMER_SCALE.
On Monday, December 2, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Monday, December 2, 2019, Michael Rolnik wrote:
>
>> how can I get this elf flags from within QEMU?
>>
>>>
>>>
> In one of files from your "machine" patch, you have this snippet:
>
> +bytes_loa
On Mon, Dec 02, 2019 at 11:36:35AM -0700, Warner Losh wrote:
>
> Just make sure that any pipeline and mandatory CI steps don't slow things
> down too much... While the examples have talked about 1 or 2 pull requests
> getting done in parallel, and that's great, the problem is when you try to
> lan
On 11/4/19 6:27 AM, Max Reitz wrote:
> On 04.11.19 12:21, Max Reitz wrote:
>> On 01.11.19 16:42, John Snow wrote:
>>> Hi, in one of my infamously unreadable and long status emails, I
>>> mentioned possibly wanting to copy allocation data into bitmaps as a way
>>> to enable users to create (exter
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank
---
hw/arm/allwinner-h3.c | 11 ++
hw/misc/Makefile
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