Ping?
On 2019/6/4 16:53, l00284672 wrote:
Hi, I found a problem that virtual machine cpu soft lockup when I
attach a disk to the vm in the case that
backend storage network has a large delay or IO pressure is too large.
1) The disk xml which I attached is:
Changes v1 -> v2:
* I've decided to get rid of the status-message and
suggested-alternative fields, to avoid more bikeshedding.
This series adds machine type deprecation information to the
output of the `query-machines` QMP command. With this, libvirt
and management software will be able to sho
Export machine type deprecation status through the query-machines
QMP command. With this, libvirt and management software will be
able to show this information to users and/or suggest changes to
VM configuration to avoid deprecated machines.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
*
On 6/6/19 12:46 PM, Peter Maydell wrote:
> For VFP short vectors, the VFP registers are divided into a
> series of banks: for single-precision these are s0-s7, s8-s15,
> s16-s23 and s24-s31; for double-precision they are d0-d3,
> d4-d7, ... d28-d31. Some banks are "scalar" meaning that
> use of a r
On 6/6/19 12:46 PM, Peter Maydell wrote:
> Convert the float-to-integer VCVT instructions to decodetree.
> Since these are the last unconverted instructions, we can
> delete the old decoder structure entirely now.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 72
On 6/6/19 12:46 PM, Peter Maydell wrote:
> Convert the VCVTT and VCVTB instructions which convert from
> f32 and f64 to f16 to decodetree.
>
> Since we're no longer constrained to the old decoder's style
> using cpu_F0s and cpu_F0d we can perform a direct 16 bit
> store of the right half of the in
On 6/6/19 12:46 PM, Peter Maydell wrote:
> Convert the VCVT integer-to-float instructions to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 58 ++
> target/arm/translate.c | 12 +--
> target/arm/vfp.decode
On 6/6/19 12:46 PM, Peter Maydell wrote:
> Convert the VCVTT, VCVTB instructions that deal with conversion
> from half-precision floats to f32 or 64 to decodetree.
>
> Since we're no longer constrained to the old decoder's style
> using cpu_F0s and cpu_F0d we can perform a direct 16 bit
> load of
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 10 ++
> target/arm/translate.c | 8 +---
> target/arm/vfp.decode | 5 +
> 3 files changed, 16 insertions(+), 7 deletions(-)
Reviewed-by: Richard He
On 6/6/19 12:46 PM, Peter Maydell wrote:
> +static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
> +{
> +TCGv_i32 vd;
> +TCGv_i64 vm;
> +
> +/* UNDEF accesses to D16-D31 if they don't exist. */
> +if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
> +return false;
>
On 6/6/19 12:46 PM, Peter Maydell wrote:
> Convert the VCVT double/single precision conversion insns to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 48 ++
> target/arm/translate.c | 13 +
> target/arm/vfp.d
On 6/6/19 12:46 PM, Peter Maydell wrote:
> Convert the VFP round-to-integer instructions VRINTR, VRINTZ and
> VRINTX to decodetree.
>
> These instructions were only introduced as part of the "VFP misc"
> additions in v8A, so we check this. The old decoder's implementation
> was incorrectly providi
On 6/6/19 12:46 PM, Peter Maydell wrote:
> Convert the VCVT (between floating-point and fixed-point) instructions
> to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 124 +
> target/arm/translate.c | 57 +
On 6/6/19 12:45 PM, Peter Maydell wrote:
> +n = (a->imm4h << 28) & 0x8000;
> +i = ((a->imm4h << 4) & 0x70) | a->imm4l;
> +if (i & 0x40) {
> +i |= 0x780;
> +} else {
> +i |= 0x800;
> +}
> +n |= i << 19;
Can we reuse vfp_expand_imm here? Given that you do
On 6/6/19 12:45 PM, Peter Maydell wrote:
> +VFM_sp 1110 1.01 1010 . o2:1 . 0 \
> + vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
> +VFM_dp 1110 1.01 1011 . o2:1 . 0 \
> + vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=1
> +VFM_sp 1110 1.
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VSUB instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 10 ++
> target/arm/translate.c | 6 +-
> target/arm/vfp.decode | 5 +
> 3 files changed, 16 inserti
On 6/6/19 12:46 PM, Peter Maydell wrote:
> +vd = tcg_temp_new_i32();
> +vm = tcg_temp_new_i32();
> +
> +neon_load_reg32(vd, a->vd);
> +if (a->z) {
> +tcg_gen_movi_i32(vm, 0);
> +} else {
> +neon_load_reg32(vm, a->vm);
> +}
> +
> +if (a->e) {
> +ge
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VSQRT instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 20
> target/arm/translate.c | 14 +-
> target/arm/vfp.decode | 5 +
> 3 files
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VDIV instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 10 ++
> target/arm/translate.c | 21 +
> target/arm/vfp.decode | 5 +
> 3 files chan
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VNEG instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 10 ++
> target/arm/translate.c | 6 +-
> target/arm/vfp.decode | 5 +
> 3 files changed, 16 inserti
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP VABS instruction to decodetree.
>
> Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or
> VFPGen2OpDPFn because none of the operations which use this format
> and support short vectors will need it.
>
> Signed-off-by: Pet
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VMUL instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 10 ++
> target/arm/translate.c | 5 +
> target/arm/vfp.decode | 5 +
> 3 files changed, 16 insertio
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP VNMLA instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 34 ++
> target/arm/translate.c | 19 +--
> target/arm/vfp.decode
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VADD instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 10 ++
> target/arm/translate.c | 6 +-
> target/arm/vfp.decode | 5 +
> 3 files changed, 16 inserti
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VNMUL instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 24
> target/arm/translate.c | 7 +--
> target/arm/vfp.decode | 5 +
> 3 files cha
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP VNMLS instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 42 ++
> target/arm/translate.c | 24 +--
> target/arm/vfp.decode
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP VMLS instruction to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 38 ++
> target/arm/translate.c | 8 +--
> target/arm/vfp.decode | 5 +
>
>
> On Tue, 14 May 2019 04:18:20 -0700
> Dongjiu Geng wrote:
>
> > This implements APEI GHES Table generation via fw_cfg blobs.
> > Now it only support GPIO-Signal and ARMv8 SEA two types of GHESv2
> > error source. Afterwards, we can extend the supported types if needed.
> > For the CPER sectio
>
> On Tue, 14 May 2019 04:18:23 -0700
> Dongjiu Geng wrote:
>
> > Add SIGBUS signal handler. In this handler, it checks the SIGBUS type,
> > translates the host VA delivered by host to guest PA, then fill this
> > PA to guest APEI GHES memory, then notify guest according to the SIGBUS
> > type
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP VMLA instruction to decodetree.
>
> This is the first of the VFP 3-operand data processing instructions,
> so we include in this patch the code which loops over the elements
> for an old-style VFP vector operation. The existing code to do
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans
> functions which perform the memory accesses by going via the TCG
> globals cpu_F0s and cpu_F0d, to use local TCG temps instead.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/t
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP load/store multiple insns to decodetree.
> This includes tightening up the UNDEF checking for pre-VFPv3
> CPUs which only have D0-D15 : they now UNDEF for any access
> to D16-D31, not merely when the smallest register in the
> transfer list
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP single load/store insns VLDR and VSTR to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c | 73 ++
> target/arm/translate.c | 22 +-
> target/arm/vfp.deco
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP two-register transfer instructions to decodetree
> (in the v8 Arm ARM these are the "Advanced SIMD and floating-point
> 64-bit move" encoding group).
>
> Again, we expand out the sequences involving gen_vfp_msr() and
> gen_msr_vfp().
>
>
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