16.04.2019 18:38, Markus Armbruster wrote:
> Before the from qerror_report() to error_setg(), hints looked like
> this:
>
> qerror_report(QERR_MACRO, ... arguments ...);
> error_printf_unless_qmp(... hint ...);
>
> error_printf_unless_qmp() made perfect sense: it printed exactly when
>
On Tue, Apr 16, 2019 at 11:59:43PM -0300, Eduardo Habkost wrote:
> The hardcoded CPU models in the code are just CPU models and
> don't include any extra options. We don't need to call
> parse_cpu_options().
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: David Gibson
> ---
> bsd-user/main.c
On Tue, Apr 16, 2019 at 11:59:41PM -0300, Eduardo Habkost wrote:
> The new function will be useful in user mode, when we already
> have a CPU model and don't need to parse any extra options.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: David Gibson
> ---
> include/qom/cpu.h | 9 +
On Tue, Apr 16, 2019 at 11:59:44PM -0300, Eduardo Habkost wrote:
> The ppc implementation of parse_features() requires the machine
> object to be created before it gets called. This is far from
> obvious when reading the code at main().
>
> Instead of making it call qdev_get_machine(), require th
On Tue, Apr 16, 2019 at 11:59:42PM -0300, Eduardo Habkost wrote:
> The return value of cpu_get_model() is just a CPU model name and
> never includes extra options. We don't need to call
> parse_cpu_option().
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: David Gibson
> ---
> linux-user/main
On Tue, Apr 16, 2019 at 11:59:40PM -0300, Eduardo Habkost wrote:
> The "model[,option...]" string parsed by the function is not just
> a CPU model. Rename the function and its argument to indicate it
> expects the full "-cpu" option to be provided.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by
Eduardo Habkost writes:
> My initial goal was simple: removing the qdev_get_machine() call
> from ppc_cpu_parse_featurestr() because I want to make
> qdev_get_machine() available only to softmmu code.
>
> Before doing this, I had to make *-user not call
> CPUClass::parse_features() anymore (it wa
Eduardo Habkost writes:
> The ppc implementation of parse_features() requires the machine
> object to be created before it gets called. This is far from
> obvious when reading the code at main().
>
> Instead of making it call qdev_get_machine(), require the caller
> of parse_cpu_option() to prov
Patchew URL:
https://patchew.org/QEMU/20190417053225.27505-1-richard.hender...@linaro.org/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT
Eduardo Habkost writes:
> The new function will be useful in user mode, when we already
> have a CPU model and don't need to parse any extra options.
>
> Signed-off-by: Eduardo Habkost
> ---
> include/qom/cpu.h | 9 +
> exec.c| 22 --
> 2 files changed,
Patchew URL:
https://patchew.org/QEMU/20190417053225.27505-1-richard.hender...@linaro.org/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin
This is a third variant attempting to fix the problem of
the -L interp_prefix handling not coping well pointing to
a full chroot.
Previous versions include:
https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg06592.html
https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg07304.html
Both
If one uses -L $PATH to point to a full chroot, the startup time
is significant. In addition, the existing probing algorithm fails
to handle symlink loops.
Instead, probe individual paths on demand. Cache both positive
and negative results within $PATH, so that any one filename is
probed only on
Like Xu writes:
> This patch makes the remaining dozen or so uses of the global
> current_machine outside vl.c use qdev_get_machine() instead,
> and then make current_machine local to vl.c instead of global.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Like Xu
I'm afraid I dislike this one
Eduardo Habkost writes:
> On Mon, Apr 15, 2019 at 03:59:45PM +0800, Like Xu wrote:
>> To avoid the misuse of qdev_get_machine() if machine hasn't been created yet,
>> this patch uses qdev_get_machine_uncheck() for obj-common (share with
>> user-only
>> mode) and adds type assertion to qdev_get_m
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Mostly courtesy of Richard H.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 34 +
> 2 files changed, 36 insertions(+)
Reviewed-by: Richard H
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Let's keep it simple for now and handle 8/16 bit elements via helpers.
> Especially for 8/16, we could come up with some bit tricks.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/helper.h | 2 ++
> target/s390x/insn-data.def
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Inline expansion courtesy of Richard H.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 29 +
> 2 files changed, 31 insertions(+)
Reviewed-by: Ric
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Use the new vector expansion for GVecGen3i.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/helper.h | 2 ++
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 51 +
>
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Implement it similar to VECTOR COUNT LEADING ZEROS.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/helper.h | 2 ++
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 28
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Similar to VECTOR ADD COMPUTE CARRY, however 128-bit handling only.
> Courtesy of Richard H.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 32 +++
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> 128-bit handling courtesy of Richard H.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 +
> target/s390x/translate_vx.inc.c | 94 +
> 2 files changed, 96 insertions(+)
Reviewed-by:
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
> without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
> for now.
>
> Signed-off-by: David Hildenbrand
> ---
> tcg/tcg-op-gvec.c | 139 +
On 4/16/19 9:43 AM, Thomas Huth wrote:
> I wonder whether we should maybe always add "-Wno-typedef-redefinition"
> in the configure script when we detect clang. All the versions of GCC
> that we currently support seem to ignore typedef redefinitions anyway...?
> (I think I've seen that warning with
On Mon, Apr 15, 2019 at 03:42:46PM +0530, Aravinda Prasad wrote:
>
>
> On Tuesday 26 March 2019 05:03 AM, David Gibson wrote:
> > On Mon, Mar 25, 2019 at 02:27:45PM +0530, Aravinda Prasad wrote:
> >>
> >>
> >> On Monday 25 March 2019 12:02 PM, David Gibson wrote:
> >>> On Fri, Mar 22, 2019 at 12:
On Tue, Apr 16, 2019 at 02:55:52PM +1000, Nicholas Piggin wrote:
> These implementations have a few deficiencies that are noted, but are
> good enough for Linux to use.
>
> Signed-off-by: Nicholas Piggin
> ---
>
> v3: Removed wrong comment about GPR3, drop H_JOIN for now (at least until
> it is
On Mon, Apr 15, 2019 at 03:06:43PM +1000, Nicholas Piggin wrote:
> David Gibson's on April 15, 2019 2:13 pm:
> > On Fri, Apr 12, 2019 at 07:36:03PM +1000, Nicholas Piggin wrote:
> >> These implementations have a few deficiencies that are noted, but are
> >> good enough for Linux to use.
> >>
> >>
The ppc implementation of parse_features() requires the machine
object to be created before it gets called. This is far from
obvious when reading the code at main().
Instead of making it call qdev_get_machine(), require the caller
of parse_cpu_option() to provide the machine object.
This makes t
The hardcoded CPU models in the code are just CPU models and
don't include any extra options. We don't need to call
parse_cpu_options().
Signed-off-by: Eduardo Habkost
---
bsd-user/main.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/bsd-user/main.c b/bsd-user/main.c
in
The return value of cpu_get_model() is just a CPU model name and
never includes extra options. We don't need to call
parse_cpu_option().
Signed-off-by: Eduardo Habkost
---
linux-user/main.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/linux-user/main.c b/linux-user/mai
The "model[,option...]" string parsed by the function is not just
a CPU model. Rename the function and its argument to indicate it
expects the full "-cpu" option to be provided.
Signed-off-by: Eduardo Habkost
---
include/qom/cpu.h | 6 +++---
bsd-user/main.c | 2 +-
exec.c| 4 +
The new function will be useful in user mode, when we already
have a CPU model and don't need to parse any extra options.
Signed-off-by: Eduardo Habkost
---
include/qom/cpu.h | 9 +
exec.c| 22 --
2 files changed, 21 insertions(+), 10 deletions(-)
diff -
My initial goal was simple: removing the qdev_get_machine() call
from ppc_cpu_parse_featurestr() because I want to make
qdev_get_machine() available only to softmmu code.
Before doing this, I had to make *-user not call
CPUClass::parse_features() anymore (it was pointless to call it,
anyway).
Whi
build_append_foo() API doesn't need explicit endianness conversions
which eliminates a source of errors and it makes build_mcfg() look like
declarative definition of MCFG table in ACPI spec, which makes it easy
to review.
Signed-off-by: Wei Yang
Suggested-by: Igor Mammedov
---
hw/acpi/pci.c
This patch set tries to generalize MCFG table build process. And it is
based on one un-merged patch from Igor, which is included in this serials.
v2->v3:
* Includes the un-merged patch from Igor
* use build_append_foo() API to construct MCFG
Igor Mammedov (1):
q35: acpi: do not create d
mcfg_start points to the start of MCFG table and is used in
build_header. While this information could be derived from mcfg.
This patch removes the unnecessary variable mcfg_start.
Signed-off-by: Wei Yang
Reviewed-by: Igor Mammedov
Reviewed-by: Philippe Mathieu-Daudé
---
hw/arm/virt-acpi-buil
Now we have two identical build_mcfg functions.
Consolidate them in acpi/pci.c.
Signed-off-by: Wei Yang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
---
v3:
* adjust changelog based on Igor's suggestion
---
default-configs/arm-softmmu.mak | 1 +
default-configs/i386-sof
Thanks Stefan and Dongli for your feedback and advices!
I will do the further investigation per your advices and get back to you later
on.
Thanks,
-Wei
On 4/16/19, 2:20 AM, "Stefan Hajnoczi" wrote:
On Tue, Apr 16, 2019 at 07:23:38AM +0800, Dongli Zhang wrote:
>
>
> On 4/16
From: Igor Mammedov
Dummy table (with signature "QEMU") creation came from original SeaBIOS
codebase. And QEMU would have to keep it around if there were Q35 machine
that depended on keeping ACPI tables blob constant size. Luckily there
were no versioned Q35 machine types before commit:
(since
To build MCFG, two information is necessary:
* bus number
* base address
Abstract these two information to AcpiMcfgInfo so that build_mcfg and
build_mcfg_q35 will have the same declaration.
Signed-off-by: Wei Yang
Reviewed-by: Philippe Mathieu-Daudé
---
v3:
* move AcpiMcfgInfo to pc
This is obvious the member in AcpiMcfgInfo describe MCFG's property.
Remove the mcfg_ prefix.
Signed-off-by: Wei Yang
Suggested-by: Igor Mammedov
Reviewed-by: Igor Mammedov
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-build.c | 14 +++---
1 file changed, 7 insertions(+), 7 de
Thanks Paolo for your response and clarification.
Btw, is there any rough schedule about when are you planning to start working
on the multi queue feature? Once you start working on the feature, I would
like to hear more details about the design and better understand how this
feature will ben
> On Apr 10, 2019, at 16:01, Philippe Mathieu-Daudé wrote:
>
> So your description and patch makes sens.
> What worries me is the controller could have other pending IRQs to
> deliver and you are clearing them. Shouldn't we only clear the
> INTR_TXINT bit, and call escc_update_irq() which shou
The SCC/ESCC will briefly stop asserting an interrupt when the
transmit FIFO is filled.
This code doesn't model the transmit FIFO/shift register so the
pending transmit interrupt is never deasserted which means that an
edge-triggered interrupt controller will never see the low-to-high
transition i
On Tue, 16 Apr 2019 at 20:33, Peter Maydell wrote:
>
> On Tue, 16 Apr 2019 at 18:27, Peter Maydell wrote:
> > Having thought a bit more I think I'd definitely like to apply
> > just patch 2 for 4.0. Could people try to test that and confirm
> > that it at least does not make the feature behave an
On Mon, Apr 15, 2019 at 03:01:28PM +0200, Philippe Mathieu-Daud?? wrote:
>Hi Wei,
>
>On 4/15/19 9:03 AM, Wei Yang wrote:
>> Now we have two identical build_mcfg function.
>>
>> Extract them to pci.c.
>>
>> Signed-off-by: Wei Yang
>>
>> ---
>> v2:
>> * put it to dedicated file pci.c
>> ---
>>
> From: Mateja Marjanovic
> >>
> >> +void helper_msa_ilvr_b(CPUMIPSState *env, uint32_t wd,
> >> + uint32_t ws, uint32_t wt)
> >> +{
> >> +wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
> >> +wr_t *pws = &(env->active_fpu.fpr[ws].wr);
> >> +wr_t *pwt = &(env->active_f
On Mon, Apr 15, 2019 at 03:59:45PM +0800, Like Xu wrote:
> To avoid the misuse of qdev_get_machine() if machine hasn't been created yet,
> this patch uses qdev_get_machine_uncheck() for obj-common (share with
> user-only
> mode) and adds type assertion to qdev_get_machine() in system-emulation mod
On Mon, Apr 15, 2019 at 03:59:44PM +0800, Like Xu wrote:
> This patch makes the remaining dozen or so uses of the global
> current_machine outside vl.c use qdev_get_machine() instead,
> and then make current_machine local to vl.c instead of global.
>
> Suggested-by: Peter Maydell
> Signed-off-by:
** Attachment added: "This is my foreign /bin/bash, of note the first 1k
appears to be mis-handled"
https://bugs.launchpad.net/qemu/+bug/1825002/+attachment/5256368/+files/bash
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https
On 16/04/2019 19.32, Richard Henderson wrote:
> On 4/16/19 7:22 AM, Richard Henderson wrote:
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index fb66e886bf..c96c616539 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -695,6 +695,7 @@ static b
On Tue, Apr 16, 2019 at 9:13 AM Stefan Weil wrote:
> On 16.04.19 09:41, Stefano Garzarella wrote:
> > there was an issue when we introduced PVH support and we fixed it. [1]
> > Maybe the build that you used (20190218) was compiled before the merge of
> > that fix (20190311).
>
> The build of qemu-
Daniel P. Berrangé writes:
> The ObjectInfo struct has a variable length array containing the UTF-16
> encoded filename. The number of characters of trailing data is given by
> the 'length' field in the struct and this must be validated against the
> size of the data packet received from the gues
On Tue, 16 Apr 2019 at 18:27, Peter Maydell wrote:
>
> On Tue, 16 Apr 2019 at 14:35, Peter Maydell wrote:
> >
> > On Mon, 15 Apr 2019 at 16:45, Daniel P. Berrangé
> > wrote:
> > >
> > > Two previous attempts to fix this due to GCC 9 highlighting
> > > unaligned data access. My attempt:
> > >
>
Daniel P. Berrangé writes:
[...]
> I think that's fundamentally the wrong way around. Most stuff *should*
> be locale dependant, otherwise any interaction with the host OS is
> likely to use incorrect localization. It isn't practical to put a
> uselocale() call around every place that opens a fil
Eric Blake writes:
> On 4/16/19 10:38 AM, Markus Armbruster wrote:
>> Before the from qerror_report() to error_setg(), hints looked like
>
> s/the from/the change from/
>
>> this:
>>
>> qerror_report(QERR_MACRO, ... arguments ...);
>> error_printf_unless_qmp(... hint ...);
>>
>> error_p
Similar to VECTOR SUM ACROSS DOUBLEWORD, however without a loop and
using 128-bit calculations.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 32
2 files changed, 34
Let's keep it simple for now and handle 8/16 bit elements via helpers.
Especially for 8/16, we could come up with some bit tricks.
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 52 +
Let's return the cc value directly via cpu_env. Unfortunately there
isn't a simple way to calculate the value lazily - one would have to
calculate and store e.g. the population count of the mask and the
result so it can be evaluated in a cc helper.
But as VTM only sets the cc, we can assume the va
We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise
existing gvec helpers.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 17 +
2 files changed, 19 insertions(+)
di
Philippe Mathieu-Daudé writes:
> On 4/16/19 11:13 AM, Markus Armbruster wrote:
>> Factored out of pc_system_firmware_init() so the next commit can reuse
>> it in hw/arm/virt.c.
>>
>> Signed-off-by: Markus Armbruster
>> ---
>> hw/block/pflash_cfi01.c | 28
>> hw/i3
Similar to VECTOR SHIFT RIGHT ARITHMETICAL.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4
target/s390x/translate_vx.inc.c | 17 +
target/s390x/vec_int_helper.c | 6 ++
Perform the calculations without a helper. Only 16 bit or 32 bit values
have to be added.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +
2 files changed, 31 insertio
We can reuse the existing 128-bit shift utility function.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4
target/s390x/translate_vx.inc.c | 20
target/s390x/vec_int_helper
Inline expansion courtesy of Richard H.
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +
2 files changed, 31 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index
Fairly easy as only 128-bit handling is required. Simply perform the
subtraction and then subtract the borrow.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 26 ++
2 files ch
Similar to VECTOR COUNT TRAILING ZEROES.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 +++
target/s390x/vec_int_helper.c | 14 +
Only for one special case we can reuse real gvec helpers. Mostly
rely on oom helpers.
One important thing to take care of is always to properly mask of
unused bits from the shift count.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 18 ++
Similar to VECTOR SUM ACROSS DOUBLEWORD.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +
2 files changed, 31 insertions(+)
diff --git a/target/s390x/insn-data.def b/
Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to
s390_vec_shr().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4
target/s390x/translate_vx.inc.c | 17 +
t
Yet another set of variants. Implement it similar to VECTOR MULTIPLY AND
ADD *. At least for one variant we have a gvec helper we can reuse.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 16 +
target/s390x/insn-data.def | 14 +++
Mostly courtesy of Richard H.
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 34 +
2 files changed, 36 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a60d85
Take care of properly taking the modulo of the count. We might later
want to come back and create a variant of VERLL where the base register
is 0, resulting in an immediate.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 4 +++
target/s390
Use the new vector expansion for GVecGen3i.
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 51 +
target/s390x/vec_int_helper.c | 20 +
4 files c
Part of vector enhancements facility 1, but easy to implement.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate.c| 1 +
target/s390x/translate_vx.inc.c | 7 +++
3 files changed, 10 insertions(+)
diff
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index bc8b84e1c2..4983867a44 100644
---
Again, vector enhancements facility 1 material.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-
Reuse a gvec helper.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index b549b76b96..
Similar to VECTOR LOAD COMPLEMENT but unfortunately we don't have a
gvec helper.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 40 +++
Again, part of vector enhancement facility 1. The operation corresponds
to an bitwise equality check.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++
2 files changed, 9 insertions(+)
diff -
To carry out the comparison, we can reuse the existing gvec comparison
function. In case the CC is to be computed, save the result vector
and compute the CC lazily. The result is a vector consisting of all 1's
for elements that matched and 0's for elements that didn't match.
Reviewed-by: Richard H
Quite some variants to handle. At least handle some 32-bit element
variants via gvec expansion (we could also handle 16/32-bit variants
for ODD and EVEN easily via gvec expansion, but let's keep it simple
for now).
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x
We can reuse an existing gvec helper for negating the values.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 17 +
2 files changed, 19 insertions(+)
diff --git a/target/s390x/insn-da
Luckily, we already have gvec helpers for all four cases.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 8
target/s390x/translate_vx.inc.c | 31 +++
2 files changed, 39 insertions(+)
diff --git a/targ
A galois field multiplication in field 2 is like binary multiplication,
however instead of doing ordinary binary additions, xor's are performed.
So no carries are considered.
Implement all variants via helpers. s390_vec_sar() and s390_vec_shr()
will be reused later on.
Reviewed-by: Richard Hender
Time to introduce read_vec_element_i32 and write_vec_element_i32.
Take proper care of properly adding the carry. We can perform both
additions including the carry via tcg_gen_add2_i32().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 +
Easy, as we can reuse existing gvec helpers.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 4
target/s390x/translate_vx.inc.c | 14 ++
2 files changed, 18 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s3
Easy, we can reuse an existing gvec helper.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data
For 8/16, use the 32 bit variant and properly subtract the added
leading zero bits.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 31
128-bit handling courtesy of Richard H.
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 +
target/s390x/translate_vx.inc.c | 94 +
2 files changed, 96 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
ind
Fairly easy to implement, we can make use of the existing CC helpers
cmps64 and cmpu64 - we siply have to sign extend the elements.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 4
target/s390x/translate_vx.inc.c | 20 +++
Handle 32/64-bit elements via gvec expansion and the 8/16 bits via
ool helpers.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/Makefile.objs | 2 +-
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_
Implement it similar to VECTOR COUNT LEADING ZEROS.
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 28
target/s390x/vec_int_helper.c | 14 ++
4 fil
Only slightly ugly, perform two additions. At least it is only supported
for 128 bit elements.
Introduce gen_gvec128_4_i64() similar to gen_gvec128_3_i64().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.in
Introduce two types of fancy new helpers that will be reused a couple of
times
1. gen_gvec_fn_3: Call an existing tcg_gen_gvec_X function with 3
parameters, simplifying parameter passing
2. gen_gvec128_3_i64: Call a function that performs 128 bit calculations
using two 64 bit values per vect
Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
for now.
Signed-off-by: David Hildenbrand
---
tcg/tcg-op-gvec.c | 139 ++
tcg/tcg-op-gvec.h | 24
2 files ch
This is the second part of vector instruction support for s390x. It is
based on the series soon to land upstream:
[PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
Part 1: Vector Support Instructions
Part 2: Vector Integer Instructions
Part 3: Vector String Instructions
Part 4: Vector Floating-P
Similar to VECTOR ADD COMPUTE CARRY, however 128-bit handling only.
Courtesy of Richard H.
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 32
2 files changed, 34 insertions(+)
diff --git a/target/s
Similar to VECTOR AVERAGE but without sign extension.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 48 +
target/s390x/vec_in
On 4/16/19 7:47 AM, Eric Blake wrote:
> On 4/16/19 3:31 AM, Richard Henderson wrote:
>> If a TB generates too much code, try again with fewer insns.
>>
>> Fixes: https://bugs.launchpad.net/bugs/1824853
>> Signed-off-by: Richard Henderson
>> ---
>> accel/tcg/translate-all.c | 39 ++
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