On 28/02/2019 08.14, Gerd Hoffmann wrote:
> On Thu, Feb 28, 2019 at 08:01:53AM +0100, Thomas Huth wrote:
>> On 28/02/2019 06.00, David Gibson wrote:
>>> On Thu, Feb 28, 2019 at 03:35:03PM +1100, Alexey Kardashevskiy wrote:
The configure script checks multiple times whether it works in a git
>>
Hi Igor, Shameer,
On 2/27/19 6:51 PM, Igor Mammedov wrote:
> On Wed, 27 Feb 2019 10:41:45 +
> Shameerali Kolothum Thodi wrote:
>
>> Hi Eric,
>>
>>> -Original Message-
>>> From: Auger Eric [mailto:eric.au...@redhat.com]
>>> Sent: 27 February 2019 10:27
>>> To: Igor Mammedov
>>> Cc: p
On 27.02.19 16:39, Richard Henderson wrote:
> On 2/26/19 3:38 AM, David Hildenbrand wrote:
>> +static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
>> +{
>> +load_vec_element(s, TMP_VREG_0, 0, o->addr1, MO_64);
>> +gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
>> +load_vec_elemen
Just wanted to share a small update on the situation after updating QEMU to the
new Alpine package patched with Natanael's patch.
So far so good, moreover I switched a few other guests from SATA to VirtIO SCSI
and after two days no issues.
Unless I find any problem I will report back with an upda
On 26.02.19 12:38, David Hildenbrand wrote:
> This is the first part of vector instruction support for s390x. Parts
> will be sent and reviewed piece by piece.
>
> Part 1: Vector Support Instructions
> Part 2: Vector Integer Instructions
> Part 3: Vector String Instructions
> Part 4: Vector Floati
On 27.02.19 22:15, David Hildenbrand wrote:
> As want to make use of vectors in constraints of inline asm statements,
> use -march=z13. To make it compile, use a reasonable optimization level
> (-O2).
>
> Add some infrastructure for checking if SIGILL will be properly triggered.
> Take care of man
On Thu, Feb 28, 2019 at 08:01:53AM +0100, Thomas Huth wrote:
> On 28/02/2019 06.00, David Gibson wrote:
> > On Thu, Feb 28, 2019 at 03:35:03PM +1100, Alexey Kardashevskiy wrote:
> >> The configure script checks multiple times whether it works in a git
> >> repository and it does this by "test -e "$
On 28.02.19 01:17, Richard Henderson wrote:
> On 2/27/19 11:37 AM, David Hildenbrand wrote:
>> #define CHECK_SIGILL(STATEMENT) \
>> do { \
>> if (signal(SIGILL, sig_sigill) == SIG_ERR) { \
>> check("SIGILL not registered", fal
On 28.02.19 01:24, Richard Henderson wrote:
> On 2/27/19 1:40 PM, Alex Bennée wrote:
>> And crucially have nice regular sized instructions. Is that not an option?
>
> s390 insns are {2,4,6} bytes. I don't think that there's an easy way to pick
> out the hw status codes that would give the ilen of
On 28/02/2019 06.00, David Gibson wrote:
> On Thu, Feb 28, 2019 at 03:35:03PM +1100, Alexey Kardashevskiy wrote:
>> The configure script checks multiple times whether it works in a git
>> repository and it does this by "test -e "${source_path}/.git" in 4 cases
>> but in one case where it tries to e
On Thu, Feb 28, 2019 at 06:01:30AM +, Mark Cave-Ayland wrote:
> On 28/02/2019 05:49, Gerd Hoffmann wrote:
>
> > Hi,
> >
> >> Right, at the moment all the MacOS driver does is parse the resolution
> >> list from the
> >> EDID and add them to the dropdown list - it doesn't support the xres a
On Wed, Feb 27, 2019 at 04:49:00PM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Currently we cleanup the migration object as we exit main after the
> main_loop finishes; however if there's a migration running things
> get messy and we can end up with the migrati
On 28/02/2019 14:31, David Gibson wrote:
> On Wed, Feb 27, 2019 at 07:51:49PM +1100, Alexey Kardashevskiy wrote:
>> NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
>> space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver
>> implements special regions f
On Wed, Feb 27, 2019 at 01:38:38PM +, Stefan Hajnoczi wrote:
> On Fri, Feb 22, 2019 at 02:57:24PM +0800, Peter Xu wrote:
> > On Fri, Feb 22, 2019 at 07:37:02AM +0100, Marc-André Lureau wrote:
> > > Hi
> > >
> > > On Fri, Feb 22, 2019 at 4:14 AM Peter Xu wrote:
> > > >
> > > > We were pushing
On 28/02/2019 05:49, Gerd Hoffmann wrote:
> Hi,
>
>> Right, at the moment all the MacOS driver does is parse the resolution list
>> from the
>> EDID and add them to the dropdown list - it doesn't support the xres and
>> yres properties.
>
>> The main reason for this that OpenBIOS currently m
Hi,
> Right, at the moment all the MacOS driver does is parse the resolution list
> from the
> EDID and add them to the dropdown list - it doesn't support the xres and yres
> properties.
> The main reason for this that OpenBIOS currently makes use of the -g XxYxD
> parameter
> to set up the
This is interesting for bisection, where an output file is plumbed,
but does not yet have patterns.
Signed-off-by: Richard Henderson
---
One more small fix that should have gone with the v2 patchset.
---
scripts/decodetree.py | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-
On 28/02/2019 14:49, David Gibson wrote:
> On Thu, Feb 28, 2019 at 10:59:56AM +1100, Alexey Kardashevskiy wrote:
>>
>>
>> On 28/02/2019 01:33, Greg Kurz wrote:
>>> On Wed, 27 Feb 2019 19:51:47 +1100
>>> Alexey Kardashevskiy wrote:
>>>
On sPAPR vfio_listener_region_add() is called in 2 situ
Like --decode, but do not drop 'static' qualifier.
Signed-off-by: Richard Henderson
---
scripts/decodetree.py | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 4596a9da02..68979b73a0 100755
--- a/scripts/decodetree.py
+++
Changes since v1:
* Move documentation to docs/devel/; fix some typos;
add a description of when you might use argument sets.
* Include test cases for pattern groups.
* Add --static-decode.
r~
Bastian Koppelmann (1):
test/decode: Add tests for PatternGroups
Philippe Mathieu-Daudé (
Signed-off-by: Richard Henderson
---
docs/devel/decodetree.rst | 58 +++
scripts/decodetree.py | 144 +++---
2 files changed, 191 insertions(+), 11 deletions(-)
diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
index 62cb7f687c..4
One great big block comment isn't the best way to document
the syntax of a language.
Signed-off-by: Richard Henderson
---
MAINTAINERS | 1 +
docs/devel/decodetree.rst | 156 ++
scripts/decodetree.py | 134 +---
3
As a consequence, the 'return false' gets pushed up one level.
This will allow us to perform some other action when the
translator returns failure.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
scrip
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20181110211313.6922-2-f4...@amsat.org>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7be8c578ea..34364a77ce 100644
--- a/MAINTA
Cc: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
docs/devel/decodetree.rst | 7 +++
1 file changed, 7 insertions(+)
diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
index d9be30b2db..62cb7f687c 100644
--- a/docs/devel/decodetree.rst
+++ b/docs/devel/decodetree.r
From: Philippe Mathieu-Daudé
Reproduced with "scripts/decodetree.py /dev/null".
Reviewed-by: Bastian Koppelmann
Reviewed-by: Eduardo Habkost
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
scripts/decodetree.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Bastian Koppelmann
This adds one test that supposed to succeed to test deep nesting
of pattern groups which is rarely exercised by targets using decode
tree. The remaining tests exercise various fail conditions.
Signed-off-by: Bastian Koppelmann
Message-Id: <20190227120217.20794-1-kbast..
On Fri, Feb 22, 2019 at 02:13:21PM +0100, Cédric Le Goater wrote:
> The interrupt mode is chosen by the CAS negotiation process and
> activated after a reset to take into account the required changes in
> the machine. This brings new constraints on how the associated KVM IRQ
> device is initialized
On 2/27/19 8:01 PM, David Gibson wrote:
> On Wed, Feb 27, 2019 at 04:47:30PM -0800, Richard Henderson wrote:
>> On 2/24/19 3:31 PM, David Gibson wrote:
>>> I have access to POWER8 and POWER9 machines, but I haven't worked with
>>> RISU before. If you can give me a straightforward recipe I can try
On 26/02/2019 22:25, Andrew Randrianasulu wrote:
(adding qemu-ppc, Richard and David - please make sure you add the relevant
maintainer on bug reports, as otherwise due to the high volume of mails to the
list
it's very easy to miss things)
> Hello.
>
> I bisected this problem with fonts (and mu
On 27/02/2019 05:27, Gerd Hoffmann wrote:
> On Tue, Feb 26, 2019 at 04:11:06PM -0500, G 3 wrote:
>> When I use edid=on, I do see a lot of extra resolutions available in Mac OS
>> 9 and Mac OS X, just not the resolution I want to use. Is there some kind
>> of rule like the resolution value has to b
On Thu, Feb 28, 2019 at 03:35:03PM +1100, Alexey Kardashevskiy wrote:
> The configure script checks multiple times whether it works in a git
> repository and it does this by "test -e "${source_path}/.git" in 4 cases
> but in one case where it tries to enable werror "-d" is used there which
> fails
The configure script checks multiple times whether it works in a git
repository and it does this by "test -e "${source_path}/.git" in 4 cases
but in one case where it tries to enable werror "-d" is used there which
fails on git worktrees as .git is a file then and not a directory.
This changes the
On Wed, Feb 27, 2019 at 04:47:30PM -0800, Richard Henderson wrote:
> On 2/24/19 3:31 PM, David Gibson wrote:
> > I have access to POWER8 and POWER9 machines, but I haven't worked with
> > RISU before. If you can give me a straightforward recipe I can try
> > running the tests.
>
> From
>
> htt
On 2/27/2019 4:05 PM, Mark Kanda wrote:
Hi all,
I noticed nested SVM is enabled only in pc-i440fx-2.1 (default is
disabled); this was added when 2.1 was the latest:
75d373ef97 ("target-i386: Disable SVM by default in KVM mode")
However, this change was not carried forward to newer machi
On Wed, Feb 27, 2019 at 07:51:49PM +1100, Alexey Kardashevskiy wrote:
> NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
> space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver
> implements special regions for such GPUs and emulates an NVLink bridge.
> NVL
On Thu, Feb 28, 2019 at 10:16:00AM +1100, Suraj Jitindar Singh wrote:
> On Wed, 2019-02-27 at 17:16 +1100, David Gibson wrote:
> > On Wed, Feb 27, 2019 at 03:30:05PM +1100, Suraj Jitindar Singh wrote:
> > > Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
> > > availability of th
On Wed, Feb 27, 2019 at 07:51:45PM +1100, Alexey Kardashevskiy wrote:
> The current code assumes that we can address more bits on a PCI bus
> for DMA than we really can but there is no way knowing the actual limit.
>
> This makes a better guess for the number of levels and if the kernel
> fails to
On Thu, Feb 28, 2019 at 10:59:56AM +1100, Alexey Kardashevskiy wrote:
>
>
> On 28/02/2019 01:33, Greg Kurz wrote:
> > On Wed, 27 Feb 2019 19:51:47 +1100
> > Alexey Kardashevskiy wrote:
> >
> >> On sPAPR vfio_listener_region_add() is called in 2 situations:
> >> 1. a new listener is registered f
On Wed, Feb 27, 2019 at 07:51:46PM +1100, Alexey Kardashevskiy wrote:
> The "systempagesize" name suggests that it is the host system page size
> while it is the smallest page size of memory backing the guest RAM so
> let's rename it to stop confusion. This should cause no behavioral change.
>
> S
On Mon, Feb 25, 2019 at 05:39:06PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 15/02/2019 16:21, David Gibson wrote:
> > On Fri, Feb 15, 2019 at 03:34:52PM +1100, Alexey Kardashevskiy wrote:
> >>
> >>
> >> On 15/02/2019 14:54, David Gibson wrote:
> >>> On Fri, Feb 15, 2019 at 02:32:14PM +1100, Al
On Wed, Feb 27, 2019 at 07:51:44PM +1100, Alexey Kardashevskiy wrote:
> sPAPR code will use it too so move it from VFIO to the common code.
>
> Signed-off-by: Alexey Kardashevskiy
> Reviewed-by: David Gibson
> Reviewed-by: Alistair Francis
Not technically my purview, but since it's to enable t
On 2019/2/28 上午1:39, Nikhil Agarwal wrote:
Hi Stefan,
Thanks for directing question to correct people, yes your understanding is
correct.
I want virtio-net control virtqueue to be handled by vhost-user-net device
based backend for vdpa use case where control message would do some
configura
Changes since v2:
* Rebase on master, cherry-picking one required patch from
the ARMv8.5-MemTag patch set.
* Use the same form of TB exit for SB as for ISB.
* Rename all the bits related to PredInv.
* Fix registration for PredInv cache flush special regs,
and spell out why in a comm
Minimize the number of places that will need updating when
the virtual host extensions are added.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 26 --
target/arm/helper.c | 8 ++--
2 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/a
This is named "Execution and Data prediction restriction instructions"
within the ARMv8.5 manual, and given the name "PredRes" by binutils.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 13 ++-
target/arm/cpu.c| 1 +
target/arm/cpu64.c | 2 ++
target/arm/helper.c | 55
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
linux-user/elfload.c | 1 +
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 2 ++
target/arm/translate-a64.c | 14 ++
target/arm/translate.c | 22 ++
6 file
ping
From: no-re...@patchew.org
Sent: Thursday, January 31, 2019 9:53
To: mhi...@scalecomputing.com
Cc: f...@euphon.net; qemu-devel@nongnu.org; mhi...@scalecomputing.com;
mdr...@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [PATCH v3] QGA: Fix guest-get-fsinfo PCI
addresscollection in Windows
On 2/26/19 10:31 AM, Peter Maydell wrote:
> On Wed, 20 Feb 2019 at 23:50, Richard Henderson
> wrote:
>>
>> Signed-off-by: Richard Henderson
>
>
>> @@ -9192,6 +9192,17 @@ static void disas_arm_insn(DisasContext *s, unsigned
>> int insn)
>> */
>> gen_goto_tb(s,
On Wed, Feb 27, 2019 at 07:04:02PM +0100, Igor Mammedov wrote:
>On Mon, 25 Feb 2019 09:15:34 +0800
>Wei Yang wrote:
>
>> On Mon, Feb 25, 2019 at 09:07:08AM +0800, Wei Yang wrote:
>> >Currently we do device realization like below:
>> >
>> > hotplug_handler_pre_plug()
>> > dc->realize()
>> > h
On 2/27/19 9:40 AM, Mateja Marjanovic wrote:
> +void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
> + uint32_t ws, uint32_t wt)
> +{
> +wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
> +wr_t *pws = &(env->active_fpu.fpr[ws].wr);
> +wr_t *pwt = &(e
On Wed, Feb 27, 2019 at 08:51:11AM -0500, Michael S. Tsirkin wrote:
>On Wed, Feb 27, 2019 at 01:33:19PM +0800, Wei Yang wrote:
>> On Tue, Feb 26, 2019 at 11:10:06AM -0500, Michael S. Tsirkin wrote:
>> >On Tue, Feb 26, 2019 at 03:31:59PM +0800, Wei Yang wrote:
>> >> Leverage __ATTR_RO_MODE to define
On Wed, Feb 27, 2019 at 12:04:49PM -0300, Murilo Opsfelder Araujo wrote:
> Hi, David.
>
> On Wed, Feb 27, 2019 at 10:19:20AM +1100, David Gibson wrote:
> > On Tue, Feb 26, 2019 at 04:11:40PM -0300, Murilo Opsfelder Araujo wrote:
> > > On Tue, Feb 26, 2019 at 02:08:30PM -0300, Murilo Opsfelder Arau
On 2/24/19 3:31 PM, David Gibson wrote:
> I have access to POWER8 and POWER9 machines, but I haven't worked with
> RISU before. If you can give me a straightforward recipe I can try
> running the tests.
From
https://git.linaro.org/people/peter.maydell/risu.git
First you need to generate the t
On Wed, Feb 27, 2019 at 06:27:49PM +0100, Igor Mammedov wrote:
>On Wed, 27 Feb 2019 13:59:20 +
>Wei Yang wrote:
>
>> On Wed, Feb 27, 2019 at 02:12:42PM +0100, Igor Mammedov wrote:
>> >On Mon, 25 Feb 2019 12:47:14 +
>> >Wei Yang wrote:
>> >
>> >> >> To me, this is a general rule for PCDI
On 2/27/19 1:40 PM, Alex Bennée wrote:
> And crucially have nice regular sized instructions. Is that not an option?
s390 insns are {2,4,6} bytes. I don't think that there's an easy way to pick
out the hw status codes that would give the ilen of the faulting insn.
r~
On 2/27/19 3:14 AM, David Hildenbrand wrote:
> Especially for inline asm with immediates;
>
> static inline void some_instr(uint8_t imm)
> {
> asm volatile("...", :: "i" (imm));
> }
>
> static void test()
> {
> some_instr(1);
> }
FWIW, __attribute__((always_inline)) should work even with
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Combine all variant in a single handler. As source and destination
> have different element sizes, we can't use gvec expansion. Expand
> manually. Also watch out for overlapping source and destination and
> use a temporary register in that case.
>
> S
On 2/27/19 11:37 AM, David Hildenbrand wrote:
> #define CHECK_SIGILL(STATEMENT) \
> do { \
> if (signal(SIGILL, sig_sigill) == SIG_ERR) { \
> check("SIGILL not registered", false); \
> }
> -Original Message-
> From: Kang, Luwei
> Sent: Wednesday, January 30, 2019 7:53 AM
> To: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; ehabk...@redhat.com
> Cc: qemu-devel@nongnu.org; Kang, Luwei
> Subject: [PATCH V2] i386: extended the cpuid_l
On 28/02/2019 01:33, Greg Kurz wrote:
> On Wed, 27 Feb 2019 19:51:47 +1100
> Alexey Kardashevskiy wrote:
>
>> On sPAPR vfio_listener_region_add() is called in 2 situations:
>> 1. a new listener is registered from vfio_connect_container();
>> 2. a new IOMMU Memory Region is added from rtas_ibm_
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Very similar to VECTOR LOAD WITH LENGTH, just the opposite direction.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/helper.h | 1 +
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 13
On 2/25/19 11:21 AM, Vladimir Sementsov-Ogievskiy wrote:
> 23.02.2019 3:22, John Snow wrote:
>> Set the inconsistent bit on load instead of rejecting such bitmaps.
>> There is no way to un-set it; the only option is to delete it.
>>
>> Obvervations:
>> - bitmap loading does not need to update th
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Similar to VECTOR LOAD MULTIPLE, just the opposite direction.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 25 +
> 2 files changed, 27 insertions(+)
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> As we only store one element, there is nothing to consider regarding
> exceptions.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 5 +
> target/s390x/translate_vx.inc.c | 18 ++
> 2 files changed,
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> +static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
> +{
> +/*
> + * FIXME: On exceptions we must not modify any memory.
> + */
> +store_vec_element(s, get_field(s->fields, v1), 0, o->addr1, MO_64);
> +gen_addi_and_wrap_i64(s
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Load both elements signed and store them into the two 64 bit elements.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 33 +
> 2 files changed,
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> +tcg_gen_not_vec(vece, t, c);
> +tcg_gen_and_vec(vece, t, t, b);
tcg_gen_andc_vec(t, b, c);
> +tcg_gen_not_i64(t, c);
> +tcg_gen_and_i64(t, b, t);
Likewise.
r~
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Similar to VECTOR GATHER ELEMENT, but the other direction.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 3 +++
> target/s390x/translate_vx.inc.c | 22 ++
> 2 files changed, 25 insertions(+)
Rev
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> +tmp = tcg_temp_new_i64();
> +tcg_gen_movi_i64(tmp, data);
> +gen_gvec_dup_i64(es, get_field(s->fields, v1), tmp);
> +tcg_temp_free_i64(tmp);
> +return DISAS_NEXT;
Reuse the dupi8, dupi16, ... switch from one of the other patches u
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Load the element and replicate it using gvec_dup.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 18 ++
> 2 files changed, 20 insertions(+)
Reviewed-by: Rich
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Read the whole input before modifying the destination vector.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 16
> 2 files changed, 18 insertions(+)
Reviewe
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Load the element and replicate it using gvec_dup.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 18 ++
> 2 files changed, 20 insertions(+)
Reviewed-by: Rich
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> Take care of overlying inputs and outputs by using a temporary vector.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/helper.h | 1 +
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 12 +++
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> We'll implement both via gvec ool helpers. As these can't return
> values, we'll return the CC via env->cc_op. Generate different C
> functions for the different cases using makros.
>
> In the future we might want to do a translation like VECTOR PACK
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> We'll implement both via gvec ool helpers. As these can't return
> values, we'll return the CC via env->cc_op. Generate different C
> functions for the different cases using makros.
>
> In the future we might want to do a translation like VECTOR PACK
On Wed, 2019-02-27 at 17:16 +1100, David Gibson wrote:
> On Wed, Feb 27, 2019 at 03:30:05PM +1100, Suraj Jitindar Singh wrote:
> > Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
> > availability of the large decrementer for a guest.
> >
> > Signed-off-by: Suraj Jitindar Singh
On 2/27/19 4:02 AM, Bastian Koppelmann wrote:
> this adds one test that supposed to succeed to test deep nesting
> of pattern groups which is rarely exercised by targets using decode
> tree. The remaining tests exercise various fail conditions.
>
> Signed-off-by: Bastian Koppelmann
> ---
> These
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> We can reuse the helper introduced along with VECTOR LOAD TO BLOCK
> BOUNDARY. We just have to take care of converting the highest index into
> a length.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> We cannot use gvex expansion as the element size of source and
> destination differs. So expand manually. Luckily, VECTOR PACK does not
> care about saturation or setting the CC, so it can be implemented
> without a helper. We have to watch out for ove
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> Fairly easy, just load from to gprs into a single vector.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 7 +++
> 2 files changed, 9 insertions(+)
Reviewed-by: Richard He
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> +for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(es); dst_idx++) {
> +src_idx = dst_idx / 2;
> +if (!high) {
> +src_idx += NUM_VEC_ELEMENTS(es) / 2;
> +}
> +if (dst_idx % 2 == 0) {
> +read_vec_el
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> Very similar to VECTOR LOAD GR FROM VR ELEMENT, just the opposite
> direction.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 33 +
> 2 files
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> +zero_vec(TMP_VREG_0);
> +load_vec_element(s, TMP_VREG_0, enr, o->addr1, es);
> +gen_gvec_mov(get_field(s->fields, v1), TMP_VREG_0);
load into TCGv_i64, zero real dest, store into real dest.
r~
On 2/26/19 3:39 AM, David Hildenbrand wrote:
> We cannot use gvec expansion as source and destination elements are
> have different element numbers. So we'll expand using a fancy loop.
> Also, we have to take care of overlapping source and target registers and
> use a temporary register in case the
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> +void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t bytes)
> +{
> +S390Vector tmp = {};
> +int i;
> +
> +bytes = MIN(bytes, 16);
> +for (i = 0; i < bytes; i++) {
> +uint8_t byte = cpu_ldub_data_ra(env, addr,
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> Take care of properly sign-extending the immediate.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 5 +
> target/s390x/translate_vx.inc.c | 17 +
> 2 files changed, 22 insertions(+)
Reviewed-by:
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> To avoid an helper, we have to do the actual calculation of the element
> address (offset in cpu_env + cpu_env) manually. Factor that out into
> get_vec_element_ptr_i64(). The same logic will be reused for "VECTOR
> LOAD VR ELEMENT FROM GR".
>
> Signe
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> Also fairly easy to implement. One issue we have is that exceptions will
> result in some vectors already being modified. At least handle it
> consistently per vector by using a temporary vector. Good enough for
> now, add a FIXME.
>
> Signed-off-by:
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> We can use tcg_gen_gvec_dup_i64() to carry out the duplication.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 17 +
> 2 files changed, 19 insertions(+)
Revi
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> Fairly easy, load with desired size and store it into the right element.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/insn-data.def | 5 +
> target/s390x/translate_vx.inc.c | 18 ++
> 2 files changed, 23 insert
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> +static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
> +{
> +load_vec_element(s, TMP_VREG_0, 0, o->addr1, MO_64);
> +gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
> +load_vec_element(s, TMP_VREG_0, 1, o->addr1, MO_64);
> +gen_gv
On 2/26/19 1:16 PM, David Hildenbrand wrote:
>> +tmp = tcg_temp_new_i64();
>> +tcg_gen_movi_i64(tmp, mask);
>> +gen_gvec_dup_i64(es, get_field(s->fields, v1), tmp);
> Richard, shall I better convert this into
>
> switch (es) {
> case MO_8:
> tcg_gen_gvec_dup8i(..., 16, 16, mask)
Hi all,
I noticed nested SVM is enabled only in pc-i440fx-2.1 (default is
disabled); this was added when 2.1 was the latest:
75d373ef97 ("target-i386: Disable SVM by default in KVM mode")
However, this change was not carried forward to newer machine types. Is
this an oversight? Is th
Patchew URL:
https://patchew.org/QEMU/20190222141024.22217-1-kbast...@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190222141024.22217-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v8 00/34
Patchew URL:
https://patchew.org/QEMU/20190222141024.22217-1-kbast...@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190222141024.22217-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v8 00/34
David Hildenbrand writes:
> On 27.02.19 21:19, Alex Bennée wrote:
>>
>> David Hildenbrand writes:
>>
>>> On 27.02.19 12:14, David Hildenbrand wrote:
We want to make use of vectors, so use -march=z13. To make it compile,
use a reasonable optimization level (-O2), which seems to work j
Patchew URL:
https://patchew.org/QEMU/20190222141024.22217-1-kbast...@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190222141024.22217-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v8 00/34
Patchew URL:
https://patchew.org/QEMU/20190222141024.22217-1-kbast...@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190222141024.22217-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v8 00/34
Patchew URL:
https://patchew.org/QEMU/20190222141024.22217-1-kbast...@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190222141024.22217-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v8 00/34
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