When there is a Backup Block Job running and shutdown command is sent to
a guest, the guest crushes due to assert(!bs->walking_aio_notifiers).
Call stack:
0 __GI_raise
1 __GI_abort
2 __assert_fail_base
3 __GI___assert_fail
4 bdrv_detach_aio_context (bs=0x55f54d65c000) <<<
5 bdrv_detach
On Wed, Jan 23, 2019 at 03:40:54PM +0100, Thomas Huth wrote:
> It's either "GNU *Library* General Public version 2" or "GNU Lesser
> General Public version *2.1*", but there was no "version 2.0" of the
> "Lesser" library. So assume that version 2.1 is meant here.
> Additionally, suggest that the us
INTERRUPT special register may be changed both by the core (by writing
to INTSET and INTCLEAR registers) and by external events (by triggering
and clearing HW IRQs). In MTTCG this state must be protected from
concurrent access, otherwise interrupts may be lost or spurious
interrupts may be detected
On Wed, Jan 23, 2019 at 09:16:07PM +0100, Zoltán Kővágó wrote:
> On 2019-01-17 10:22, Gerd Hoffmann wrote:
> > On Thu, Jan 17, 2019 at 12:36:48AM +0100, Kővágó, Zoltán wrote:
> >> Remove glob_audio_state from functions, where possible without breaking
> >> the API. This means that most static func
On 23/01/2019 04:01, Fabiano Rosas wrote:
> This allows reading and writing of SPRs via GDB:
>
> (gdb) p/x $srr1
> $1 = 0x82803033
>
> (gdb) p/x $pvr
> $2 = 0x4b0201
> (gdb) set $pvr=0x4b
> (gdb) p/x $pvr
> $3 = 0x4b
>
> They can also be shown as a group:
> (gdb) info reg spr
On 24/01/19 03:00, Yang Zhong wrote:
> On Thu, Jan 24, 2019 at 02:09:25AM +0100, Paolo Bonzini wrote:
>> On 23/01/19 07:55, Yang Zhong wrote:
>>> This Kconfig implementation is rebased from Paolo's branch
>>> https://github.com/bonzini/qemu/commits/kconfig
>>>
>>> I rebased most of patches except n
On 24/01/19 03:38, BALATON Zoltan wrote:
>>
>> I started looking at this, and found two bugs in current code
>> (unreachable devices that shouldn't be there - SERIAL_ISA for ARM,
>> ACPI_NVDIMM for MIPS). There are a few issues in that the script is not
>
> The ACPI_NVDIMM for MIPS is pulled in b
Rename pc_get_hotpug_handler to pc_get_hotplug_handler.
No functional change.
Signed-off-by: Wei Yang
---
hw/i386/pc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 115bc2825c..5317e08f60 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@
On 23/01/2019 04:01, Fabiano Rosas wrote:
> These will be used to let GDB know about PPC's Special Purpose
> Registers (SPR).
>
> They take an index based on the order the registers appear in the XML
> file sent by QEMU to GDB. This index does not match the actual
> location of the registers in
On Wed, Jan 23, 2019 at 05:35:03PM +0100, Juan Quintela wrote:
> bal...@linux.vnet.ibm.com wrote:
> > From: Balamuruhan S
> >
> > currently we calculate expected_downtime by time taken to transfer
> > remaining ram, but during the time we had transferred remaining ram
> > few pages of ram might be
Finally fixed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=a442fe2f2b2f20e7be0
** Changed in: qemu
Status: New => Fix Committed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1392468
+-- On Fri, 11 Jan 2019, Paolo Bonzini wrote --+
| diff --git a/hw/scsi/scsi-generic.c b/hw/scsi/scsi-generic.c
| index 7237b4162e..42700e8897 100644
| --- a/hw/scsi/scsi-generic.c
| +++ b/hw/scsi/scsi-generic.c
| @@ -182,7 +182,7 @@ static void scsi_handle_inquiry_reply(SCSIGenericReq *r,
SCSIDev
On 23/01/2019 04:01, Fabiano Rosas wrote:
> A following patch will add support for handling the Special Purpose
> Registers (SPR) in GDB via gdbstub. For that purpose, GDB needs to be
> provided with an XML description of the registers (see gdb-xml
> directory).
>
> This patch adds the code tha
On 2019-01-24 07:38, Gerd Hoffmann wrote:
[...]
> I'm not going to join the sndio vs. pulse discussion.
>
> But from a maintenance point of view it sucks big time to have a bunch
> of ways to play sound, and everybody uses a different one so you have to
> maintain a backend for each of those metho
Hi,
> > https://xkcd.com/927/
>
> There is a different context on BSD than on Linux. We can choose one
> solution and switch to it literally all the software keeping everything
> in a single ports tree.
>
> This is what happened on OpenBSD.
>
> The result is that almost everything uses sndio,
On 2019-01-23 at 10:04:01 -0500, Michael S. Tsirkin wrote:
> On Wed, Jan 23, 2019 at 10:59:45AM +0800, Zhang, Yi wrote:
> > From: Zhang Yi
> >
> > When a file supporting DAX is used as vNVDIMM backend, mmap it with
> > MAP_SYNC flag in addition which can ensure file system metadata
> > synced in
On 2019/1/24 上午3:53, Dr. David Alan Gilbert wrote:
* Jason Wang (jasow...@redhat.com) wrote:
On 2019/1/22 上午2:56, Peter Maydell wrote:
On Thu, 17 Jan 2019 at 09:46, Jason Wang wrote:
On 2019/1/15 上午12:33, Zhang Chen wrote:
On Sat, Jan 12, 2019 at 12:15 AM Dr. David Alan Gilbert
mailto:dgil
Signed-off-by: Doug Gale
---
configure | 4 +-
gdb-xml/i386-32bit-core.xml | 65 ---
gdb-xml/i386-32bit-sse.xml | 52 -
gdb-xml/i386-32bit.xml | 184 ++-
gdb-xml/i386-64bit-core.xml | 73 -
gdb-xml/i386-64bit-sse
INTERRUPT special register may be changed both by the core (by writing
to INTSET and INTCLEAR registers) and by external events (by triggering
and clearing HW IRQs). In MTTCG this state must be protected from
concurrent access, otherwise interrupts may be lost or spurious
interrupts may be detected
On Mon, 14 Jan 2019 04:40:06 PST (-0800), Peter Maydell wrote:
On Fri, 11 Jan 2019 at 18:06, Palmer Dabbelt wrote:
The following changes since commit 147923b1a901a0370f83a0f4c58ec1baffef22f0:
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190108-pull-request'
into staging (2019-01
On 2019-01-23 at 12:50:50 -0200, Eduardo Habkost wrote:
> On Wed, Jan 23, 2019 at 11:00:02AM +0800, Zhang, Yi wrote:
> > From: Zhang Yi
> >
> > Signed-off-by: Zhang Yi
> > ---
> > docs/nvdimm.txt | 29 -
> > qemu-options.hx | 4
> > 2 files changed, 32 insertio
On 23/01/2019 19:24, David Hildenbrand wrote:
> While looking at the s390x implementation, looks like spapr has a
> similar BUG when building the topology.
>
> The primary bus number corresponds always to the bus number of the
> bus the bridge is attached to.
>
> Right now, if we have two brid
On Thu, 24 Jan 2019, Paolo Bonzini wrote:
On 23/01/19 07:55, Yang Zhong wrote:
This Kconfig implementation is rebased from Paolo's branch
https://github.com/bonzini/qemu/commits/kconfig
I rebased most of patches except non-x86 ARCHs dependency definitions
this time.
https://github.com/yangzhon/
On Wed, 23 Jan 2019, John Snow wrote:
On 1/22/19 7:39 AM, BALATON Zoltan wrote:
The device was initialised in ISA compatibility mode and native PCI
IDE mode was not implemented but no clents are known to need ISA mode
but to the contrary, most clients that want to switch to and use
device in nat
When performing SCSI reservation inside the guest, 'sys_rawio' selinux alarm is
triggered, shown as below:
"type=AVC msg=audit(1548231520.416:8086): avc: denied { sys_rawio } for
pid=30357 comm="worker" capability=17
scontext=system_u:system_r:svirt_t:s0:c72,c348
tcontext=system_u:system_r:svir
https://cgit.freedesktop.org/mesa/mesa/commit/include/EGL/eglplatform.h?id=f744c6c1e28fe363474550b94af42a8b7fc1c755
Unfortunately that issue has only been fixed very recently.
There is a possibility of us updating from Mesa 17.3.9 to 18.3.x which
would bring in this header fix, but I don't know
On Thu, Jan 24, 2019 at 02:09:25AM +0100, Paolo Bonzini wrote:
> On 23/01/19 07:55, Yang Zhong wrote:
> > This Kconfig implementation is rebased from Paolo's branch
> > https://github.com/bonzini/qemu/commits/kconfig
> >
> > I rebased most of patches except non-x86 ARCHs dependency definitions
> >
The patch pasted in previous mail lost some indentations and spaces.
Sorry.
From 7921a69f106233ebc0ff9bdc29d7c6182160fc6f Mon Sep 17 00:00:00 2001
From: Chen Zhang
Date: Thu, 24 Jan 2019 09:16:23 +0800
Subject: [PATCH] DMABuf: Blend cursor buf within a scaled viewport
Signed-off-by: Chen Zhang
On Tue, 15 Jan 2019 13:09:28 PST (-0800), alistai...@gmail.com wrote:
On Mon, Jan 14, 2019 at 2:58 AM Philippe Mathieu-Daudé
wrote:
Hi Alistair,
On 1/12/19 2:17 AM, Alistair Francis wrote:
> Cast the kernel start address to the target bit length.
>
> This ensures that we calculate the initrd
On 24.01.2019 02:36, Philippe Mathieu-Daudé wrote:
> OpenBSD display various warnings about the use of an undefined __HAIKU__:
>
Please report it to OpenBSD and/or 3rd party libs. It's just a warning
in public headers, not an issue on the qemu side.
> CC ui/egl-context.o
> In file inc
On 1/23/19 10:33 AM, Daniel P. Berrangé wrote:
> On Tue, Jan 22, 2019 at 07:20:35PM +, Peter Maydell wrote:
>> On Tue, 22 Jan 2019 at 19:05, Philippe Mathieu-Daudé
>> wrote:
>>>
>>> Currently if we try to build QEMU on OpenBSD with SDL disabled, we get:
>>>
>>> $ ./configure --cc=x86_64-unk
OpenBSD display various warnings about the use of an undefined __HAIKU__:
CC ui/egl-context.o
In file included from /usr/X11R6/include/epoxy/egl_generated.h:10:0,
from /usr/X11R6/include/epoxy/egl.h:46,
from include/ui/egl-helpers.h:5,
When a gtk-egl window (for gvt-g DMABuf) was zoomed, the cursor plane buffer
did not zoom covariantly, resulting in a mismatched cursor size. In this patch,
`egl_texture_blend()` is augmented with two extra parameters to convey the size
for a scaled viewport, as in `egl_texture_blend2()`.
Sig
Move the complexity of milkymist_tmu2_create() into the
source file. Doing so we avoid to include the X11/OpenGL
headers in all LM32 devices, and we also avoid the duplicate
declaration of glx_fbconfig_attr[] (it is already declared
in hw/display/milkymist-tmu2.c).
Since TYPE_MILKYMIST_TMU2 is now
Currently if we try to build QEMU on OpenBSD with SDL disabled, we get:
$ ./configure --cc=x86_64-unknown-openbsd6.1-gcc-4.9.4 --python=python2.7
--disable-sdl
ERROR: sdl not found or disabled, can not use sdl audio driver
Since SDL is not a requirement for OpenBSD, let it be optional.
If i
The TMU device requires both X11 and OpenGL.
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/lm32-softmmu.mak | 2 +-
hw/display/Makefile.objs | 4 ++--
hw/lm32/milkymist-hw.h | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/default-configs/lm3
v1 was too simple to work, so here we go again.
I hit a problem with the Milkymist TMU device when disabling SDL,
so I fixed it and added another patch in this series which clean
a bit the device, but is not required for this series.
The important patches are 1-3, and eventually 1-2 could be squash
A minor change to speed up VM testing: clone submodules locally
(like we do with the QEMU repository).
Also add the script to MAINTAINERS.
Regards,
Phil.
Philippe Mathieu-Daudé (2):
MAINTAINERS: Add an entry for scripts/archive-source.sh
archive-source.sh: Clone the submodules locally
MAIN
Commit 5f9b1e35060b8 remove the dependency between OpenGL and X11.
However the milkymist-tmu2 device do require X11.
When using SDL, the configure script sets need_x11=yes, so the X11
flags are populated to the makefiles.
When building without SDL, X11 is not pulled and populated, leading
to a link
On 23/01/19 07:55, Yang Zhong wrote:
> This Kconfig implementation is rebased from Paolo's branch
> https://github.com/bonzini/qemu/commits/kconfig
>
> I rebased most of patches except non-x86 ARCHs dependency definitions
> this time.
> https://github.com/yangzhon/qemu/commits/topic/upstream/Kconf
We cloned the QEMU repository from the local storage. Since the
submodules are also available there, clone them too. This is
quicker and reduce network use.
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/archive-source.sh | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --
The scripts/archive-source.sh is used by the VM tests, it makes
sense to add it in the "Build and test automation" section.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index af339b86db..f7c38848ca 100644
---
On 1/22/19 7:39 AM, BALATON Zoltan wrote:
> The device was initialised in ISA compatibility mode and native PCI
> IDE mode was not implemented but no clents are known to need ISA mode
> but to the contrary, most clients that want to switch to and use
> device in native PCI IDE mode. Therefore im
On 1/10/19 7:36 PM, BALATON Zoltan wrote:
> Hello,
>
> This series is a small refactoring that moves some common PCI IDE io
> mem ops functions from the CMD646 model to the PCI IDE model so a
> CMD646 specific type can be dropped from PCIIDEState, removes code
> duplication from SiI3112 model (
On 1/21/19 10:50 AM, Peter Maydell wrote:
> Expose "start-powered-off" as a property of the ARMv7M container,
> which we just pass through to the CPU object in the same way that we
> do for "init-svtor" and "idau". (We want this for the SSE-200, which
> powers up only the first CPU at reset and lea
On 1/21/19 10:50 AM, Peter Maydell wrote:
> Rather than just creating the CPUs with object_new, make them child
> objects of the armv7m container. This will allow the cluster code to
> find the CPUs if an armv7m object is made a child of a cluster object.
> object_new_with_props() will do the paren
On 1/21/19 10:50 AM, Peter Maydell wrote:
> Currently the ARMv7M NVIC object's realize method assumes that the
> CPU the NVIC is attached to is CPU 0, because it thinks there can
> only ever be one CPU in the system. To allow a dual-Cortex-M33
> setup we need to remove this assumption; instead the
On 1/23/19 11:59 AM, Aaron Lindsay OS wrote:
> A bug was introduced during a respin of:
>
> commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a
> target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
>
> This patch introduced two calls to get_pmceid() during CPU
> initia
On 1/23/19 1:32 PM, Aaron Lindsay OS wrote:
> Make PMU overflow interrupts more accurate by using a timer to predict
> when they will overflow rather than waiting for an event to occur which
> allows us to otherwise check them.
>
> Signed-off-by: Aaron Lindsay
> ---
> target/arm/cpu.c| 12 ++
On 1/23/19 1:32 PM, Aaron Lindsay OS wrote:
> +uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
> + INT64_MIN : INT32_MIN;
With type promotion, this is the same as writing
? 0x8000ull : 0x8000ull
which is probably not wha
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 2 +-
tcg/riscv/tcg-target.inc.c | 126 -
2 files changed, 56 insertions(+), 72 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 1eb032626c..83b123ca03 100644
--
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.inc.c | 143 +++
2 files changed, 72 insertions(+), 73 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index c5a7064bdc..679aaf097e 100644
--- a/tc
This is automatic due to TCI using the other softtlb macros.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 816dc4697c..d9a28752c1 100644
--- a/tcg/tci/tcg-target.h
++
From: "Emilio G. Cota"
As the following experiments show, this series is a net perf gain,
particularly for memory-heavy workloads. Experiments are run on an
Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz.
1. System boot + shudown, debian aarch64:
- Before (v3.1.0):
Performance counter stats for './d
On 1/23/19 5:39 PM, David Kozub wrote:
> On Thu, 17 Jan 2019, John Snow wrote:
>
>> Admittedly I'm not too sure of how the ATA support in Linux works to
>> know what the passthrough would actually look like, bit-wise. I know
>> there's some SCSI abstraction layer that can drive ATA devices, but
Patch the branch after it has been emitted rather
than before it exists.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.inc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index be0bc92e8e..c5d7067f89 100644
Now that all tcg backends support TCG_TARGET_IMPLEMENTS_DYN_TLB,
remove the define and the old code.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 46
include/exec/cpu_ldst.h | 14
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/t
From: "Emilio G. Cota"
Disabled in all TCG backends for now.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Message-Id: <20190116170114.26802-3-c...@braap.org>
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 57 ++-
include/exec/cpu_ld
Signed-off-by: Richard Henderson
---
tcg/s390/tcg-target.h | 2 +-
tcg/s390/tcg-target.inc.c | 45 +--
2 files changed, 20 insertions(+), 27 deletions(-)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 394b545369..357528dd97 100644
--- a/
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/aarch64/tcg-target.inc.c | 100 +--
2 files changed, 60 insertions(+), 42 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 68868a27eb..5085a81060 100
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.h | 2 +-
tcg/mips/tcg-target.inc.c | 94 ++-
2 files changed, 64 insertions(+), 32 deletions(-)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 8600eefd9a..40adbe38cb 100644
--- a/
From: "Emilio G. Cota"
Currently we evict an entry to the victim TLB when it doesn't match
the current address. But it could be that there's no match because
the current entry is empty (i.e. all -1's, for instance via tlb_flush).
Do not evict the entry to the vtlb in that case.
This change will
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target.h | 2 +-
tcg/sparc/tcg-target.inc.c | 82 +++---
2 files changed, 51 insertions(+), 33 deletions(-)
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index dc0a227890..6020a670c0 100644
---
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 91 ++--
2 files changed, 52 insertions(+), 41 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index b51854b5cf..95b735b0bb 100644
--- a/tcg
This is Emilio's v7 unchanged, plus all of the backends updated.
Finally, remove the static tlb sizing so that we only support
the one code path.
I have tested all of these, though riscv, s390 and mips were
done under qemu emulation itself.
I'll leave some time for comment, but otherwise will in
On Thu, 17 Jan 2019, John Snow wrote:
Admittedly I'm not too sure of how the ATA support in Linux works to
know what the passthrough would actually look like, bit-wise. I know
there's some SCSI abstraction layer that can drive ATA devices, but I'm
not completely clear on the actual plumbing. How
On Wed, Jan 23, 2019 at 04:18:16PM -0600, Eric Blake wrote:
> On 1/23/19 3:55 PM, Richard W.M. Jones wrote:
> > On Wed, Jan 23, 2019 at 03:19:53PM -0600, Eric Blake wrote:
> >> The existing qemu-nbd --partition code claims to handle logical
> >> partitions up to 8, since its introduction in 2008 (c
On 1/23/19 3:55 PM, Richard W.M. Jones wrote:
> On Wed, Jan 23, 2019 at 03:19:53PM -0600, Eric Blake wrote:
>> The existing qemu-nbd --partition code claims to handle logical
>> partitions up to 8, since its introduction in 2008 (commit 7a5ca86).
>> However, the implementation is bogus (actual MBR
On Wed, Jan 23, 2019 at 8:12 AM Thomas Huth wrote:
>
> On 2019-01-23 07:55, Yang Zhong wrote:
> > Add the new configs to default-configs/riscv*-sofmmu.mak.
> >
> > Signed-off-by: Yang Zhong
> > ---
> > default-configs/riscv32-softmmu.mak | 7 +++
> > default-configs/riscv64-softmmu.mak | 7
On Wed, Jan 23, 2019 at 03:19:53PM -0600, Eric Blake wrote:
> The existing qemu-nbd --partition code claims to handle logical
> partitions up to 8, since its introduction in 2008 (commit 7a5ca86).
> However, the implementation is bogus (actual MBR logical partitions
> form a sort of linked list, wi
On Mon, 21 Jan 2019 at 14:15, Gerd Hoffmann wrote:
>
> The following changes since commit 681d61362d3f766a00806b89d6581869041f73cb:
>
> Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request'
> into staging (2019-01-17 12:48:42 +)
>
> are available in the git repository at:
Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c| 12
target/arm/cpu.h| 10 +++
target/arm/helpe
Most of this patchset to implement the PMU has been merged already, but
the interrupt-on-overflow behavior had some additional review comments.
In addition to improving the overflow detection and bit-clearing logic,
I split the previous patch [1] into two to (hopefully) make it more
digestable.
Th
Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 61 +
1 file changed, 51 insertions(+), 10
This patch adds a new option to the input-linux object:
grab-toggle=[key-combo]
The key combination can be one of the following:
* ctrl-ctrl
* alt-alt
* meta-meta
* scrolllock
* ctrl-scrolllock
The user can pick any of these key combinations. The VM's grab
of the evdev device will be toggled wh
The latest revision of the input-linux customizable grab toggle keys
patch.
Signed-off-by: Ryan El Kochta
---
qapi/ui.json | 10
ui/input-linux.c | 66 +---
2 files changed, 73 insertions(+), 3 deletions(-)
diff --git a/qapi/ui.json b/qap
From: Steffen Görtz
Signed-off-by: Steffen Görtz
Signed-off-by: Stefan Hajnoczi
---
tests/microbit-test.c | 97 +++
1 file changed, 97 insertions(+)
diff --git a/tests/microbit-test.c b/tests/microbit-test.c
index 0c125535f6..d3edd38643 100644
--- a/tes
From: Steffen Görtz
Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC.
Signed-off-by: Steffen Görtz
Reviewed-by: Peter Maydell
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Stefan Hajnoczi
---
include/hw/arm/nrf51_soc.h | 2 ++
hw/arm/nrf51_soc.c | 41 +++--
ROM devices go via MemoryRegionOps->write() callbacks for write
operations and do not dirty/invalidate that memory. Device emulation
must be able to mark memory ranges that have been modified internally
(e.g. using memory_region_get_ram_ptr()).
Introduce the memory_region_flush_rom_device() API f
From: Steffen Görtz
The nRF51 contains three regions of non-volatile memory (NVM):
- CODE (R/W): contains code
- FICR (R): Factory information like code size, chip id etc.
- UICR (R/W): Changeable configuration data. Lock bits, Code
protection configuration, Bootloader address, Nordic SoftRadio
On Wed, Jan 23, 2019 at 1:15 AM Bastian Koppelmann
wrote:
>
>
> On 1/22/19 10:38 PM, Richard Henderson wrote:
> > On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> >> Hi,
> >>
> >> this patchset converts the RISC-V decoder to decodetree in four major
> >> steps:
> >>
> >> 1) Convert 32-bit instruct
pflash devices should mark the memory region dirty and invalidate TBs
after directly writing to the RAM backing the ROM device.
Note that pflash_cfi01_get_memory() is used by several machine types to
populate ROM contents directly. Callers are untouched by this patch
because they only modify memo
On Tue, Jan 22, 2019 at 04:36:36PM +, Peter Maydell wrote:
> On Sun, 20 Jan 2019 at 14:35, Stefan Hajnoczi wrote:
> >
> > ROM devices go via MemoryRegionOps->write() callbacks for write
> > operations and do not dirty/invalidate that memory. Device emulation
> > must be able to mark memory ra
On 1/22/19 10:55 PM, Yang Zhong wrote:
> @@ -19,3 +19,5 @@ CONFIG_I8259=y
> CONFIG_MC146818RTC=y
> CONFIG_ISA_TESTDEV=y
> CONFIG_SMC37C669=y
> +CONFIG_DP264=y
> +CONFIG_TYPHOON=y
There's not really a point in two configs; just use DP264.
But beyond that, is there a point in adding configury th
On Wed, 23 Jan 2019 at 21:07, Stefan Hajnoczi wrote:
>
> On Tue, Jan 22, 2019 at 04:36:36PM +, Peter Maydell wrote:
> > API and implementation make sense to me, but better that Paolo reviews
> > this I think. I guess we should add calls to this to the pflash device
> > models too...
>
> Okay,
On 1/22/19 10:55 PM, Yang Zhong wrote:
> Add the new configs to default-configs/hppa-sofmmu.mak.
>
> Signed-off-by: Yang Zhong
> ---
> default-configs/hppa-softmmu.mak | 2 ++
> hw/hppa/Makefile.objs| 4 +++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/default
v2:
* Add Patch 2 to call memory_region_flush_rom_device() from pflash devices
[Peter]
This series adds the Non-Volatile Memory Controller, which controls access to
the User Information Control Registers (UICR), Factory Information Control
Registers (FICR), and flash memory.
This is the last
On 1/22/19 10:55 PM, Yang Zhong wrote:
> +++ b/hw/moxie/Makefile.objs
> @@ -1,2 +1,2 @@
> # moxie boards
> -obj-y += moxiesim.o
> +obj-$(CONFIG_MOXIE) += moxiesim.o
Repeat question about single machine type.
r~
On 1/22/19 10:55 PM, Yang Zhong wrote:
> make virt code configurable and the new CONFIG_VIRT definitions
> added to the default-configs/arm-softmmu.mak to replace CONFIG_ACPI
> in arm board.
>
> Signed-off-by: Yang Zhong
> Reviewed-by: Thomas Huth
> ---
> default-configs/arm-softmmu.mak | 1 +
>
On 1/22/19 10:56 PM, Yang Zhong wrote:
> default-configs/alpha-softmmu.mak | 1 -
Acked-by: Richard Henderson
r~
On 1/22/19 10:56 PM, Yang Zhong wrote:
> default-configs/alpha-softmmu.mak | 2 +-
Acked-by: Richard Henderson
r~
The existing qemu-nbd --partition code claims to handle logical
partitions up to 8, since its introduction in 2008 (commit 7a5ca86).
However, the implementation is bogus (actual MBR logical partitions
form a sort of linked list, with one partition per extended table
entry, rather than four logical
On 1/23/19 7:33 PM, Stefan Hajnoczi wrote:
> New source files were added without corresponding ./MAINTAINERS file
> entries. Let's get things up to date.
>
> Reviewed-by: Thomas Huth
> Signed-off-by: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
> ---
> v2:
> * Simplify using wildcard
Hi Gerd,
On 1/18/19 1:22 PM, Gerd Hoffmann wrote:
> Get rid of the pcspk_state global, allow pc speaker
> be added using "-device isa-pcspk".
>
> Signed-off-by: Gerd Hoffmann
> ---
> hw/audio/pcspk.c | 35 +++
> 1 file changed, 15 insertions(+), 20 deletions(-)
>
On 1/23/19 2:13 PM, Zoltán Kővágó wrote:
>>> { 'struct': 'AudiodevPaPerDirectionOptions',
>>>'data': {
>>> -'*name': 'str' } }
>>> +'*name':'str',
>>> +'*channel-map': 'str' } }
>>
>> Ah, I see. Thats why patch #1 creates a AudiodevPaPerDirectionOptions
>> struct with jus
On Wed, Jan 23, 2019 at 06:55:07PM +0100, Stefano Garzarella wrote:
> On Wed, Jan 23, 2019 at 04:53:10PM +, Stefan Hajnoczi wrote:
> > Signed-off-by: Stefan Hajnoczi
> > ---
> > v2:
> > * Added mentor names
> > * Added additional details from Marc-André and Paolo
> > ---
> > _posts/2019-01-
On 2019-01-17 10:22, Gerd Hoffmann wrote:
> On Thu, Jan 17, 2019 at 12:36:48AM +0100, Kővágó, Zoltán wrote:
>> Remove glob_audio_state from functions, where possible without breaking
>> the API. This means that most static functions in audio.c now take an
>> AudioState pointer instead of implicitl
Hi Alex,
On Mon, Jan 21, 2019 at 11:54 PM Philippe Mathieu-Daudé
wrote:
>
> On 1/21/19 6:15 PM, Alex Bennée wrote:
> > This allows us to invoke the build with a custom target (for the VMs
> > that use the {target} format string specifier). Currently OpenBSD is
> > still hardwired due to problems
On Jan 18 14:13, Peter Maydell wrote:
> On Tue, 11 Dec 2018 at 15:20, Aaron Lindsay
> wrote:
> >
> > The ARM PMU implementation currently contains a basic cycle counter, but
> > it is often useful to gather counts of other events, filter them based
> > on execution mode, and/or be notified on coun
Hey Stefan,
Not trying to ignore you here. I have reached out to members of management on
our side I just don’t have any responses yet on what we can do here. Will
update as I learn more.
Thanks,
Justin Terry
> -Original Message-
> From: Stefan Weil
> Sent: Thursday, January 17, 2019
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