Peter Xu writes:
> On Fri, Sep 28, 2018 at 01:00:26PM +0400, Marc-André Lureau wrote:
>> Hi
>>
>> On Fri, Sep 28, 2018 at 12:02 PM Wolfgang Bumiller
>> wrote:
>> >
>> > Commit d32749deb615 moved the call to monitor_init_globals()
>> > to before os_daemonize(), making it an unsuitable place to
>
Signed-off-by: Suraj Jitindar Singh
---
linux-headers/asm-powerpc/kvm.h | 1 +
linux-headers/linux/kvm.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 1b32b56a03..8c876c166e 100644
--- a/linux-headers/asm-powerp
The ptcr (partition table control register) is used to store the address
and size of the partition table. For nested kvm-hv we have a level 1
guest register the location of it's partition table with the hypervisor.
Thus to support migration we need to be able to read this out of kvm
and restore it
This patch series adds the qemu support for running nested kvm-hv on a
POWER9 platform with appropriate hypervisor support and migration of
these guests.
That is, the ability to run kvm-hv guests as guests of an operating system
which is itself a kvm-hv guest.
The host (L0 hypervisor) and level 1
Add the spapr cap SPAPR_CAP_NESTED_KVM_HV to be used to control the
availability of nested kvm-hv to the level 1 (L1) guest.
Assuming a hypervisor with support enabled an L1 guest can be allowed to
use the kvm-hv module (and thus run it's own kvm-hv guests) by setting:
-machine pseries,cap-nested-
On Wed, 2018-10-10 at 10:57 -0700, Alistair wrote:
> On 10/10/2018 05:26 AM, Andrea Bolognani wrote:
> > * what should libvirt look for to figure out whether or not a RISC-V
> >guest will have PCI support? For aarch64 we look for the presence
> >of the 'gpex-pcihost' device, but of course t
On Wed, 2018-10-10 at 12:53 -0700, Alistair wrote:
> On 10/10/2018 11:47 AM, Stephen Bates wrote:
> > > Strange. Is there any reason you need to use the e1000? The VirtIO
> > > networking device works for me.
> >
> > As per above. The e1000 is there to test PCIe not networking.
Unless I'
On 10/10/18 11:42 PM, Eduardo Habkost wrote:
> On Wed, Oct 10, 2018 at 08:17:26PM -0400, Cleber Rosa wrote:
>>
>>
>> On 10/10/18 11:47 AM, Cleber Rosa wrote:
>>>
>>>
>>> On 10/10/18 10:28 AM, Eduardo Habkost wrote:
On Wed, Oct 10, 2018 at 10:15:15AM -0400, Cleber Rosa wrote:
>
>
>>>
According to the "Devicetree Specification, Release v0.2" 'model' is a
required property of the root node.
Some software like the Debian flash-kernel package rely on this property
to identify boards.
The patch sets the model property to 'qemu,virt'.
Signed-off-by: Heinrich Schuchardt
---
v2
On Wed, Oct 10, 2018 at 08:17:26PM -0400, Cleber Rosa wrote:
>
>
> On 10/10/18 11:47 AM, Cleber Rosa wrote:
> >
> >
> > On 10/10/18 10:28 AM, Eduardo Habkost wrote:
> >> On Wed, Oct 10, 2018 at 10:15:15AM -0400, Cleber Rosa wrote:
> >>>
> >>>
> >>> On 10/10/18 9:59 AM, Cleber Rosa wrote:
>
On Wed, 10/10 13:19, Paolo Bonzini wrote:
> On 09/10/2018 21:37, John Snow wrote:
> >
> >
> > On 08/14/2018 02:27 AM, Paolo Bonzini wrote:
> >> nvme_poll_queues is already protected by q->lock, and
> >> AIO callbacks are invoked outside the AioContext lock.
> >> So remove the acquire/release pair
On Wed, 10/10 13:19, Paolo Bonzini wrote:
> On 09/10/2018 21:37, John Snow wrote:
> >
> >
> > On 08/14/2018 02:27 AM, Paolo Bonzini wrote:
> >> nvme_poll_queues is already protected by q->lock, and
> >> AIO callbacks are invoked outside the AioContext lock.
> >> So remove the acquire/release pair
On Mon, 10/01 01:23, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> v2: Add get_default_jobs (Fam suggestion)
> ---
> tests/vm/basevm.py | 13 ++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/tests/vm/basevm.py b/tests/vm/basevm.py
From: "Edgar E. Iglesias"
Add a virtual Xilinx Versal board.
This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to auto-discover
periphera
From: "Edgar E. Iglesias"
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias
---
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/xlnx-versal.c| 324
include/hw/arm/xlnx-versal.h
From: "Edgar E. Iglesias"
Implement support for 64bit descriptor addresses.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 47
1 file changed, 39 insertions(+), 8 deletions(-)
diff --git a/hw/net/cadence_
On Wed, Oct 10, 2018 at 08:17:41PM -0500, Eric Blake wrote:
> On 10/10/18 7:05 PM, Peter Xu wrote:
>
> > > other than the command line that is hanging:
> > >
> > > /home/eblake/qemu/x86_64-softmmu/qemu-system-x86_64 -S -no-user-config
> > > -nodefaults -nographic -machine none,accel=kvm:tcg -qmp
From: "Edgar E. Iglesias"
Add support for selecting the Memory Region that the GEM
will do DMA to.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 59 ++--
include/hw/net/cadence_gem.h | 2 ++
2 files changed, 39 insertions(+), 22 deletions(
From: "Edgar E. Iglesias"
Add the ARM Cortex-A72.
Signed-off-by: Edgar E. Iglesias
---
target/arm/cpu64.c | 66 +++---
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index db71504cb5..44fdf0f6fa 100
From: "Edgar E. Iglesias"
This patch series adds initial support for Xilinx's Versal SoC.
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelli
From: "Edgar E. Iglesias"
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 6 +-
From: "Edgar E. Iglesias"
Announce 64bit addressing support.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 550225c15b..7f96de4aff 1
From: "Edgar E. Iglesias"
When QEMU provides the equivalent of the EL3 firmware, we
need to enable HVCs in scr_el3 when turning on CPUs that
target EL2.
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target/arm/arm-powerctl.c | 10 ++
1 file changed, 10 insertions(+)
From: "Edgar E. Iglesias"
Add macro with max number of DMA descriptor words.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 4 ++--
include/hw/net/cadence_gem.h | 5 -
2 files cha
From: "Edgar E. Iglesias"
Add support for extended descriptors with optional 64bit
addressing and timestamping. QEMU will not yet provide
timestamps (always leaving the valid timestamp bit as zero).
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c
From: "Edgar E. Iglesias"
Disable the Timestamping Unit feature bit since QEMU does not
yet support it. This allows guest SW to correctly probe for
its existance.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1
From: "Edgar E. Iglesias"
Use uint32_t instead of unsigned to describe 32bit descriptor words.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 42 ++--
include/hw/net/cadence
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Thursday, October 11, 2018 4:35 AM
> To: Liu, Jingqi
> Cc: Xu, Tao3 ; pbonz...@redhat.com; r...@twiddle.net;
> qemu-devel@nongnu.org; Robert Hoo
> Subject: Re: [PATCH 1/1] i386: Add new model of Cascadelake-
On 10/10/18 7:05 PM, Peter Xu wrote:
other than the command line that is hanging:
/home/eblake/qemu/x86_64-softmmu/qemu-system-x86_64 -S -no-user-config
-nodefaults -nographic -machine none,accel=kvm:tcg -qmp
unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile
/var/lib/l
On 10/4/18 6:22 AM, Tomáš Golembiovský wrote:
In the subject: s/retrived/retrieved/
The guest-get-fsinfo command collects also information about PCI
controller where the disk is attached. When this fails for some reasons
it tries to return just the partial information. However in certain
cases
On 10/10/18 5:29 PM, Philippe Mathieu-Daudé wrote:
In the subject: s/prefered/preferred/
Signed-off-by: Philippe Mathieu-Daudé
---
.mailmap | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
+
+# This section is to track prefered (or last up to date) email for
On 10/10/18 11:47 AM, Cleber Rosa wrote:
>
>
> On 10/10/18 10:28 AM, Eduardo Habkost wrote:
>> On Wed, Oct 10, 2018 at 10:15:15AM -0400, Cleber Rosa wrote:
>>>
>>>
>>> On 10/10/18 9:59 AM, Cleber Rosa wrote:
On 10/10/18 9:46 AM, Eduardo Habkost wrote:
> On Wed, Oct 10, 2018
Public bug reported:
Since RPi Kernel 1.20170427, qemu is no longer able to emulate the
Rasberry Pi, as the linux kernel is complaining about timing issues.
Old kernel output - https://pastebin.com/wvkneNNF
New kernel output - https://pastebin.com/QTwgCkV2
Note that the actual error is caused by
On Fri, Sep 28, 2018 at 09:58:30AM +0200, Wolfgang Bumiller wrote:
> The early monitor iothread creation conflicts with the -daemonize option
> causing crashes at shutdown of a daemonized qemu instance.
> These patches will delay the creation to when a monitor using it is
> actually spawned.
>
> W
Quoting Tomáš Golembiovský (2018-10-04 06:22:28)
> The guest-get-fsinfo command collects also information about PCI
> controller where the disk is attached. When this fails for some reasons
> it tries to return just the partial information. However in certain
> cases the pointer to the structure wa
Quoting Tomáš Golembiovský (2018-10-04 06:22:29)
> Handle returned NULLs properly to:
> - avoid crashes in serialization.
> - properly report errors to the caller
>
> Signed-off-by: Tomáš Golembiovský
> ---
> qga/commands-win32.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
On Wed, Oct 10, 2018 at 03:27:34PM -0500, Eric Blake wrote:
> On 10/10/18 2:26 PM, Eric Blake wrote:
>
> >
> > On the other hand, when I'm trying to use a qemu binary with these
> > patches applied, libvirt is hanging when trying to probe the
> > capabilities of the binary, waiting for a response
On 10/9/2018 11:04 AM, Kamil Rytarowski wrote:
On 09.10.2018 16:12, Peter Maydell wrote:
On 9 October 2018 at 14:52, Kamil Rytarowski wrote:
On 07.10.2018 17:37, Brad Smith wrote:
Use MAP_STACK in qemu_alloc_stack() on OpenBSD.
Added to -current and will be in our soon to be 6.4 release.
M
If the format is not the syscall last argument, a comma is append.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
linux-user/strace.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 5435d01569.
Signed-off-by: Philippe Mathieu-Daudé
Tested-By: Guido Günther
---
linux-user/strace.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index ca2cd75993..425c06d169 100644
--- a/linux-user/strace.c
+++ b/linux-us
Signed-off-by: Philippe Mathieu-Daudé
Tested-By: Guido Günther
---
linux-user/syscall_defs.h | 7 +++
linux-user/syscall.c | 6 --
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 18d434d6dc..8ddeec1bae 10064
Suggested-by: Laurent Vivier
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 33f4a506a2..c95557bf83 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -
Signed-off-by: Philippe Mathieu-Daudé
Tested-By: Guido Günther
Reviewed-by: Laurent Vivier
---
linux-user/strace.c| 13 +
linux-user/strace.list | 2 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 10ae22263c..ca
Signed-off-by: Philippe Mathieu-Daudé
Tested-By: Guido Günther
Reviewed-by: Laurent Vivier
---
linux-user/syscall.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index ae3c0dfef7..ea503381aa 100644
--- a/linux-user/syscall.c
+++ b/linux-use
Hi Laurent,
Few patches I'v been writting while trying to figure out this issue:
http://lists.nongnu.org/archive/html/qemu-arm/2018-01/msg00514.html
As usual with linux-user files, this series will trigger some checkpatch
benign warnings.
Regards,
Phil.
Since v4:
- rebased on master (no change
Suggested-by: Laurent Vivier
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index c95557bf83..10ae22263c 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
Extract common print_sockfd() from various socket related syscalls.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 425c06d169..5435d01569 100644
This probably happened when interpreting the utf8 name as latin1.
Fixes dbbaaff6867 and f4e94dfefb6.
Signed-off-by: Philippe Mathieu-Daudé
---
.mailmap | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/.mailmap b/.mailmap
index 2c2b9b1205..6f2ff22a45 100644
--- a/.mailmap
++
Signed-off-by: Philippe Mathieu-Daudé
---
.mailmap | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/.mailmap b/.mailmap
index 6f2ff22a45..8475adf799 100644
--- a/.mailmap
+++ b/.mailmap
@@ -4,26 +4,31 @@
# into proper addresses so that they are counted p
Hi,
This amazing series sort a bit the mailmap sections,
then fix Reimar Döffinger name from 2 missed commits.
Regards,
Phil.
Philippe Mathieu-Daudé (2):
mailmap: Fix Reimar Döffinger name
mailmap: Split 'prefered emails' from 'original git import' section
.mailmap | 24 +++---
On 10/10/2018 23:31, Philippe Mathieu-Daudé wrote:
> Both Python 2.7 and 3 support the same io.StringIO to
> handle unicode strings.
>
> Use the common form to use indistinctly Python 2.7 or 3.
>
> http://python-future.org/compatible_idioms.html#stringio
>
> This fixes running tests on the Fedor
Introduced in 48ebf2f90f8 and faf1e708d5b, these functions
were never used. Remove them.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-bridge/xio3130_downstream.h | 11 ---
hw/pci-bridge/xio3130_upstream.h | 10 --
hw/pci-bridge/xio3130_downstream.c | 28 +---
Noted while refactoring:
CC mips-softmmu/hw/mips/gt64xxx_pci.o
In file included from include/hw/pci-host/gt64xxx.h:2,
from hw/mips/gt64xxx_pci.c:30:
include/hw/pci/pci_bus.h:23:5: error: unknown type name ‘PCIIOMMUFunc’
PCIIOMMUFunc iommu_fn;
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-bridge/ioh3420.h | 6 --
hw/pci-bridge/ioh3420.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
delete mode 100644 hw/pci-bridge/ioh3420.h
diff --git a/hw/pci-bridge/ioh3420.h b/hw/pci-bridge/ioh3420.h
deleted file mode 100644
index
Hi Michael, these are obvious cleanups patches.
I might ressurect David's old series later:
https://lists.gnu.org/archive/html/qemu-devel/2017-11/msg05277.html
Regards,
Phil.
Philippe Mathieu-Daudé (3):
hw/pci-bridge/xio3130: Remove unused functions
hw/pci-bridge/ioh3420: Remove unuseful he
Both Python 2.7 and 3 support the same io.StringIO to
handle unicode strings.
Use the common form to use indistinctly Python 2.7 or 3.
http://python-future.org/compatible_idioms.html#stringio
This fixes running tests on the Fedora Docker image,
which uses Python3 since 356dc290f:
$ make docke
Ping?
On 10/1/18 1:23 AM, Philippe Mathieu-Daudé wrote:
> Hi Fam,
>
> Since v1:
> http://lists.nongnu.org/archive/html/qemu-devel/2018-07/msg03411.html
> - rebased on master
> - added get_default_jobs (Fam)
> - dropped 'When using TCG, wait longer for a VM to start'
>
> Few patches I added whil
Eric corrected s/Voluntary/Volunteer/ in the subject line.
On 9/30/18 11:47 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ce7c351afa..2708745bf7 100644
>
Ping?
On 9/30/18 11:47 PM, Philippe Mathieu-Daudé wrote:
> After noticing Fredrik patch [1] clashes with an ongoing work, I shared my
> concerns after the current limitations of CPUMIPSState::insn_flags, having
> 1 bit left to store more 'Chip specific instructions'.
>
> Since v2: https://lists.g
On Wed, Oct 10, 2018 at 09:10:25AM -0700, Li Qiang wrote:
> Cc: qemu-triv...@nongnu.org
> Signed-off-by: Li Qiang
Queued, thanks.
--
Eduardo
Add arrays to hold the registers, the definitions themselves, access
functions, and logic to reset counters when PMCR.P is set. Update
filtering code to support counters other than PMCCNTR. Support migration
with raw read/write functions.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.
Setup a QEMUTimer to get a callback when we expect counters to next
overflow and trigger an interrupt at that time.
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c| 11
target/arm/cpu.h| 7 +++
target/arm/helper.c | 126 +---
3 files chan
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 89ceb34cb9..6c2a899009 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9
In some cases it may be helpful to modify state before saving it for
migration, and then modify the state back after it has been saved. The
existing pre_save function provides half of this functionality. This
patch adds a post_save function to provide the second half.
Signed-off-by: Aaron Lindsay
The pmu_counter_enabled and pmu_op_start/finish functions are generic
(as opposed to PMCCNTR-specific) to allow for the implementation of
other events.
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/cpu.c | 3 ++
target/arm/cpu.h | 22 +++-
target/arm/help
pmccntr_read and pmccntr_write contained duplicate code that was already
being handled by pmccntr_sync. Consolidate the duplicated code into two
functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to
c15_ccnt in CPUARMState so that we can simultaneously save both the
architectural re
This is an amendment to my earlier patch:
commit 7ece99b17e832065236c07a158dfac62619ef99b
Author: Aaron Lindsay
Date: Thu Apr 26 11:04:39 2018 +0100
target/arm: Mask PMU register writes based on PMCR_EL0.N
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 1 +
1 file
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/helper.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 52bd13fdde..e804caaced 100644
--- a/target/arm/helper.c
+++ b/target/arm
The instruction event is only enabled when icount is used, cycles are
always supported. Always defining get_cycle_count (but altering its
behavior depending on CONFIG_USER_ONLY) allows us to remove some
CONFIG_USER_ONLY #defines throughout the rest of the code.
Signed-off-by: Aaron Lindsay
Review
This commit doesn't add any supported events, but provides the framework
for adding them. We store the pm_event structs in a simple array, and
provide the mapping from the event numbers to array indexes in the
supported_event_map array. Because the value of PMCEID[01] depends upon
which events are
I previously fixed this for PMINTENSET_EL1, but missed these.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c83f7c1109..52c76b7444 100644
Add an array for PMOVSSET so we only define it for v7ve+ platforms
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 28
1 file changed, 28 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e804caaced..f3c00c3db0 100644
--- a/target/arm
Because of the PMU's design, many register accesses have side effects
which are inter-related, meaning that the normal method of saving CP
registers can result in inconsistent state. These side-effects are
largely handled in *op_start and *op_finish functions which can be
called globally once befor
The ARM PMU implementation currently contains a basic cycle counter, but
it is often useful to gather counts of other events, filter them based
on execution mode, and/or be notified on counter overflow. These patches
flesh out the implementations of various PMU registers including
PM[X]EVCNTR and P
On Wed, Oct 10, 2018 at 01:49:56AM +, Liu, Jingqi wrote:
> Hi Eduardo/Paolo,
>
> Do you have any comments about this patch ?
Thanks for the reminder and sorry for the delay. I was waiting
for MSR features to be merged before including this CPU model.
But considering that it's taking a while
On 10/10/18 2:26 PM, Eric Blake wrote:
On the other hand, when I'm trying to use a qemu binary with these
patches applied, libvirt is hanging when trying to probe the
capabilities of the binary, waiting for a response to
"qmp_capabilities". I'll try and bisect which patch is causing the
pro
On 10/8/18 1:31 PM, Markus Armbruster wrote:
Calling error_report() in a function that takes an Error ** argument
is suspicious. tpm_init_tpmdev() does that, and then fails without
setting an error. Its caller main(), via tpm_init() and
qemu_opts_foreach(), is fine with it, but clean it up anyw
On Mon, 08 Oct 2018 11:25:45 PDT (-0700), alistair.fran...@wdc.com wrote:
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 2 ++
1 file changed, 2 inser
On Mon, 08 Oct 2018 11:25:27 PDT (-0700), alistair.fran...@wdc.com wrote:
From: Michael Clark
This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.
Cc: Sagar Karandik
On Mon, 08 Oct 2018 11:25:56 PDT (-0700), alistair.fran...@wdc.com wrote:
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_u.c | 4 +++-
hw/riscv/spike.c| 6 --
hw/riscv/virt.c | 4 +++-
3
On Mon, 08 Oct 2018 11:25:36 PDT (-0700), alistair.fran...@wdc.com wrote:
From: Michael Clark
* Add user-mode CSR defininitions.
* Reorder CSR definitions to match the specification.
* Change H mode interrupt comment to 'reserved'.
* Remove unused X_COP interrupt.
* Add user-mode interrupts.
*
On Mon, 08 Oct 2018 11:25:17 PDT (-0700), alistair.fran...@wdc.com wrote:
From: Michael Clark
Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_u
On 10/10/2018 12:01 PM, Stephen Bates wrote:
I added e1000 and e1000e support to my kernel and changed the QEMU command to:
So using -device e1000e rather than -device e1000 seems to work. I am not sure
why -device e1000 causes a kernel panic. The MSI-X message is interesting and
may be rela
On 10/10/18 2:07 PM, Peter Maydell wrote:
> On 10 October 2018 at 18:52, Cleber Rosa wrote:
>>
>>
>> On 10/10/18 12:23 PM, Peter Maydell wrote:
>>> On 10 October 2018 at 16:47, Cleber Rosa wrote:
To make sure we're on the same page, we're still going to have default
machine types, ba
On 10/10/2018 11:47 AM, Stephen Bates wrote:
Why do you need two networking options?
I don't need the e1000 for networking. The e1000 option is there to test the
PCIe since it implements a PCIe model of the e1000 NIC. Basically it's another
test path for your PCIe patches and was used
On 10/10/18 11:26 AM, Eric Blake wrote:
On 10/9/18 1:27 AM, Peter Xu wrote:
Based-on: <20180828191048.29806-1-arm...@redhat.com>
Based-on: <2018090716.1675-1-arm...@redhat.com>
(this series is based on Markus's monitor-next tree)
v9:
- add r-bs
- release the qmp queue lock before resume [M
On 08/10/2018 20:25, Alistair Francis wrote:
> From: Michael Clark
>
> Cc: Palmer Dabbelt
> Cc: Sagar Karandikar
> Cc: Bastian Koppelmann
> Cc: Alistair Francis
> Signed-off-by: Michael Clark
> Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/riscv/virt.c | 2
On 08/10/2018 20:25, Alistair Francis wrote:
> From: Michael Clark
>
> This patch makes op_helper.c contain only instruction
> operation helpers used by translate.c and moves any
> unrelated cpu helpers into cpu_helper.c. No logic is
> changed by this patch.
>
> Cc: Sagar Karandikar
> Cc: Basti
On 08/10/2018 20:25, Alistair Francis wrote:
> From: Michael Clark
>
> Cc: Palmer Dabbelt
> Cc: Alistair Francis
> Signed-off-by: Michael Clark
> Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/riscv/sifive_u.c | 4 +++-
> hw/riscv/spike.c| 6 --
> hw/
* Ilya Maximets (i.maxim...@samsung.com) wrote:
> 'fd' received from the vhost side is never freed.
> Also, everything (including 'postcopy_listen' state) should be
> cleaned up on vhost cleanup.
>
> Fixes: 46343570c06e ("vhost+postcopy: Wire up POSTCOPY_END notify")
> Fixes: f82c11165ffa ("vhost+
On 10/10/18 20:56, Paolo Bonzini wrote:
> On 09/10/2018 19:09, Laszlo Ersek wrote:
>>>memory_region_size() != 0
>>> and therefore it's ok to access it in
>>>file_backend_unparent()
>>> if (memory_region_size() != 0)
>>> memory_region_get_ram_ptr()
>>>
>>> which happens when
* Ilya Maximets (i.maxim...@samsung.com) wrote:
> POSTCOPY_NOTIFY_INBOUND_END handlers will remove userfault fds
> from the postcopy_remote_fds array which could be still in
> use by the fault thread. Let's stop the thread before
> notification to avoid possible accessing wrong memory.
OK I think;
> I added e1000 and e1000e support to my kernel and changed the QEMU command to:
So using -device e1000e rather than -device e1000 seems to work. I am not sure
why -device e1000 causes a kernel panic. The MSI-X message is interesting and
may be related to why NVMe interrupts are not reaching the
On 09/10/2018 19:09, Laszlo Ersek wrote:
>>memory_region_size() != 0
>> and therefore it's ok to access it in
>>file_backend_unparent()
>> if (memory_region_size() != 0)
>> memory_region_get_ram_ptr()
>>
>> which happens when object_add fails and unparents failed backend mak
Device trees in the Linux kernel generally provide a model property. Some
software like the Debian flash-kernel package rely on this property to
identify boards.
The patch sets the model property for the virt boards to 'QEMU virt'.
Signed-off-by: Heinrich Schuchardt
---
hw/arm/virt.c | 1 +
1 f
>Why do you need two networking options?
I don't need the e1000 for networking. The e1000 option is there to test the
PCIe since it implements a PCIe model of the e1000 NIC. Basically it's another
test path for your PCIe patches and was used for testing when PCIe support to
the arm virt mod
On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.mayd...@linaro.org wrote:
On 10 October 2018 at 18:49, Palmer Dabbelt wrote:
we should really
get the ball rolling on our big patch backlog.
Yes, please do. Softfreeze is not all that far away and I
would strongly prefer not to get an enormous s
On 10/10/2018 07:03 PM, Tony Krowiak wrote:
> This patch series is the QEMU counterpart to the KVM/kernel support for
> guest dedicated crypto adapters. The KVM/kernel model is built on the
> VFIO mediated device framework and provides the infrastructure for
> granting exclusive guest access t
On 10/10/2018 11:10 AM, Peter Maydell wrote:
On 10 October 2018 at 18:49, Palmer Dabbelt wrote:
we should really
get the ball rolling on our big patch backlog.
Yes, please do. Softfreeze is not all that far away and I
would strongly prefer not to get an enormous sized pull
request at the l
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