Can you attach gdb to qemu when the guest hangs, then run "thread apply
all bt"?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1787070
Title:
Guests using the qxl-vga are freezing
Status in QEMU:
Thomas Huth writes:
> On 08/14/2018 07:53 PM, Markus Armbruster wrote:
>> Thomas Huth writes:
>>
>>> Introspection should not change the qom-tree / qtree, so we should check
>>> this in the device-introspect-test, too. This patch helped to find lots
>>> of instrospection bugs during the QEMU v3
Thomas Huth writes:
> On 08/14/2018 07:53 PM, Markus Armbruster wrote:
>> Thomas Huth writes:
> [...]
>>> @@ -115,10 +122,18 @@ static void test_one_device(const char *type)
>>>
>>> /*
>>> * Some devices leave dangling pointers in QOM behind.
>>> - * "info qom-tree" has a good c
On Wed, Aug 15, 2018 at 07:58:52AM +0200, Markus Armbruster wrote:
> I'm afraid I let this fall through the cracks. Sorry about that!
>
> PATCH 2 conflicts semantically with commmit 63b88968f13: the latter adds
> a trace_vtd_err() the former doesn't replace. Please respin.
Will do.
Regards,
-
On 08/14/2018 07:10 PM, Paolo Bonzini wrote:
> On 14/08/2018 18:11, Thomas Huth wrote:
>> On 08/14/2018 06:03 PM, Paolo Bonzini wrote:
>>> On 14/08/2018 18:01, Thomas Huth wrote:
On 08/14/2018 05:57 PM, Paolo Bonzini wrote:
> On 14/08/2018 17:43, Thomas Huth wrote:
>> The machines whic
On 08/14/2018 07:53 PM, Markus Armbruster wrote:
> Thomas Huth writes:
[...]
>> @@ -115,10 +122,18 @@ static void test_one_device(const char *type)
>>
>> /*
>> * Some devices leave dangling pointers in QOM behind.
>> - * "info qom-tree" has a good chance at crashing then
>> +
I'm afraid I let this fall through the cracks. Sorry about that!
PATCH 2 conflicts semantically with commmit 63b88968f13: the latter adds
a trace_vtd_err() the former doesn't replace. Please respin.
On 08/14/2018 07:53 PM, Markus Armbruster wrote:
> Thomas Huth writes:
>
>> Introspection should not change the qom-tree / qtree, so we should check
>> this in the device-introspect-test, too. This patch helped to find lots
>> of instrospection bugs during the QEMU v3.0 soft/hard-freeze period in
On Wed, Aug 15, 2018 at 11:09:42 +0800, Fam Zheng wrote:
> On Mon, 08/13 13:11, Emilio G. Cota wrote:
> > + --enable-sync-profiler) sync_profiler="yes"
> > + ;;
>
> Curious, not asking for a change: can this be made a runtime option instead of
> compile time, since there's no library dependencie
"Emilio G. Cota" writes:
> On Tue, Aug 14, 2018 at 10:13:12 +0200, Paolo Bonzini wrote:
>> On 13/08/2018 19:11, Emilio G. Cota wrote:
>> > +struct qsp_report rep;
>>
>> Don't like camelcase? But that's really all that I have to remark on
>> this lovely series.
>
> I have a strong aversion t
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180809141403.11296-1-o...@aepfle.de
Subject: [Qemu-devel] [PATCH v1] exec: handle NULL pointer in
flatview_read_continue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n
Simon Ruderich writes:
> On Tue, Aug 14, 2018 at 05:49:12PM +0200, Markus Armbruster wrote:
>>> On Fri, Aug 10, 2018 at 11:36:51AM +0100, Dr. David Alan Gilbert wrote:
> --- a/hmp-commands.hx
> +++ b/hmp-commands.hx
>>
>> Subject claims "qmp: add", but the patch also adds to hmp. Recomme
Peter Maydell writes:
> On 14 August 2018 at 18:44, Michele Denber <1785...@bugs.launchpad.net> wrote:
>> On 08-14-2018 4:42 AM, Peter Maydell wrote:
>>>
>>> We do assume a posix shell and that that shell is /bin/sh.
>>> We may have bugs where we assume non-posix behaviour
>>> from it, since almo
The counter is for qemu_lockcnt_inc/dec sections (read side),
qemu_lockcnt_lock/unlock is for the write side.
Suggested-by: Paolo Bonzini
Signed-off-by: Fam Zheng
Message-Id: <20180803063917.30292-1-f...@redhat.com>
Signed-off-by: Fam Zheng
---
util/aio-posix.c | 2 +-
1 file changed, 1 insert
The images are big. Add a rule to clean up easily.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Fam Zheng
Message-Id: <20180716020008.31468-1-f...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Fam Zheng
---
tests/vm/Makefile.include |
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Fam Zheng
Message-Id: <20180727083445.21436-1-f...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Fam Zheng
---
tests/vm/Makefile.include | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/v
An aio_notify() pairs with an aio_notify_accept(). The former should
happen in the main thread or a vCPU thread, and the latter should be
done in the IOThread.
There is one rare case that the main thread or vCPU thread may "steal"
the aio_notify() event just raised by itself, in bdrv_set_aio_conte
From: Peter Maydell
Use make's --output-sync option when running tests inside VMs,
so that if we're building with parallelization the output doesn't
get scrambled.
Signed-off-by: Peter Maydell
Message-Id: <20180803085230.30574-6-peter.mayd...@linaro.org>
Signed-off-by: Fam Zheng
---
tests/vm/
From: Paolo Bonzini
bdrv_io_plug/bdrv_io_unplug take care of keeping a nesting count,
so change s->plugged to just a bool.
Signed-off-by: Paolo Bonzini
Message-Id: <20180813144320.12382-2-pbonz...@redhat.com>
Signed-off-by: Fam Zheng
---
block/nvme.c | 20 ++--
1 file changed,
In VM based tests, the source archive is created in host, we don't have
to run archive-source.sh again, as it complicates the Makefile and
scripts.
Signed-off-by: Fam Zheng
Message-Id: <20180712012829.20231-4-f...@redhat.com>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Fam Zheng
---
tests
From: Peter Maydell
Currently we run the guests in a VM which is given only 2G of RAM.
Since the guests are configured without any swap space, builds
can fail because the system runs out of memory and kills the
compiler, especially if the job count is set for a lot of
parallelism. Bump the settin
The same logic exists in fd polling. This change is especially important
to avoid busy loop once we limit aio_notify_accept() to blocking
aio_poll().
Cc: qemu-sta...@nongnu.org
Signed-off-by: Fam Zheng
Message-Id: <20180809132259.18402-2-f...@redhat.com>
Signed-off-by: Fam Zheng
---
util/aio-po
From: Peter Maydell
Invoking 'make vm-build-freebsd' and friends with V=1 should
propagate that verbosity setting down into the build run
inside the VM. Make sure we do that. This brings it into
line with how the container tests handle V=1.
Signed-off-by: Peter Maydell
Message-Id: <201808030852
Not using snapshot has the benefit of automatically persisting useful
test harnesses, such as docker images and ccache database. Although it
will lose some cleanness, it is imaginably useful for patchew.
Signed-off-by: Fam Zheng
Message-Id: <20180712012829.20231-2-f...@redhat.com>
Tested-by: Phil
This makes test-block work.
Signed-off-by: Fam Zheng
Message-Id: <20180711065813.14894-1-f...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Fam Zheng
---
tests/docker/dockerfiles/centos7.docker | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/docker/dockerfiles/cen
This one does docker testing in the VM. It is intended to replace the
native docker testing on patchew testers.
Signed-off-by: Fam Zheng
Message-Id: <20180712012829.20231-5-f...@redhat.com>
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Fam Zheng
---
test
It is wrong to leave this field as 1, as nvme_close() called in the
error handling code in nvme_file_open() will use it and try to free
s->queues again.
Another problem is the cleaning ups are duplicated between the fail*
labels of nvme_init() and nvme_file_open(), which calls nvme_close().
A thi
From: Peter Maydell
Our test suite works for parallel execution too, and this can
noticeably speed up a test run; pass the 'jobs' setting to
it as well as to the build proper.
Signed-off-by: Peter Maydell
Message-Id: <20180803085230.30574-3-peter.mayd...@linaro.org>
Signed-off-by: Fam Zheng
--
From: Philippe Mathieu-Daudé
Similar to 79f24568e5e70, this fixes the following warnings:
CHK version_gen.h
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
BISON dtc-parser.tab.c
make[1]: bison: Command not found
LEX dtc-lexer.lex.c
From: Philippe Mathieu-Daudé
If KVM is not available, then use the 'max' cpu.
This fixes:
ERROR:root:Log:
ERROR:root:qemu-system-x86_64: CPU model 'host' requires KVM
Failed to prepare guest environment
error: [Errno 104] Connection reset by peer
source/qemu/tests/vm/Makefile.include:
The following changes since commit 38441756b70eec5807b5f60dad11a93a91199866:
Update version for v3.0.0 release (2018-08-14 16:38:43 +0100)
are available in the Git repository at:
git://github.com/famz/qemu.git tags/block-and-testing-pull-request
for you to fetch changes up to 37a81812f7b836
On Mon, 08/13 13:11, Emilio G. Cota wrote:
> + --enable-sync-profiler) sync_profiler="yes"
> + ;;
Curious, not asking for a change: can this be made a runtime option instead of
compile time, since there's no library dependencies? That should make this
somewhat easier to use.
> +
> +#define QSP_
On 2018年08月13日 20:31, Markus Armbruster wrote:
Thomas Huth writes:
When using the "-device" option, the property is called "mac".
"macaddr" is only used for the legacy "-net nic" option.
Indeed:
#define DEFINE_NIC_PROPERTIES(_state, _conf)\
--->DEFINE_
For feature parity with dd, we want to be able to specify
the offset within the output file, just as we can specify
the offset for the input (in particular, this makes copying
a subset range of guest-visible bytes from one file to
another much easier).
The code style for 'qemu-img dd' was pretty h
I was trying to test NBD fleecing by copying subsets of one
file to another, and had the idea to use:
$ export NBD drive to be fleeced on port 10809
$ qemu-img create -f qcow2 copy $size
$ qemu-nbd -f qcow2 -p 10810 copy
$ qemu-img dd -f raw -O raw if=nbd://localhost:10809 of=nbd://localhost:10810
When both skip= and count= are active, qemu-img dd was not copying
enough data. It didn't help that the code made the same check for
dd.flags & C_SKIP in two separate places. Compute 'size' as the
amount of bytes to be read, and 'end' as the offset to end at,
rather than trying to cram both meaning
On Linux, SOCK_DGRAM+IPPROTO_ICMP sockets give only the ICMP packet when
read from. On macOS, however, the socket acts like a SOCK_RAW socket
and includes the IP header as well.
This change strips the extra IP header from the received packet on macOS
before sending it to the guest. SOCK_DGRAM IC
Public bug reported:
I have noticed that guests using qxl-vga are freezing. They may freeze
after a few minutes or after many hours. The freeze consists of the
entire system hanging, except the cursor, but the cursor animation stops
too. Changing to tty is not possible after this. There are three
On Tue, Aug 14, 2018 at 10:43:47 +0100, Dr. David Alan Gilbert wrote:
> * Emilio G. Cota (c...@braap.org) wrote:
> > +@item info sync
>
> As long as this is just for devs I'm OK with this from the HMP side;
> however, if you want to automate the display or wire it to other
> tools then you should
On Tue, Aug 14, 2018 at 10:14:01 +0200, Paolo Bonzini wrote:
> On 13/08/2018 19:11, Emilio G. Cota wrote:
> Would it make sense to add a flag to sort by average wait time
Done:
(qemu) help info sync-profile
info sync-profile [-m] [max] -- show sync profiling info \
for up to max entries (default:
Here's a mystery. It looks like I finally have a clean compile - there
are no error messages but I don't see an executable. Is there supposed
to be something called "qemu" somewhere now? I looked in build/, the
top level, and /usr/local/bin/.
# gmake V=1
(cd /export/home/denber/qemu-2.12.0;
On Tue, Aug 14, 2018 at 10:13:12 +0200, Paolo Bonzini wrote:
> On 13/08/2018 19:11, Emilio G. Cota wrote:
> > +struct qsp_report rep;
>
> Don't like camelcase? But that's really all that I have to remark on
> this lovely series.
I have a strong aversion to it :-)
But if that's a deal breake
On Tue, Aug 14, 2018 at 08:26:54 +0200, Paolo Bonzini wrote:
> On 13/08/2018 18:38, Emilio G. Cota wrote:
> > Fix it by implementing the CPU list as an RCU QLIST. This requires
> > a little bit of extra work to insert CPUs at the tail of
> > the list and to iterate over the list in reverse order (s
On Fri, Jul 13, 2018 at 3:12 PM Marc-André Lureau
wrote:
>
> Hi,
>
> vhost-user allows to drive a virtio device in a seperate
> process. After vhost-user-net, we have seen
> vhost-user-{scsi,blk,crypto} added more recently.
>
> This series, initially proposed 2 years ago
> (https://lists.gnu.org/a
On 08/13/2018 12:00 PM, Dr. David Alan Gilbert wrote:
> cc'ing in Mike*2
> * Denis Plotnikov (dplotni...@virtuozzo.com) wrote:
>>
>>
>> On 26.07.2018 12:23, Peter Xu wrote:
>>> On Thu, Jul 26, 2018 at 10:51:33AM +0200, Paolo Bonzini wrote:
On 25/07/2018 22:04, Andrea Arcangeli wrote:
>
>>>
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of
the QEMU 3.0.0 release. This release contains 2300+ commits from 169
authors.
A note from the maintainer:
Why 3.0? Well, we felt that our version numbers were getting a bit
unwieldy, and since this year is QEMU's 15t
>
>
> > I notice in the Makefile in dtc/ that it's calling python. My default
> > python is 2.6.9. I found some discussion about qemu moving to python
> > 3. Could this be the problem?
>
> We require either Python 2.7.x, or Python 3.x versions. Support for
> 2.6.x was dropped I'm afraid.
>
>
Th
On 08-14-2018 2:17 PM, Peter Maydell wrote:
>
> dtc stuff really necessary?
> It is necessary, but only for certain guest CPU types. You can
> disable it by passing configure both "--disable-fdt" and also
> "--target-list= any arm, ppc, mips, microblaze or riscv targets>"
> (for instance "--targe
Em seg, 13 de ago de 2018 às 11:10, Kevin Wolf escreveu:
>
> Am 10.08.2018 um 06:07 hat Julio Faracco geschrieben:
> > This commit includes the support to lzfse opensource library. With this
> > library dmg block driver can decompress images with this type of
> > compression inside.
> >
> > Signed
Oh, and how I found this. From
http://lists.xymon.com/archive/2012-July/035109.html:
> Sorry to reply to myself. Looks like this line:
>
> uname -s | tr '[/]' '[_]'
>
> ...is not acceptable to /usr/bin/tr on Solaris 10. It worked fine
> on 9. On 10, one receives this error:
>
> # uname -s | tr
[Solved]
There's nothing like going public with a problem to find the answer
yourself shortly after. In case it helps someone else in the future, it
turns out that the Makefile in dtc/ contains the following line:
HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
sed -e 's/\(cygwin\
Debian console-setup uses /proc/hardware to guess the keyboard layout.
If the file /proc/hardware cannot be opened, the installation fails.
This patch adds a pseudo /proc/hardware file to report the model of
the machine. Instead of reporting a known and fake model, it
reports "qemu-m68k", which is
SPARC libc6 debian package wants to check the cpu level to be
installed or not:
WARNING: This machine has a SPARC V8 or earlier class processor.
Debian lenny and later does not support such old hardware
any longer.
To avoid this, it only needs to know if the machine type is sun4u or sun4v,
Le 09/08/2018 à 19:55, Alex Bennée a écrit :
> When debugging you often don't care about the libraries but just the
> code in the testcase. Rather than make the user build this by hand
> offer a shortcut.
>
> Signed-off-by: Alex Bennée
> ---
> linux-user/main.c | 16 +++-
> 1 file ch
Emilio G. Cota writes:
> On Tue, Aug 14, 2018 at 11:17:03 +0100, Alex Bennée wrote:
>> Emilio G. Cota writes:
>> > Would be great to get this in for 3.1.
>>
>> I would like this merged by 3.1 as well. However I think there is still
>> some work to be done on the testing side. IIRC the fptest c
Public bug reported:
While building qemu2.12.0 on a Sun Oracle Enterprise M3000 SPARC64 VII
running Solaris 10U11, opencsw toolchain, gcc 7.3.0, and python 3.3.6 I
get:
# gmake
mkdir -p dtc/libfdt
mkdir -p dtc/tests
Bad string
DEP /export/home/denber/qemu-2.12.0/dtc/tests/dumptrees.c
* Simon Ruderich (si...@ruderich.org) wrote:
> On Fri, Aug 10, 2018 at 11:36:51AM +0100, Dr. David Alan Gilbert wrote:
> >> --- a/hmp-commands.hx
> >> +++ b/hmp-commands.hx
> >> @@ -822,6 +822,20 @@ STEXI
> >> @item pmemsave @var{addr} @var{size} @var{file}
> >> @findex pmemsave
> >> save to dis
On 08/14/2018 11:41 AM, Paolo Bonzini wrote:
> Thomas has been doing a lot of work on qom-test and device-introspection-test,
> and Laurent has ported libqos to sPAPR and co-mentored Emanuele on the
> upcoming qtest device framework. They deserve recognition. :)
>
> Signed-off-by: Paolo Bonzin
On Tue, Aug 14, 2018 at 9:27 AM, Stefan Hajnoczi wrote:
> Image file loaders may add a series of roms. If an error occurs partway
> through loading there is no easy way to drop previously added roms.
>
> This patch adds a transaction mechanism that works like this:
>
> rom_transaction_begin();
The IMO, FMO and AMO bits in HCR_EL2 are defined to "behave as
1 for all purposes other than direct reads" if HCR_EL2.TGE
is set and HCR_EL2.E2H is 0, and to "behave as 0 for all
purposes other than direct reads" if HCR_EL2.TGE is set
and HRC_EL2.E2H is 1.
To avoid having to check E2H and TGE ever
On Tue, Aug 14, 2018 at 11:17:03 +0100, Alex Bennée wrote:
> Emilio G. Cota writes:
> > Would be great to get this in for 3.1.
>
> I would like this merged by 3.1 as well. However I think there is still
> some work to be done on the testing side. IIRC the fptest case works
> with whitelists and I
If the "trap general exceptions" bit HCR_EL2.TGE is set, we
must mask all virtual interrupts (as per DDI0487C.a D1.14.3).
Implement this in arm_excp_unmasked().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20180724115950.17316-2-peter.mayd...@linaro.org
---
target/arm
Public bug reported:
QEMU Version: 2.12.1, 3.0.0-rc4
Compiling with GCC 8.2.0
System: Plop Linux, 32 bit
Error:
CC disas/i386.o
/tmp/ccK8tHRs.s: Assembler messages:
/tmp/ccK8tHRs.s:53353: Error: can't resolve `L0' {*ABS* section} - `obuf'
{.bss section}
The problematic line is in 'dis
From: Adam Lackorzynski
Use an int64_t as a return type to restore
the negative check for arm_load_as.
Signed-off-by: Adam Lackorzynski
Message-id: 20180730173712.gg4...@os.inf.tu-dresden.de
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/boot.c | 8
1 file change
From: Richard Henderson
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Desnogues
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Alex Bennée
Tested-by: Laurent Desnogues
Message-id: 20180801123111.3595-5-richard.hender...@linaro
From: Luc Michel
Add support for GICv2 virtualization extensions by mapping the necessary
I/O regions and connecting the maintenance IRQ lines.
Declare those additions in the device tree and in the ACPI tables.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
Message-id: 20180727095421.38
From: Richard Henderson
Used the wrong temporary in the computation of subtractive overflow.
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Desnogues
Tested-by: Alex Bennée
Tested-by: Laurent Desnogues
Message-id: 20180801123111.3595-3-richard.hender...
From: Luc Michel
Add some traces to the ARM GIC to catch register accesses (distributor,
(v)cpu interface and virtual interface), and to take into account
virtualization extensions (print `vcpu` instead of `cpu` when needed).
Also add some virtualization extensions specific traces: LR updating
a
Improve the exception-taken logging by logging in
v7m_exception_taken() the exception we're going to take
and whether it is secure/nonsecure.
This requires us to move logging at many callsites from after the
call to before it, so that the logging appears in a sensible order.
(This will make tail-
Whene we raise a synchronous exception, if HCR_EL2.TGE is set then
exceptions targeting NS EL1 must be redirected to EL2. Implement
this in raise_exception() -- all synchronous exceptions go through
this function.
(Asynchronous exceptions go via arm_cpu_exec_interrupt(), which
already honours HCR
On Tue, Aug 14, 2018 at 05:49:12PM +0200, Markus Armbruster wrote:
>> On Fri, Aug 10, 2018 at 11:36:51AM +0100, Dr. David Alan Gilbert wrote:
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
>
> Subject claims "qmp: add", but the patch also adds to hmp. Recommend to
> split the patch into QMP
From: Luc Michel
This commit improve the way the GIC is realized and connected in the
ZynqMP SoC. The security extensions are enabled only if requested in the
machine state. The same goes for the virtualization extensions.
All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ,
vIR
From: Luc Michel
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off-by
From: Luc Michel
An access to the CPU interface is non-secure if the current GIC instance
implements the security extensions, and the memory access is actually
non-secure. Until then, it was checked with tests such as
if (s->security_extn && !attrs.secure) { ... }
in various places of the CPU i
On 14/08/2018 17:43, Thomas Huth wrote:
> On 08/14/2018 05:33 PM, Paolo Bonzini wrote:
>> On 14/08/2018 16:46, Thomas Huth wrote:
>>> When running qtests with -nodefaults, we are not interested in
>>> these 'XYZ has no peer' messages.
>>>
>>> Signed-off-by: Thomas Huth
>>> ---
>>> vl.c | 3 +--
>>
From: Luc Michel
Add the register definitions for the virtual interface of the GICv2.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
Message-id: 20180727095421.386-7-luc.mic...@greensocs.com
Signed-off-by: Peter Maydell
---
hw/intc/gic_internal.h | 65 ++
Tailchaining is an optimization in handling of exception return
for M-profile cores: if we are about to pop the exception stack
for an exception return, but there is a pending exception which
is higher priority than the priority we are returning to, then
instead of unstacking and then immediately t
From: Luc Michel
Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
Message-id: 20180727095421.386-14
From: Julia Suvorova
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suv
From: Richard Henderson
The pseudocode for this operation is an increment + compare loop,
so comparing <= the maximum integer produces an all-true predicate.
Rather than bound in both the inline code and the helper, pass the
helper the number of predicate bits to set instead of the number
of pre
On exception return for M-profile, we must restore the CONTROL.SPSEL
bit from the EXCRET value before we do any kind of tailchaining,
including for the derived exceptions on integrity check failures.
Otherwise we will give the guest an incorrect EXCRET.SPSEL value on
exception entry for the tailcha
From: Luc Michel
Implement virtualization extensions in gic_activate_irq() and
gic_drop_prio() and in gic_get_prio_from_apr_bits() called by
gic_drop_prio().
When the current CPU is a vCPU:
- Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt
counterparts,
- the vCPU APR i
From: Aleksandar Markovic
Synchronize content of linux-user/mips/syscall_nr.h and
linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers.
This adds 9 new syscall numbers, the last being NR_io_pgetevents.
Reviewed-by: Laurent Vivier
Reviewed-by: Richard Henderson
Signed-off-by: Aleksanda
From: Richard Henderson
The normal vector element is sign-extended before
comparing with the wide vector element.
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Desnogues
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Tested-by: Laurent Desnogues
Mess
In do_v7m_exception_exit(), we use the exc_secure variable to track
whether the exception we're returning from is secure or non-secure.
Unfortunately the statement initializing this was accidentally
inside an "if (env->v7m.exception != ARMV7M_EXCP_NMI)" conditional,
which meant that we were using t
From: Luc Michel
Implement virtualization extensions in the gic_acknowledge_irq()
function. This function changes the state of the highest priority IRQ
from pending to active.
When the current CPU is a vCPU, modifying the state of an IRQ modifies
the corresponding LR entry. However if we clear t
One of the required effects of setting HCR_EL2.TGE is that when
SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for
all purposes except direct reads. That is, it effectively disables
the MMU for the NS EL0/EL1 translation regime.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hen
From: Aleksandar Markovic
Remove duplicate preprocessor constant definition for EF_MIPS_ARCH.
The duplicate was introduced in commit 45506bdd. It placed the
constant EF_MIPS_ARCH in a better place, however it did not remove
the original. This patch removes the original occurrence.
Reviewed-by:
Some debug registers can be trapped via MDCR_EL2 bits TDRA, TDOSA,
and TDA, which we implement in the functions access_tdra(),
access_tdosa() and access_tda(). If MDCR_EL2.TDE or HCR_EL2.TGE
are 1, the TDRA, TDOSA and TDA bits should behave as if they were 1.
Implement this by having the access fun
From: Luc Michel
Add some helper macros and functions related to the virtualization
extensions to gic_internal.h.
The GICH_LR_* macros help extracting specific fields of a list register
value. The only tricky one is the priority field as only the MSB are
stored. The value must be shifted accordi
From: Yongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.c| 4 +++-
target/mips/op_helper.c | 12
From: Luc Michel
Add the gic_update_virt() function to update the vCPU interface states
and raise vIRQ and vFIQ as needed. This commit renames gic_update() to
gic_update_internal() and generalizes it to handle both cases, with a
`virt' parameter to track whether we are updating the CPU or vCPU
in
From: Luc Michel
Add some helper functions to gic_internal.h to get or change the state
of an IRQ. When the current CPU is not a vCPU, the call is forwarded to
the GIC distributor. Otherwise, it acts on the list register matching
the IRQ in the current CPU virtual interface.
gic_clear_active can
From: Luc Michel
Add the necessary parts of the virtualization extensions state to the
GIC state. We choose to increase the size of the CPU interfaces state to
add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way,
we'll be able to reuse most of the CPU interface code for the vCPU
From: Luc Michel
Implement the read and write functions for the virtual interface of the
virtualization extensions in the GICv2.
One mirror region per CPU is also created, which maps to that specific
CPU id. This is required by the GIC architecture specification.
Signed-off-by: Luc Michel
Revi
From: Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
From: Luc Michel
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
Message-id: 20180727095421.386-3-luc.mic...@greensocs.com
Signed-off-
From: Luc Michel
Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
a VMState.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20180727095421.386-5-luc.mic...@greensocs.com
Signed-off-by: Peter Maydell
---
include/mi
From: Stefan Markovic
Add testing Config1.WR bit into watch exception handling logic.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/mips/transla
From: Luc Michel
Add the read/write functions to handle accesses to the vCPU interface.
Those accesses are forwarded to the real CPU interface, with the CPU id
being converted to the corresponding vCPU id (vCPU id = CPU id +
GIC_NCPU).
Signed-off-by: Luc Michel
Message-id: 20180727095421.386-15
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