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https://bugs.launchpad.net/bugs/1775702
Title:
High host CPU load and slower guest after upgrade guest OS Windows 10
to ver 1803
Status in QEMU:
New
Bug descr
On 07/30/2018 08:32 AM, Markus Armbruster wrote:
> Eric Blake writes:
>
>> On 07/27/2018 11:46 AM, Thomas Huth wrote:
>>> On 07/27/2018 05:13 PM, Markus Armbruster wrote:
qtest_qmp_discard_response(...) is shorthand for
qobject_unref(qtest_qmp(...), except it's not actually shorter.
>>>
On Tue, Jul 31, 2018 at 07:39:45PM +0200, Greg Kurz wrote:
> On Mon, 30 Jul 2018 16:11:32 +0200
> Cédric Le Goater wrote:
>
> > This proposal introduces a new IRQ number space layout using static
> > numbers for all devices, depending on a device index, and a bitmap
> > allocator for the MSI IRQ
Hello,
On Tue, Jul 31, 2018 at 6:36 PM, Richard Henderson
wrote:
> On 07/31/2018 09:52 AM, Laurent Desnogues wrote:
>> Hello Richard,
>>
>> according to SVE specification, whilels/whilele instructions have a
>> special case where if the second operand is the maximum (un)signed
>> integer then the
On Mon, Jul 30, 2018 at 05:09:17PM +, Yasmin Beatriz wrote:
> After solving a corner case in bcdsub, this patch simplifies the logic
> of both bcdadd/sub instructions by removing some unnecessary local flags.
> This commit also rearranges some if-else conditions in bcdadd to make it
> easier to
On Mon, Jul 30, 2018 at 04:11:31PM +0200, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Applied to ppc-for-3.1, thanks.
> ---
> include/hw/compat.h | 3 +++
> hw/ppc/spapr.c | 23 +--
> 2 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/inc
On Tue, Jul 31, 2018 at 12:56:49PM +0200, Greg Kurz wrote:
> The last user of the PowerPCCPU typedef in "hw/ppc/xics.h" vanished with
> commit b1fd36c363d73969841468146ebfb9fd84a5ee52. It isn't necessary to
> include "target/ppc/cpu-qom.h" there anymore.
>
> Signed-off-by: Greg Kurz
Applied to p
From: BALATON Zoltan
The four interrupts of the PCI bus are connected to the same UIC pin
on the real Sam460ex. Evidence for this can be found in the UBoot
source for the Sam460ex in the Sam460ex.c file where
PCI_INTERRUPT_LINE is written. Change the ppc440_pcix model to behave
more like this.
T
From: Thomas Huth
Valgrind reports an error when introspecting the macio devices, e.g.:
echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \
"'arguments':{'typename':'macio-newworld'}}" \
"{'execute': 'human-monitor-command', " \
"'arguments': {'command-line': 'info qt
The following changes since commit f7502360397d291be04bc040e9f96c92ff2d8030:
Update version for v3.0.0-rc3 release (2018-07-31 19:30:17 +0100)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-3.0-20180801
for you to fetch changes up to 6484ab3dffadc7902
On Tue, Jul 31, 2018 at 11:55:02PM +0200, Sebastian Bauer wrote:
> Am 2018-07-31 13:08, schrieb BALATON Zoltan:
> > The four interrupts of the PCI bus are connected to the same UIC pin
> > on the real Sam460ex. Evidence for this can be found in the UBoot
> > source for the Sam460ex in the Sam460ex.
On Sat, 7 Jul 2018, Fredrik Noring wrote:
> The MIPS R5900 is normally taken to be MIPS3, but it has MOVN, MOVZ and PREF
> defined in MIPS4 which is why ISA_MIPS4 is chosen for this patch.
It also has several instructions removed, so I don't think you can really
just mark it MIPS IV without spe
On Tue, 07/31 15:28, Guenter Roeck wrote:
> mptsas1068 is currently listed as uncategorized device.
> Mark it as storage device.
>
> Signed-off-by: Guenter Roeck
> ---
> hw/scsi/mptsas.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c
> index 4176e87
2018-07-31 23:50 GMT+08:00 Daniel P. Berrangé :
> On Tue, Jul 31, 2018 at 04:48:35PM +0200, Juan Quintela wrote:
> > "Dr. David Alan Gilbert" wrote:
> > > * Li Qiang (liq...@gmail.com) wrote:
> > >> The default max cpu throttle is 99, this is too big that may
> > >> influence the guest loads. Add
On Tue, Jul 31, 2018 at 6:22 AM Peter Maydell
wrote:
> On 31 July 2018 at 02:16, Andrew Oates wrote:
> > Yeah, I suspect (but haven't tested) that this applies to all BSDs. We
> > could switch CONFIG_DARWIN to CONFIG_BSD (happy to resend the patch, just
> > LMK).
> >
> > Agreed that platform-sp
Alex, Laurent, I'm new to this management/development system. So, first
off, thanks for working on this bug.
I have a few (probably silly) questions:
1. What is 'the r-b' that Alex used in #14?
2. When should I change the status of the bug? I can already see it in GitHub's
mirror and in https://
sd-card is currently listed as uncategorized device.
Mark it as storage device.
Signed-off-by: Guenter Roeck
---
hw/sd/sd.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index d4356e9..aaab15f 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -2121,6 +2121,7 @@ static voi
mptsas1068 is currently listed as uncategorized device.
Mark it as storage device.
Signed-off-by: Guenter Roeck
---
hw/scsi/mptsas.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c
index 4176e87..929404f 100644
--- a/hw/scsi/mptsas.c
+++ b/hw/scsi/mptsas.c
Am 2018-07-31 13:08, schrieb BALATON Zoltan:
The four interrupts of the PCI bus are connected to the same UIC pin
on the real Sam460ex. Evidence for this can be found in the UBoot
source for the Sam460ex in the Sam460ex.c file where
PCI_INTERRUPT_LINE is written. Change the ppc440_pcix model to b
On Tue, 31 Jul 2018 16:07:46 +0100
"Dr. David Alan Gilbert" wrote:
> * Alex Williamson (alex.william...@redhat.com) wrote:
> > On Tue, 31 Jul 2018 15:29:17 +0300
> > "Michael S. Tsirkin" wrote:
> >
> > > On Mon, Jul 30, 2018 at 05:13:26PM -0600, Alex Williamson wrote:
> > > > v2:
> > > > -
The current emulation will clear the XCH bit when a burst finishes.
This is not quite correct. According to the i.MX7d referemce manual,
Rev 0.1, §10.1.7.3:
This bit [XCH] is cleared automatically when all data in the TXFIFO
and the shift register has been shifted out.
So XCH should be c
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180730134321.19898-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [PATCH v2 for 3.0 0/2] fix for bug #1783362
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(g
On Tue, Jul 31, 2018 at 11:18:02AM +0200, Niels de Vos wrote:
> On Mon, Jul 30, 2018 at 03:27:29PM -0400, Jeff Cody wrote:
> > On Mon, Jul 30, 2018 at 10:07:27AM -0500, Eric Blake wrote:
> > > On 07/28/2018 02:50 AM, Niels de Vos wrote:
> > > >>
> > > >>Part of me wishes that libgfapi had just crea
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 3.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-3.0.0-rc3.tar.xz
http://down
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> v4->v5:
>
> - merged series "Mips maintenance and misc fixes and improvements"
> and this one for easier handling (there are build dependencies)
> - eliminated shadow variables from translate.c
> - repla
On 07/31/2018 02:58 PM, Richard Henderson wrote:
> On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
>> +switch (extract32(ctx->opcode, 12, 1)) {
>> +case 0:
>> +/* NM_SHRA_QB */
>> +check_dspr2(ctx);
>> +gen_helper_shra_qb(cpu_gpr[ret], t0, v1_t
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
> index 084ad6a..1d3dc9e 100644
> --- a/linux-user/mips/cpu_loop.c
> +++ b/linux-user/mips/cpu_loop.c
> @@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env)
>
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: James Hogan
>
> nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit
> of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being
> read as e.g. 0xbfc1, and prevents writing to the PC clearing
> MIPS_HF
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index c55a1e6..e6749c5 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -2430,6 +2430,13 @@ static void set_pc(CPUMIPSState *env, target_ulong
> error_pc
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: James Hogan
>
> We shouldn't clear M16 mode when entering an interrupt on nanoMIPS,
> otherwise we'll start interpreting the code as normal MIPS code.
Likewise re nanomips not setting M16.
r~
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: James Hogan
>
> ERET and ERETNC shouldn't clear MIPS_HFLAG_M16 for nanoMIPS since there
> is no ISA bit, so fix set_pc() to skip the hflags update.
>
> Signed-off-by: James Hogan
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> -isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
> +isa_mode = env->hflags & MIPS_HFLAG_M16 &&
> +!(env->insn_flags & ISA_NANOMIPS32);
Likewise re nanomips not setting M16.
r~
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Config3.ISAOnExc is read only in nanoMIPS.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/op_helper.c | 3 ++-
> 1 file changed, 2 insertions(+
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: Stefan Markovic
>
> Add testing Config0.WR bit into watch exception handling logic.
>
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/helper.c| 12 +++-
> target/mips/translate.c |
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
> +(env->hflags & MIPS_HFLAG_BMASK)) {
> +if (!(env->hflags & MIPS_HFLAG_B16)) {
> +env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC -
> 4);
> +
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Aleksandar Rikalo
>
> Add ability to target platforms to individually include user-mode
> support for system calls from "stat" group of system calls.
>
> This change is related to new nanoMIPS platform in the sense that
> it supports a d
On 07/31/2018 07:03 PM, Michael S. Tsirkin wrote:
On Tue, Jul 31, 2018 at 10:58:37AM -0500, Venu Busireddy wrote:
On 2018-07-07 15:14:11 +0300, Marcel Apfelbaum wrote:
Hi Venu,
On 06/30/2018 01:19 AM, Venu Busireddy wrote:
Add a new bridge device "pcie-downstream" with a
Vendor ID of PCI_V
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> -int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
> +int lowbit = ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M16);
I believe I asked why M16 is set for nanoMIPS at all.
You go out of your way to ignore it in lots of places,
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +switch (extract32(ctx->opcode, 12, 1)) {
> +case 0:
> +/* NM_SHRA_QB */
> +check_dspr2(ctx);
> +gen_helper_shra_qb(cpu_gpr[ret], t0, v1_t);
More unprotected use of cpu_gpr[0].
I think you need
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
> + int ret, int v1, int v2)
> +{
> +TCGv t0;
> +TCGv v0_t;
> +TCGv v1_t;
> +
> +t0 = tcg_temp_new();
> +
> +
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
+static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
> + int ret, int v1, int v2)
> +{
> +TCGv t0;
> +TCGv t1;
> +
> +TCGv v0_t;
> +TCGv v1_t;
> +
> +t0 = tcg_temp
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: Stefan Markovic
>
> Add emulation of DSP ASE instructions for nanoMIPS - part 3.
>
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c | 180
>
On 07/31/2018 01:00 PM, Richard W.M. Jones wrote:
Hi Eric. Is this a bug?
$ nbdkit -fv random size=1023
(You can choose any size which is not a multiple of 512.)
$ qemu-img convert nbd:localhost:10809 /var/tmp/test
qemu-img: error while reading sector 0: Invalid argument
Or more d
On Mon, 30 Jul 2018 16:11:32 +0200
Cédric Le Goater wrote:
> This proposal introduces a new IRQ number space layout using static
> numbers for all devices, depending on a device index, and a bitmap
> allocator for the MSI IRQ numbers which are negotiated by the guest at
> runtime.
>
> As the VIO
On 31 July 2018 at 16:51, Markus Armbruster wrote:
> The following changes since commit 42e76456cf68dc828b8dbd3c7e255197e9b5e57d:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging
> (2018-07-31 13:52:03 +0100)
>
> are available in the Git re
Add test, which starts backup to nbd target and restarts nbd server
during backup.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/220| 67 +++
tests/qemu-iotests/220.out| 7 +
tests/qemu-iotests/group | 1 +
tests
Keep all connection code in one file, to be able to implement reconnect
in further patches.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/nbd-client.h | 2 +-
block/nbd-client.c | 37 +++--
block/nbd.c| 40 ++--
To implement reconnect we need several states for the client:
CONNECTED, QUIT and two CONNECTING states. CONNECTING states will
be realized in the following patches. This patch implements CONNECTED
and QUIT.
QUIT means, that we should close the connection and fail all current
and further requests
To implement nbd reconnect in further patches, we need to distinguish
error codes, returned by nbd server, from channel errors, to reconnect
only in the latter case.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
---
block/nbd-client.c | 83 +++--
This coroutine will serve nbd reconnects, so, rename it to be something
more generic.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/nbd-client.h | 4 ++--
block/nbd-client.c | 24
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/block/nbd-client.
Split connection code to reuse it for reconnect.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/nbd-client.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/block/nbd-client.c b/block/nbd-client.c
index a0d8f2523e..a1813cbfe1 100644
-
Use exported report, not the variable to be reused (should not really
matter).
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/nbd-client.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/nbd-client.c b/block/nbd-client.c
index a1813cbfe1..263d1721f9 100644
--- a/
Reconnect will be implemented in the following commit, so for now,
in semantics below, disconnect itself is a "serious error".
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
qapi/block-core.json | 12 +++-
block/nbd-client.h | 1 +
block/nbd-client.c | 1 +
block/nbd.c |
Hi all.
Here is NBD reconnect. Previously, if connection failed all current
and future requests will fail. After the series, nbd-client driver
will try to reconnect unlimited times. During first @reconnect-delay
seconds of reconnecting all requests will wait for the connection,
and if it is establ
Implement reconnect. To achieve this:
1. add new modes:
connecting-wait: means, that reconnecting is in progress, and there
were small number of reconnect attempts, so all requests are
waiting for the connection.
connecting-nowait: reconnecting is in progress, there were a lot of
We have several paranoiac checks for ioc != NULL. But ioc may become
NULL only on close, which should not happen during requests handling.
Also, we check ioc only sometimes, not after each yield, which is
inconsistent. Let's drop these checks. However, for safety, lets leave
asserts instead.
Signe
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +case NM_BPOSGE32C:
> +check_dsp(ctx);
> +{
> +int32_t imm = ctx->opcode;
> +imm >>= 1;
> +imm &= 0x1fff;
> +
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +case OPC_CMPGU_EQ_QB:
> +check_dsp(ctx);
> +gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t);
> +break;
Missing a test for ret == 0, here and many other places.
I believe some (many?) of these have side-effects, so y
On 25 July 2018 at 09:59, Stefan Hajnoczi wrote:
> Some ARM CPUs have bitbanded IO, a memory region that allows convenient
> bit access via 32-bit memory loads/stores. This eliminates the need for
> read-modify-update instruction sequences.
>
> This patch makes this optional feature a ARMMProfile
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +/* Immediate Value Compact Branches */
> +static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
> + int rt, int32_t imm, int32_t offset)
> +{
> +TCGCond cond;
> +int bcond_compute = 0;
> +
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> case NM_P_GP_BH:
> +{
> +uint32_t u = extract32(ctx->opcode, 0, 18);
> +switch (extract32(ctx->opcode, 18, 3)) {
> +case NM_LBGP:
> +gen_ld(ctx, OPC_LB, rt, 28, u);
> +
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
> +{
> +TCGv t0, t1;
> +t0 = tcg_temp_new();
> +t1 = tcg_temp_new();
> +
> +gen_load_gpr(t0, rs);
> +gen_load_gpr(t1, rt);
> +
> +if ((extract32(ctx->opcode
On Wed 04 Jul 2018 04:54:10 PM CEST, Stefan Hajnoczi wrote:
> Throttle groups consist of members sharing one throttling state
> (including bps/iops limits). Round-robin scheduling is used to ensure
> fairness. If a group member already has a timer pending then other
> groups members do not schedu
On 07/30/2018 10:18 AM, Ulrich Hecht wrote:>> On July 30, 2018 at 3:02 PM Geert
Uytterhoeven wrote:
>> Fix this by adding basic timeout handling. As the QEMU SCIF emulation
>> ignores any serial speed programming, the timeout value used conforms to
>> a default speed of 9600 bps, which is fine fo
On 07/31/2018 09:52 AM, Laurent Desnogues wrote:
> Hello Richard,
>
> according to SVE specification, whilels/whilele instructions have a
> special case where if the second operand is the maximum (un)signed
> integer then the result is an all-true predicate. The current code in
> trans_WHILE does
Eric Blake writes:
> On 07/31/2018 10:01 AM, Marc-André Lureau wrote:
>> With a Spice port chardev, it is possible to reenter
>> monitor_qapi_event_queue() (when the client disconnects for
>> example). This will dead-lock on monitor_lock.
>>
>> Instead, use some TLS variables to check for recursi
Hi
On Tue, Jul 31, 2018 at 6:03 PM, Eric Blake wrote:
> On 07/31/2018 10:01 AM, Marc-André Lureau wrote:
>>
>> With a Spice port chardev, it is possible to reenter
>> monitor_qapi_event_queue() (when the client disconnects for
>> example). This will dead-lock on monitor_lock.
>>
>> Instead, use s
On Tue, Jul 31, 2018 at 10:58:37AM -0500, Venu Busireddy wrote:
> On 2018-07-07 15:14:11 +0300, Marcel Apfelbaum wrote:
> > Hi Venu,
> >
> > On 06/30/2018 01:19 AM, Venu Busireddy wrote:
> > > Add a new bridge device "pcie-downstream" with a
> > > Vendor ID of PCI_VENDOR_ID_REDHAT and a Device ID
On 07/31/2018 10:01 AM, Marc-André Lureau wrote:
With a Spice port chardev, it is possible to reenter
monitor_qapi_event_queue() (when the client disconnects for
example). This will dead-lock on monitor_lock.
Instead, use some TLS variables to check for recursion and queue the
events.
diff
On 2018-07-07 15:14:11 +0300, Marcel Apfelbaum wrote:
> Hi Venu,
>
> On 06/30/2018 01:19 AM, Venu Busireddy wrote:
> > Add a new bridge device "pcie-downstream" with a
> > Vendor ID of PCI_VENDOR_ID_REDHAT and a Device ID of
> > PCI_DEVICE_ID_REDHAT_DOWNPORT_FAILOVER.
>
> Can't we use the current
The following changes since commit 42e76456cf68dc828b8dbd3c7e255197e9b5e57d:
Merge remote-tracking branch
'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-07-31
13:52:03 +0100)
are available in the Git repository at:
git://repo.or.cz/qemu/armbru.git tags/pull-monit
From: Marc-André Lureau
With a Spice port chardev, it is possible to reenter
monitor_qapi_event_queue() (when the client disconnects for
example). This will dead-lock on monitor_lock.
Instead, use some TLS variables to check for recursion and queue the
events.
Fixes:
(gdb) bt
#0 0x7fa69e
On Tue, Jul 31, 2018 at 04:48:35PM +0200, Juan Quintela wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Li Qiang (liq...@gmail.com) wrote:
> >> The default max cpu throttle is 99, this is too big that may
> >> influence the guest loads. Add a qmp to config it can make it
> >> more flexible.
> >>
>
On Fri, Jul 27, 2018 at 04:06:23PM +0300, Michael S. Tsirkin wrote:
> On Fri, Jul 27, 2018 at 01:49:17PM +0100, Stefan Hajnoczi wrote:
> > On Wed, Jul 18, 2018 at 03:47:56PM +0800, junyan...@gmx.com wrote:
> > > From: Junyan He
> > >
> > > QEMU writes to vNVDIMM backends in the vNVDIMM label emul
Marc-André Lureau writes:
> Hi
>
> On Tue, Jul 31, 2018 at 1:30 PM, Markus Armbruster wrote:
>> Marc-André Lureau writes:
>>
>>> A chardev may stop trying to write if the associated can_read()
>>> callback returned 0. This happens when the monitor is suspended.
>>> The frontend is supposed to c
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Li Qiang (liq...@gmail.com) wrote:
> >> The default max cpu throttle is 99, this is too big that may
> >> influence the guest loads. Add a qmp to config it can make it
> >> more flexible.
> >>
> >> Signed-off-by:
On Tue, Jul 31, 2018 at 5:25 PM, Markus Armbruster wrote:
> Marc-André Lureau writes:
>
>> With a Spice port chardev, it is possible to reenter
>> monitor_qapi_event_queue() (when the client disconnects for
>> example). This will dead-lock on monitor_lock.
>>
>> Instead, use some TLS variables to
Marc-André Lureau writes:
> With a Spice port chardev, it is possible to reenter
> monitor_qapi_event_queue() (when the client disconnects for
> example). This will dead-lock on monitor_lock.
>
> Instead, use some TLS variables to check for recursion and queue the
> events.
>
> Fixes:
> (gdb) bt
Marc-André Lureau writes:
> Hi
>
> On Tue, Jul 31, 2018 at 9:05 AM, Markus Armbruster wrote:
>> Marc-André Lureau writes:
>>
>>> With a Spice port chardev, it is possible to reenter
>>> monitor_qapi_event_queue() (when the client disconnects for
>>> example). This will dead-lock on monitor_lock
* Alex Williamson (alex.william...@redhat.com) wrote:
> On Tue, 31 Jul 2018 15:29:17 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Mon, Jul 30, 2018 at 05:13:26PM -0600, Alex Williamson wrote:
> > > v2:
> > > - Use atomic ops for balloon inhibit counter (Peter)
> > > - Allow endpoint driver opt-
On Tue, Jul 31, 2018 at 11:53:40AM +0200, Igor Mammedov wrote:
> On Mon, 30 Jul 2018 17:26:24 -0300
> Eduardo Habkost wrote:
>
> > On Mon, Jul 30, 2018 at 11:41:41AM +0200, Igor Mammedov wrote:
> > > Commit 848a1cc1e (hw/acpi-build: build SRAT memory affinity structures
> > > for DIMM devices)
>
With a Spice port chardev, it is possible to reenter
monitor_qapi_event_queue() (when the client disconnects for
example). This will dead-lock on monitor_lock.
Instead, use some TLS variables to check for recursion and queue the
events.
Fixes:
(gdb) bt
#0 0x7fa69e7217fd in __lll_lock_wait
"Dr. David Alan Gilbert" wrote:
> * Li Qiang (liq...@gmail.com) wrote:
>> The default max cpu throttle is 99, this is too big that may
>> influence the guest loads. Add a qmp to config it can make it
>> more flexible.
>>
>> Signed-off-by: Li Qiang
>
> This should be done as a migration parameter
Hi
On Tue, Jul 31, 2018 at 9:05 AM, Markus Armbruster wrote:
> Marc-André Lureau writes:
>
>> With a Spice port chardev, it is possible to reenter
>> monitor_qapi_event_queue() (when the client disconnects for
>> example). This will dead-lock on monitor_lock.
>>
>> Instead, use some TLS variable
On Tue, 31 Jul 2018 15:29:17 +0300
"Michael S. Tsirkin" wrote:
> On Mon, Jul 30, 2018 at 05:13:26PM -0600, Alex Williamson wrote:
> > v2:
> > - Use atomic ops for balloon inhibit counter (Peter)
> > - Allow endpoint driver opt-in for ballooning, vfio-ccw opt-in by
> >default, vfio-pci opt-i
Wei Wang wrote:
> When "nbits = 0", which means no bits to mask, this macro is expected to
> return 0, instead of 0x. This patch changes the macro to return
> 0 when there is no bit needs to be masked.
>
> Signed-off-by: Wei Wang
> CC: Juan Quintela
> CC: Dr. David Alan Gilbert
> CC: Pe
Eric Blake wrote:
>> +++ b/qapi/migration.json
>> @@ -6,6 +6,7 @@
>> ##
>> { 'include': 'common.json' }
>> +{ 'include': 'sockets.json' }
>> ##
>> # @MigrationStats:
>> @@ -169,6 +170,7 @@
>> # only present when the postcopy-blocktime migration capability
>> #
On 07/31/2018 06:36 AM, Sebastian Bauer wrote:
> This can be done by using the newly introduced num_irqs property. In
> particular, this change introduces a special case if num_irqs is 1 in which
> case any interrupt pin will be connected to the single irq. The default
> case is untouched (but note
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +case NM_SOV:
> +{
> +TCGv t0 = tcg_temp_local_new();
tcg_temp_new.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 31 July 2018 at 09:42, Laurent Vivier wrote:
> The following changes since commit 6d9dd5fb9d0e9f4a174f53a0e20a39fbe809c71e:
>
> Merge remote-tracking branch
> 'remotes/armbru/tags/pull-qobject-2018-07-27-v2' into staging (2018-07-30
> 09:55:47 +0100)
>
> are available in the Git repository
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> case NM_P48I:
> -return 6;
> +{
> +insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
> +uint32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
This value is supposed to be signed.
r~
On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c | 33 ++
Hello Richard,
according to SVE specification, whilels/whilele instructions have a
special case where if the second operand is the maximum (un)signed
integer then the result is an all-true predicate. The current code in
trans_WHILE doesn't seem to capture that requirement. I'm afraid the
fix won
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> +case NM_ADDIUPC:
> +if (rt != 0) {
> +int32_t offset = sextract32(ctx->opcode, 0, 1) << 21 |
> + extract32(ctx->opcode, 1, 20) << 1;
> +target_long addr = addr_add(ctx, ctx->base.pc
On Wed 04 Jul 2018 04:54:10 PM CEST, Stefan Hajnoczi wrote:
> Throttle groups consist of members sharing one throttling state
> (including bps/iops limits). Round-robin scheduling is used to ensure
> fairness. If a group member already has a timer pending then other
> groups members do not schedu
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180730192955.14291-1-programmingk...@gmail.com
Subject: [Qemu-devel] [PATCH] Add interac
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> +static void gen_adjust_sp(DisasContext *ctx, int u)
> +{
> +TCGv tsp = tcg_temp_new();
> +gen_base_offset_addr(ctx, tsp, 29, u);
> +gen_store_gpr(tsp, 29);
> +tcg_temp_free(tsp);
> +}
This could now be just
gen_op_addr_addi(c
Laurent Vivier writes:
> Le 31/07/2018 à 14:24, no-re...@patchew.org a écrit:
>> Hi,
>>
>> This series seems to have some coding style problems. See output below for
>> more information:
>>
>> Type: series
>> Message-id: 20180731084203.29959-1-laur...@vivier.eu
>> Subject: [Qemu-devel] [PULL 0/
On 07/30/2018 12:11 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Add emulation of NOT16, AND16, XOR16, OR16 instructions.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/trans
On 31.07.2018 15:06, Cornelia Huck wrote:
> On Tue, 31 Jul 2018 13:09:08 +0100
> Janosch Frank wrote:
>
>> QEMU has had huge page support for a longer time already, but KVM
>> memory management under s390x needed some changes to work with huge
>> backings.
>>
>> Now that we have support, let's en
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