On Fri, Jun 22, 2018 at 4:22 AM, Shimi Gersner wrote:
> PCI/e configuration currently does not meets specifications.
>
> Patch includes various configuration changes to support specifications
> - BAR2 to return zero when read and CMD.IOSE is not set.
> - Expose NVME configuration through IO space
Hi Peter,
On 07/13/2018 12:09 PM, Peter Maydell wrote:
> We set up TLB entries in tlb_set_page_with_attrs(), where we have
> some logic for determining whether the TLB entry is considered
> to be RAM-backed, and thus has a valid addend field. When we
> look at the TLB entry in get_page_addr_code()
On 07/14/2018 02:35 PM, Laurent Vivier wrote:
> The value given by mmap_find_vma_reserved() is used with mmap(),
> so it is needed to be aligned with the host page size.
>
> Since commit 18e80c55bb, reserved_va is only aligned to TARGET_PAGE_SIZE,
> and it works well if this size is greater or equ
On 07/13/2018 10:09 AM, Peter Maydell wrote:
> @@ -939,29 +935,21 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env,
> target_ulong addr)
> }
> assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
> }
> +assert(tlb_hit(env->tlb_table[mmu_idx][index].addr
The value given by mmap_find_vma_reserved() is used with mmap(),
so it is needed to be aligned with the host page size.
Since commit 18e80c55bb, reserved_va is only aligned to TARGET_PAGE_SIZE,
and it works well if this size is greater or equal to the host page size.
But ppc64 hosts have 64kB pag
On Sat, Jul 14, 2018 at 07:16:00PM +0200, Luc Michel wrote:
> This commit improve the way the GIC is realized and connected in the
> ZynqMP SoC. The security extensions are enabled only if requested in the
> machine state. The same goes for the virtualization extensions.
>
> All the GIC to APU CPU
Add the gic_update_virt() function to update the vCPU interface states
and raise vIRQ and vFIQ as needed. This commit renames gic_update() to
gic_update_internal() and generalizes it to handle both cases, with a
`virt' parameter to track whether we are updating the CPU or vCPU
interfaces.
The main
Add the necessary parts of the virtualization extensions state to the
GIC state. We choose to increase the size of the CPU interfaces state to
add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way,
we'll be able to reuse most of the CPU interface code for the vCPUs.
The only except
Implement the read and write functions for the virtual interface of the
virtualization extensions in the GICv2.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 235 +-
1 file changed, 233 insertions(+), 2 deletions(-)
dif
This commit improve the way the GIC is realized and connected in the
ZynqMP SoC. The security extensions are enabled only if requested in the
machine state. The same goes for the virtualization extensions.
All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ,
vIRQ and vFIQ. The mis
Add the read/write functions to handle accesses to the vCPU interface.
Those accesses are forwarded to the real CPU interface, with the CPU id
being converted to the corresponding vCPU id (vCPU id = CPU id +
GIC_NCPU).
As for the CPU interface, we create a base region for the vCPU interface
that f
Add some helper functions to gic_internal.h to get or change the state
of an IRQ. When the current CPU is not a vCPU, the call is forwarded to
the GIC distributor. Otherwise, it acts on the list register matching
the IRQ in the current CPU virtual interface.
gic_clear_active can have a side effect
Add some traces to the ARM GIC to catch register accesses (distributor,
(v)cpu interface and virtual interface), and to take into account
virtualization extensions (print `vcpu` instead of `cpu` when needed).
Also add some virtualization extensions specific traces: LR updating
and maintenance IRQ
Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 20 +++-
1
Add support for GICv2 virtualization extensions by mapping the necessary
I/O regions and connecting the maintenance IRQ lines.
Declare those additions in the device tree and in the ACPI tables.
Signed-off-by: Luc Michel
---
hw/arm/virt-acpi-build.c | 6 +++--
hw/arm/virt.c| 52
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off-by: Luc Michel
Revie
Add some helper macros and functions related to the virtualization
extensions to gic_internal.h.
The GICH_LR_* macros help extracting specific fields of a list register
value. The only tricky one is the priority field as only the MSB are
stored. The value must be shifted accordingly to obtain the
Implement virtualization extensions in the gic_acknowledge_irq()
function. This function changes the state of the highest priority IRQ
from pending to active.
When the current CPU is a vCPU, modifying the state of an IRQ modifies
the corresponding LR entry. However if we clear the pending flag bef
Implement the maintenance interrupt generation that is part of the GICv2
virtualization extensions.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 97 +++
1 file changed, 97 insertions(+)
diff --git a/hw/intc/arm_gic.c b
An access to the CPU interface is non-secure if the current GIC instance
implements the security extensions, and the memory access is actually
non-secure. Until then, it was checked with tests such as
if (s->security_extn && !attrs.secure) { ... }
in various places of the CPU interface code.
Wit
Implement virtualization extensions in gic_activate_irq() and
gic_drop_prio() and in gic_get_prio_from_apr_bits() called by
gic_drop_prio().
When the current CPU is a vCPU:
- Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt
counterparts,
- the vCPU APR is stored in the vir
Implement virtualization extensions in the gic_deactivate_irq() and
gic_complete_irq() functions. When a guest tries to deactivat or end an
IRQ that does not exist in the LRs, the EOICount field of the virtual
interface HCR register is incremented by one, and the request is
ignored.
Signed-off-by
Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
a VMState.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 42b946c
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 61 +++
1 file changed, 57 insertions(+), 4 del
v2:
- Add VMSTATE_UINT16_SUB_ARRAY to vmstate.h
- Keep backward compatibility on the GIC VMState by storing vCPUs
state in the virt VMState subsection.
- Use h_apr to store APR value for vCPUs, instead of increasing apr 2D
array. This adds a little complexity to the implementation (a
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 23 ++-
Add the register definitions for the virtual interface of the GICv2.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/gic_internal.h | 65 ++
1 file changed, 65 insertions(+)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
in
ping ...
On Mon, Jun 18, 2018 at 02:04:06PM -0700, Guenter Roeck wrote:
> RX and TX interrupt bits were reversed, resulting in an endless sequence
> of serial interupts in the emulated system and the following repeated
> error message when booting Linux.
>
> serial8250: too much work for irq61
>
This patch adds field with content of KERNEL_GS_BASE MSR to QEMU note in
ELF dump.
On Windows, if all vCPUs are running usermode tasks at the time the dump is
created, this can be helpful in the discovery of guest system structures
during conversion ELF dump to MEMORY.DMP dump.
Signed-off-by: Vik
On Sat, Jul 14, 2018 at 07:37:43AM +0200, Laurent Vivier wrote:
> Le 14/07/2018 à 03:07, David Gibson a écrit :
> > On Fri, Jul 13, 2018 at 07:34:46AM -0500, Shivaprasad G Bhat wrote:
> >> Qemu includes the glibc headers for the host defines and target headers are
> >> part of the qemu source thems
30 matches
Mail list logo
