Ciro Santilli reported that commit a5ed352596a8b7eb2f9acce34371b944ac3056c4
breaks the execution replay. It happens due to the probing the clock
for the new instances of iothread.
However, this probing was made in replay mode for the timer lists that
are empty.
This patch removes clock probing in r
This patch adds events processing when emulation finishes instead
of just cleaning the queue. Now the bdrv coroutines will be in consistent
state when emulator closes. It allows correct polling of the block layer
at exit.
Signed-off-by: Pavel Dovgalyuk
---
replay/replay-events.c | 14 +--
This patch introduces replay_break qmp and hmp commands.
These commands allow stopping at the specified instruction.
It may be useful for debugging when there are some known
events that should be investigated.
The commands have one argument - number of instructions
executed since the start of the r
After recent updates block devices cannot be closed on qemu exit.
This happens due to the block request polling when replay is not finished.
Therefore now we stop execution recording before closing the block devices.
Signed-off-by: Pavel Dovgalyuk
---
replay/replay.c |2 ++
vl.c|
This patch introduces 'info replay' monitor command and
corresponding qmp request.
These commands request the current record/replay mode, replay log file name,
and the execution step (number or recorded/replayed instructions).
Signed-off-by: Pavel Dovgalyuk
--
v2:
- renamed info_replay qmp int
Saving icount as a parameters of the snapshot allows navigation between
them in the execution replay scenario.
This information can be used for finding a specific snapshot for rewinding
the recorded execution to the specific moment of the time.
E.g., 'reverse step' action needs to load the nearest
In record/replay mode bdrv queue is controlled by replay mechanism.
It does not allow saving or loading the snapshots
when bdrv queue is not empty. Stopping the VM is not blocked by nonempty
queue, but flushing the queue is still impossible there,
because it may cause deadlocks in replay mode.
This
Hi,
> > +if (pci_bus_is_express(pci_get_bus(dev))) {
> > +dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
> > +ret = pcie_endpoint_cap_init(dev, 0x80);
> > +assert(ret > 0);
>
> Maybe error_setg(errp, ...) && return?
No. It really should not trigger, and if it does it is
This patch adds hmp/qmp commands replay_seek/replay-seek that proceed
the execution to the specified step.
The commands automatically loads nearest snapshot and replay the execution
to find the desired step.
Signed-off-by: Pavel Dovgalyuk
--
v2:
- renamed replay_seek qmp command into replay-se
From: Pavel Dovgalyuk
This patch enables making snapshots with blkreplay used in
block devices.
This function is required to make bdrv_snapshot_goto without
calling .bdrv_open which is not implemented.
Signed-off-by: Pavel Dovgalyuk
---
block/blkreplay.c |8
1 file changed, 8 inse
This patch updates the description of the command lines for using
record/replay with attached block devices.
Signed-off-by: Pavel Dovgalyuk
---
docs/replay.txt | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/docs/replay.txt b/docs/replay.txt
index 2e21e9c..f7de
GDB remote protocol supports reverse debugging of the targets.
It includes 'reverse step' and 'reverse continue' operations.
The first one finds the previous step of the execution,
and the second one is intended to stop at the last breakpoint that
would happen when the program is executed normally.
This patch introduces the icount field for saving within the snapshot.
It is required for navigation between the snapshots in record/replay mode.
Signed-off-by: Pavel Dovgalyuk
--
v2:
- documented format changes in docs/interop/qcow2.txt
(suggested by Eric Blake)
---
block/qcow2-snapshot.c
Hi,
ZCR system registers are both flagged as ARM_CP_SVE and ARM_CP_FPU,
which results in an assertion failure in fp_access_check due to the
check of these flags in handle_sys:
if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
return;
}
if ((ri->type & ARM_CP_FPU) && !fp_a
From: Pavel Dovgalyuk
This patch disables setting '-snapshot' option on by default
in record/replay mode. This is needed for creating vmstates in record
and replay modes.
Signed-off-by: Pavel Dovgalyuk
---
vl.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/vl
Le 23/05/2018 à 02:15, Michael Clark a écrit :
> Refer to the RISC-V PSABI specification for details:
>
> - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
>
> Cc: Michael Tokarev
> Cc: Laurent Vivier
> Cc: Richard Henderson
> Cc: Alistair Francis
> Signed-off-by: Michae
Kevin Wolf wrote:
> Am 18.05.2018 um 14:14 hat Kevin Wolf geschrieben:
>> Am 18.05.2018 um 12:34 hat Dr. David Alan Gilbert geschrieben:
>> > * Kevin Wolf (kw...@redhat.com) wrote:
>> > > Am 16.05.2018 um 01:39 hat Juan Quintela geschrieben:
>> > > > We need to make sure that we have started all t
On 22.05.2018 21:17, Paolo Bonzini wrote:
> AT24c EEPROM is currently gated by CONFIG_I2C, and as such it is
> being included in all emulators that use I2C, even if they do not
> really need it. Separate it and, since it was added for the e500
> machines, add it to qemu-system-ppc and qemu-system-
On 22.05.2018 21:50, Paolo Bonzini wrote:
> This is only half of the work, because the proxy devices (virtio-*-pci,
> virtio-*-ccw, etc.) are still included unconditionally. It is still a
> move in the right direction.
[...]
> diff --git a/hw/virtio/Makefile.objs b/hw/virtio/Makefile.objs
> index
Hello,
On Tue, May 22, 2018 at 7:56 PM, Richard Henderson
wrote:
> Depending on the host abi, float16, aka uint16_t, values are
> passed and returned either zero-extended in the host register
> or with garbage at the top of the host register.
>
> The tcg code generator has so far been assuming ga
Hello,
I'm investigating status of vNVDIMM on qemu/KVM,
and I have some questions about it. I'm glad if anyone answer them.
In my understanding, qemu/KVM has a feature to show NFIT for guest,
and it will be still updated about platform capability with this patch set.
https://lists.gnu.org/archive
On 22.05.2018 21:20, Paolo Bonzini wrote:
> Even though the presence of softfloat does not cause --disable-tcg builds to
> fail,
> it is the single largest .o file in them. Remove it, since TCG is the only
> client.
>
> Signed-off-by: Paolo Bonzini
> ---
> Makefile.target | 2 +-
>
On 22.05.2018 23:21, Mark Cave-Ayland wrote:
> On 22/05/18 09:30, Thomas Huth wrote:
>
>> Peter reported that the boot-serial tester sometimes runs into timeouts
>> with SPARC guests. It's currently completely unclear whether this is due
>> to too much load on the host machine (so that the guest r
On Wed, 23 May 2018 02:38:52 +0300
"Michael S. Tsirkin" wrote:
> On Tue, May 22, 2018 at 03:47:41PM -0600, Alex Williamson wrote:
> > On Wed, 23 May 2018 00:44:22 +0300
> > "Michael S. Tsirkin" wrote:
> >
> > > On Tue, May 22, 2018 at 03:36:59PM -0600, Alex Williamson wrote:
> > > > On Tue,
While we skip the GIC_INTERNAL irqs, we don't change the register offset
accordingly. This will overlap the GICR registers value and leave the
last GIC_INTERNAL irq's registers out of update.
Fix this by skipping the registers banked by GICR.
Also for migration compatibility if the migration sour
It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-sta...@nongnu.org
Signed-off-by: Shannon Zhao
Reviewed-by: Eric Auger
---
Changes in V3: Add reviewed-by tag
---
hw/intc/arm_gicv3_kvm.c | 1 +
1 file ch
Replace existing trace_vtd_err() with error_report_once() then stderr
will capture something if any of the error happens, meanwhile we don't
suffer from any DDOS. Then remove the trace point. Since at it,
provide more information where proper (now we can pass parameters into
the report function).
I stole the printk_once() macro.
I always wanted to be able to print some error directly if there is a
buffer to dump, however we can't use error_report() where the code path
can be triggered by DDOS attack. To avoid that, we can introduce a
print-once-like function for it. Meanwhile, we also in
v3:
- reindent in patch 2, dump more things [Philippe]
v2:
- for patch 1: replace tabs, add trivial comment [Markus]
(I didn't add much comment otherwise I'll need to duplicate what's
there in error_report())
- add patch 2
Patch 1 introduce the helpers.
Patch 2 use it to replace VT-d trace_
It's a BlockBackend wrapper of the BDS interface.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
---
block/block-backend.c | 18 ++
include/sysemu/block-backend.h | 4
2 files changed, 22 insertions(+)
diff --git a/block/block-backend.c b/block/block-backe
The new blk_co_copy_range interface offers a more efficient way in the
case of network based storage. Make use of it to allow faster convert
operation.
Since copy offloading cannot do zero detection ('-S') and compression
(-c), only try it when these options are not used.
Signed-off-by: Fam Zheng
Issue EXTENDED COPY (LID1) command to implement the copy_range API.
The parameter data construction code is modified from libiscsi's
iscsi-dd.c.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
---
block/iscsi.c| 219 +++
include/scs
This loop is repeated a growing number times. Make a helper.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
---
block/iscsi.c | 54 +-
1 file changed, 17 insertions(+), 37 deletions(-)
diff --git a/block/iscsi.
The two callbacks are implemented quite similarly to the read/write
functions: bdrv_co_copy_range_from maps for read and calls into bs->file
or bs->backing depending on the allocation status; bdrv_co_copy_range_to
maps for write and calls into bs->file.
Signed-off-by: Fam Zheng
---
block/qcow2.c
With copy_file_range(2), we can implement the bdrv_co_copy_range
semantics.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
---
block/file-posix.c | 96 +++--
include/block/raw-aio.h | 10 --
2 files changed, 101 insertions(+), 5 deleti
The device designator data returned in INQUIRY command will be useful to
fill in source/target fields during copy offloading. Do this when
connecting to the target and save the data for later use.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
---
block/iscsi.c| 41 ++
v5: - Fix raw offset/bytes check for read. [Eric]
- Fix qcow2_handle_l2meta. [Stefan]
- Add coroutine_fn whereever appropriate. [Stefan]
v4: - Fix raw offset and size. [Eric]
- iscsi: Drop unnecessary return values and variables in favor of
constants. [Stefan]
- qcow2: Handle
We don't verify the request range against s->size in the I/O callbacks
except for raw_co_pwritev. This is wrong (especially for
raw_co_pwrite_zeroes and raw_co_pdiscard), so fix them.
Signed-off-by: Fam Zheng
---
block/raw-format.c | 64 +-
1 f
Just pass down to ->file.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
---
block/raw-format.c | 32
1 file changed, 32 insertions(+)
diff --git a/block/raw-format.c b/block/raw-format.c
index b69a0674b3..f2e468df6f 100644
--- a/block/raw-format.c
+++ b
Introduce the bdrv_co_copy_range() API for copy offloading. Block
drivers implementing this API support efficient copy operations that
avoid reading each block from the source device and writing it to the
destination devices. Examples of copy offload primitives are SCSI
EXTENDED COPY and Linux co
On Fri, 05/18 16:26, Kevin Wolf wrote:
> NFS paths were only partially filtered in _filter_img_create, _img_info
> and _filter_img_info, resulting in "nfs://127.0.0.1TEST_DIR/t.IMGFMT".
> This adds another replacement to the sed calls that matches the test
> directory not as a host path, but as an
On Fri, 05/18 16:26, Kevin Wolf wrote:
> The reference output file only works for file. 'qemu-img convert -p'
> makes a lot more progress updates for NFS than for file, so disable the
> test for NFS.
>
> Signed-off-by: Kevin Wolf
Reviewed-by: Fam Zheng
On Fri, 05/18 16:26, Kevin Wolf wrote:
> Test cases were trying to use nfs:// URLs as local filenames, which made
> every test fail for NFS. With TEST_IMG and TEST_IMG_FILE set like for
> the other protocols, NFS tests can pass again.
>
> Signed-off-by: Kevin Wolf
Reviewed-by: Fam Zheng
ping.
On Mon, May 21, 2018 at 7:49 PM, 858585 jemmy wrote:
> On Wed, May 16, 2018 at 5:36 PM, 858585 jemmy wrote:
>> On Tue, May 15, 2018 at 10:54 PM, Paolo Bonzini wrote:
>>> On 05/05/2018 16:35, Lidong Chen wrote:
@@ -2635,12 +2637,20 @@ static ssize_t qio_channel_rdma_writev(QIOChannel
On Tue, 05/22 22:10, Paolo Bonzini wrote:
> The expression "SD_INODE_SIZE - sizeof(inode.data_vdi_id)" already has a macro
> defined for the same value (though with a nicer definition using offsetof).
> Replace it.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Fam Zheng
On Tue, 05/22 17:02, Kevin Wolf wrote:
> Am 22.05.2018 um 16:19 hat Michael S. Tsirkin geschrieben:
> > On Tue, May 22, 2018 at 09:35:55AM +0200, Gerd Hoffmann wrote:
> > > Hi,
> > >
> > > > You must /sometimes/ supply the correct machine type.
> > > >
> > > > It is quite dependent on the guest
Hi!
I'm tracking an error case in the native AIO path, and was wondering if
there was a latent (albeit possibly hard to hit) bug. Specifically
util/async.c::aio_get_linux_aio:
#ifdef CONFIG_LINUX_AIO
LinuxAioState *aio_get_linux_aio(AioContext *ctx)
{
if (!ctx->linux_aio) {
ctx->linux
On Tue, 05/22 22:10, Paolo Bonzini wrote:
> block/sheepdog.o has a 4M static variable that is 90% of QEMU's whole .bss
> section. Replace it with a heap-allocated block, and make it smaller too
> since only the inode header is actually being used.
>
> bss size goes down from 4464280 to 269976.
>
On Tue, May 22, 2018 at 06:09:46PM -0300, Philippe Mathieu-Daudé wrote:
> Hi Peter,
>
> On 05/22/2018 12:56 AM, Peter Xu wrote:
> > Replace existing trace_vtd_err() with error_report_once() then stderr
> > will capture something if any of the error happens, meanwhile we don't
> > suffer from any D
On Tue, May 22, 2018 at 12:11:38PM +0100, Peter Maydell wrote:
> On 22 May 2018 at 12:02, Peter Xu wrote:
> > On Tue, May 22, 2018 at 09:40:44AM +0100, Peter Maydell wrote:
> >> On 22 May 2018 at 04:03, Peter Xu wrote:
> >> The reason for not just passing in the transaction attributes to
> >> tra
Support for separate firmware and kernel payload is added
by updating BBL to read optional preloaded kernel address
attributes from device-tree using a similar mechanism to
that used to pass init ramdisk addresses to linux kernel.
chosen {
riscv,kernel-start = <0x 0x8020>;
---
hw/riscv/sifive_u.c | 4 +++-
hw/riscv/spike.c| 6 --
hw/riscv/virt.c | 4 +++-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 326b0f434cff..02721d43c474 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -
From: Kito Cheng
This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.
Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.
Cc: Palmer Dabbelt
Cc: Sagar Kara
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
disas/riscv.c | 138 ---
This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing the translation cache
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Cc: Emilio G. Cota
Signed-off-by: Michael Clark
Reviewed-by
From: Richard Henderson
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Richard Henderson
Signed-off-by: Michael Clark
Reviewed-by: Michael Clark
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +-
2 files changed, 8
The address calculation for the pending bitfield had
a copy paste bug. This bug went unnoticed because the Linux
PLIC driver does not read the pending bitfield, rather it
reads pending interrupt numbers from the claim register
and writes acknowledgements back to the claim register.
Cc: Palmer Dabb
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev
Cc: Laurent Vivier
Cc: Richard Henderson
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
include/elf.h | 8
1 file changed, 8 inser
CSR predicate functions are added to the CSR table.
mstatus.FS and counter enable checks are moved
to predicate functions and two new predicates are
added to check misa.S for s* CSRs and a new PMP
CPU feature for pmp* CSRs.
Processors that don't implement S-mode will trap
on access to s* CSRs and
A missing shift made updates to the low order bits
of timecmp erroneously copy the old low order bits
into the high order bits of the 64-bit timecmp
register. Add the missing shift and rename timecmp
local variables to timecmp_hi and timecmp_lo.
This bug didn't show up as the low order bits are
us
Previously the second UARTs on the sifive_e and sifive_u machines
where disabled due to check-qtest-riscv32 and check-qtest-riscv64
failures. Recent changes in the QEMU core serial code have
resolved these failures so the second UARTs can be instantiated.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/csr.c | 56 +++---
1 file chan
Add misa checks for M, A, F and D extensions and if they are
not present generate illegal instructions. This improves
emulation accurary for harts with a limited set of extensions.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Cc: Emilio G. Cota
Signed-of
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ad03113e0f72..321fa6e8122a 100644
--- a/hw/riscv/virt.c
+++ b/hw/r
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu_helper.c | 18 ++
This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 4 ++--
1 file changed, 2 insertion
This allows hardware and/or derived cpu instances
to override or implement new CSR operations.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu.h | 18 ++
target/riscv/csr.c | 35
Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_update_mip.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mod
From: Richard Henderson
Modifed from Richard Henderson's patch [1] to integrate
with the new control and status register implementation.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html
Note: the f* CSRs already mark mstatus.FS dirty using
env->mstatus |= mstatus.FS so
The PLIC previously used a mutex to protect against concurrent
access to the claimed and pending bitfields. Instead of using
a mutex, we update the bitfields using atomic_cmpxchg.
Rename sifive_plic_num_irqs_pending to sifive_plic_irqs_pending
and add an early out if any interrupts are pending as
We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.
This logic was previously hard-coded so SEI
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Matthew Suozzo
Signed-off-by: Michael Clark
Co-authored-by: Matthew Suozzo
Co-authored-by: Michael Clark
---
targ
* Add user-mode CSR defininitions.
* Reorder CSR definitions to match the specification.
* Change H mode interrupt comment to 'reserved'.
* Remove unused X_COP interrupt.
* Add user-mode and core-level interrupts.
* Remove erroneous until comemnts on machine mode interrupts.
* Move together paging
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34abc383e3d4..e0608e6d5f08 100644
Previous CSR code uses csr_read_helper and csr_write_helper
to update CSR registers however this interface prevents
atomic read/modify/write CSR operations; in addition
there is no trap-free method to access to CSRs due
to the monolithic CSR functions call longjmp.
The current iCSR interface is no
This commit is intended to improve readability.
There is no change to the logic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/helper.c | 34 --
- Inline PTE_TABLE check for better readability
- Change access checks from ternary operator to if
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Set READ protection for
This is a series of bug fixes, specification conformance
fixes and CPU feature modularily updates to allow more
precise modelling of the SiFive U Series CPUs (multi-core
application processors with MMU, Supervisor and User modes)
and SiFive E Series CPUs (embedded microcontroller cores
without MMU
On Wed, May 23, 2018 at 12:42:09AM +0200, Laszlo Ersek wrote:
> Hold on,
>
> On 05/22/18 21:51, Laszlo Ersek wrote:
>
> > It had taken years until the edk2 core gained a universal
> > PciHostBridgeDxe driver with a well-defined platform customization
> > interface, and that interface doesn't supp
On Tue, May 22, 2018 at 03:47:41PM -0600, Alex Williamson wrote:
> On Wed, 23 May 2018 00:44:22 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Tue, May 22, 2018 at 03:36:59PM -0600, Alex Williamson wrote:
> > > On Tue, 22 May 2018 23:58:30 +0300
> > > "Michael S. Tsirkin" wrote:
> > > >
> > > >
On 05/22/2018 02:11 AM, Philippe Mathieu-Daudé wrote:
> On 05/14/2018 12:38 PM, Peter Maydell wrote:
>> On 9 May 2018 at 07:01, Philippe Mathieu-Daudé wrote:
>>> [based on a patch from Alistair Francis
>>> from qemu/xilinx tag xilinx-v2015.2]
>>> Signed-off-by: Edgar E. Iglesias
>>> [PMD: rebas
Hold on,
On 05/22/18 21:51, Laszlo Ersek wrote:
> It had taken years until the edk2 core gained a universal
> PciHostBridgeDxe driver with a well-defined platform customization
> interface, and that interface doesn't support multiple domains /
> segments.
after doing a bit more research: I was w
trace_mem_build_info expects a size_shift for its first argument. Fix it.
Signed-off-by: Emilio G. Cota
---
include/exec/cpu_ldst_useronly_template.h | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu_ldst_useronly_template.h
b/include/exec/cpu_ldst
These will be used by the following commit.
Signed-off-by: Emilio G. Cota
---
trace/mem-internal.h | 12
1 file changed, 12 insertions(+)
diff --git a/trace/mem-internal.h b/trace/mem-internal.h
index a9e408e..f6efaf6 100644
--- a/trace/mem-internal.h
+++ b/trace/mem-internal.h
@@
We do not trace guest atomic accesses. Fix it.
Tested with a modified atomic_add-bench so that it executes
a deterministic number of instructions, i.e. fixed seeding,
no threading and fixed number of loop iterations instead
of running for a certain time.
Before:
- With parallel_cpus = false (no c
Add some defines for the mem_info bits, simplify
trace_mem_build_info, and also simplify trace_mem_get_info
by making it a wrapper around trace_mem_build_info.
This paves the way for increasing size_shift by one bit.
Signed-off-by: Emilio G. Cota
---
trace/mem-internal.h | 40 ++
This series fixes a few issues that I found while testing
the tracing of guest memory accesses in TCG. Please review!
You can fetch these patches from:
https://github.com/cota/qemu/commits/trace-mem
Thanks,
Emilio
This will allow us to trace 16B-long memory accesses.
Signed-off-by: Emilio G. Cota
---
trace/mem-internal.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/trace/mem-internal.h b/trace/mem-internal.h
index b684e27..a9e408e 100644
--- a/trace/mem-internal.h
+++ b/trac
See the individual patches (inclusive change log).
Halil Pasic (2):
vfio-ccw: add force unlimited prefetch property
vfio-ccw: remove orb.c64 (64 bit data addresses) check
hw/s390x/css.c | 12
hw/vfio/ccw.c | 25 +
2 files changed, 25 insertions(+), 12 de
There is at least one guest (OS) such that although it does not rely on
the guarantees provided by ORB 1 word 9 bit (aka unlimited prefetch, aka
P bit) not being set, it fails to tell this to the machine.
Usually this ain't a big deal, as the original purpose of the P bit is to
allow for performan
The vfio-ccw module does the check too, and there is actually no
technical obstacle for supporting fmt 1 idaws. Let us be ready for the
beautiful day when fmt 1 idaws become supported by the vfio-ccw kernel
module. QEMU does not have to do a thing for that, except not insisting
on this check.
Sign
On 22/05/2018 21:27, Peter Maydell wrote:
> On 22 May 2018 at 20:20, Paolo Bonzini wrote:
>> Even though the presence of softfloat does not cause --disable-tcg builds to
>> fail,
>> it is the single largest .o file in them. Remove it, since TCG is the only
>> client.
>>
>> Signed-off-by: Paolo
On 22/05/2018 22:53, Richard Henderson wrote:
> On 05/22/2018 12:20 PM, Paolo Bonzini wrote:
>> Even though the presence of softfloat does not cause --disable-tcg builds to
>> fail,
>> it is the single largest .o file in them. Remove it, since TCG is the only
>> client.
>>
>> Signed-off-by: Paol
On 22/05/2018 22:37, Philippe Mathieu-Daudé wrote:
> Hi Paolo,
>
> On 05/22/2018 04:49 PM, Paolo Bonzini wrote:
>> Signed-off-by: Paolo Bonzini
>> ---
>> default-configs/mips-softmmu-common.mak | 1 +
>> default-configs/pci.mak | 1 +
>> default-configs/riscv32-softmmu.mak |
On 05/22/18 23:47, Alex Williamson wrote:
> On Wed, 23 May 2018 00:44:22 +0300
> "Michael S. Tsirkin" wrote:
>
>> On Tue, May 22, 2018 at 03:36:59PM -0600, Alex Williamson wrote:
>>> On Tue, 22 May 2018 23:58:30 +0300
>>> "Michael S. Tsirkin" wrote:
It's not hard to think of a use-c
On 05/22/18 23:22, Michael S. Tsirkin wrote:
> On Tue, May 22, 2018 at 03:17:32PM -0600, Alex Williamson wrote:
>> On Tue, 22 May 2018 21:51:47 +0200
>> Laszlo Ersek wrote:
>>> But 64-bit is ill-partitioned and/or crowded too: first you have the
>>> cold-plugged >4GB DRAM (whose size the firmware
On 05/22/18 23:17, Alex Williamson wrote:
> On Tue, 22 May 2018 21:51:47 +0200
> Laszlo Ersek wrote:
Thanks Michael and Alex for the education on ARI.
I'd just like to comment on one sub-topic:
>> There are signs that the edk2 core supports ARI if the underlying
>> platform supports it. (Which
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