On Fri, 4 May 2018 15:00:20 +1000
David Gibson wrote:
> On Thu, May 03, 2018 at 06:34:16PM +0200, Greg Kurz wrote:
> > On Thu, 3 May 2018 16:21:40 +1000
> > David Gibson wrote:
> >
> > > rtas_start_cpu() calls spapr_cpu_update_tb_offset() and
> > > spapr_cpu_set_endianness() to initialize ce
On Thu, May 03, 2018 at 12:26:36PM -0500, Eric Blake wrote:
> [resend with updated list address and pruning addresses that bounced]
>
> Reviving this discussion, as it still seems useful to incorporate now that
> BLOCK_STATUS is only recently part of the standard.
Yeah. I thought we'd incorporate
On Fri, May 04, 2018 at 07:58:21AM +0200, Greg Kurz wrote:
> On Fri, 4 May 2018 10:11:02 +1000
> David Gibson wrote:
>
> > On Thu, May 03, 2018 at 11:16:10PM +0200, Greg Kurz wrote:
> > > Hi,
> > >
> > > It is expected to be able to migrate a guest started with
> > >
> > > -machine max-cpu
On Thu, May 03, 2018 at 10:43:47AM +0200, Cédric Le Goater wrote:
> On 05/03/2018 04:29 AM, David Gibson wrote:
> > On Thu, Apr 26, 2018 at 10:17:13AM +0200, Cédric Le Goater wrote:
> >> On 04/26/2018 07:36 AM, David Gibson wrote:
> >>> On Thu, Apr 19, 2018 at 07:40:09PM +0200, Cédric Le Goater wro
On Thu, May 03, 2018 at 12:57:09PM -0300, Murilo Opsfelder Araujo wrote:
> On Thu, Apr 19, 2018 at 04:29:13PM +1000, David Gibson wrote:
> > The paravirtualized PAPR platform sometimes needs to restrict the guest to
> > using only some of the page sizes actually supported by the host's MMU.
> > At
On Fri, May 04, 2018 at 07:54:19AM +0200, Greg Kurz wrote:
> On Fri, 4 May 2018 10:12:23 +1000
> David Gibson wrote:
>
> > On Thu, May 03, 2018 at 11:16:29PM +0200, Greg Kurz wrote:
> > > The pseries-2.7 and older machine types require CPUPPCState::insns_flags
> > > to be strictly equal between s
From: Mark Cave-Ayland
Introduce constants for the pre-defined New World IRQs to help keep things
readable.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
hw/ppc/mac.h | 9 +
hw/ppc/mac_newworld.c | 29 +++--
2 files changed, 24 inser
From: Greg Kurz
On a POWER9 host, if a guest runs in pre POWER9 compat mode, it necessarily
uses the hash MMU mode. In this case, we shouldn't advertise radix GTSE in
the ibm,arch-vec-5-platform-support DT property as the current code does.
The first reason is that it doesn't make sense, and the
From: Greg Kurz
The pseries-2.7 and older machine types require CPUPPCState::insns_flags
to be strictly equal between source and destination. This checking is
abusive and breaks migration of KVM guests when the host CPU models
are different, even if they are compatible enough to allow the guest
t
cpu_ppc_set_papr() does several things:
1) it sets up the virtual hypervisor interface
2) it prevents the cpu from ever entering hypervisor mode
3) it tells KVM that we're emulating a cpu in PAPR mode
and 4) it configures the LPCR and AMOR (hypervisor privileged registers)
so tha
From: Mark Cave-Ayland
Commit 4e46dcdbd3 "PPC: Newworld: Add uninorth token register" added a TODO
which was to convert the uninorth registers hack to a proper device. Move
these registers to a new uninorth device, removing the old hacks from
mac_newworld.c.
Signed-off-by: Mark Cave-Ayland
Revi
In cpu_ppc_set_papr() the UPRT and GTSE bits of the LPCR default value are
initialized based on on ppc64_radix_guest(). Which seems reasonable,
except that ppc64_radix_guest() is based on spapr->patb_entry which is
only set up in spapr_machine_reset, called _after_ cpu_ppc_set_papr() for
boot cpus
To prevent spurious wakeups on cpus that are supposed to be disabled, we
need to clear the LPCR bits which control certain wakeup events.
spapr_cpu_reset() has separate cases here for boot and non-boot (initially
inactive) cpus. rtas_start_cpu() then turns the LPCR bits on when the
non-boot cpus a
This makes several minor cleanups to these functions:
* Follow usual convention of an early exit on error, rather than having
most of the body in an if
* Clearer naming of cpu and cpu_. Now callcpu is the cpu from which the
RTAS call is invoked, newcpu is the cpu which we're starting
rtas_start_cpu() calls spapr_cpu_update_tb_offset() and
spapr_cpu_set_endianness() to initialize certain things in the new cpu's
state. This is the only caller of those helpers, and they're each only
a few lines long, so we might as well just fold them into the caller.
In addition, those helpers
There are some fields in the cpu state which need to be updated when the
LPCR register is changed, which is done by ppc_hash64_update_rmls() and
ppc_hash64_update_vrma(). Code which alters env->spr[SPR_LPCR] needs to
call them afterwards to make sure the state is up to date.
That's easy to get wr
From: Mark Cave-Ayland
Since the macio device has a link to the PIC device, we can now wire up the
IRQs directly via qdev GPIOs rather than having to use an intermediate array.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
hw/misc/macio/macio.c | 39 +
From: Cédric Le Goater
commit e57ca75ce3b2 ("target/ppc: Manage external HPT via virtual
hypervisor") exported a set of methods to manipulate the HPT from the
core hash MMU. But SPR_SDR1 is still used under some circumstances to
get the base address of the HPT, which is incorrect for the sPAPR
ma
Under PAPR, only the boot CPU is active when the system starts. Other cpus
must be explicitly activated using an RTAS call. The entry state for the
boot and secondary cpus isn't identical, but it has some things in common.
We're going to add a bit more common setup later, too, so to simplify
make
From: Greg Kurz
a324d6f16697 "spapr: Support ibm,dynamic-memory-v2 property" added
a new feature in the set of CAS-negotiatable options. This causes
the CAS-negotiated options subsection to be migrated, even for old
machine types that don't know about it, and breaks backward migration
to QEMU 2.7
Current POWER cpus allow for a VRMA, a special mapping which describes a
guest's view of memory when in real mode (MMU off, from the guest's point
of view). Older cpus didn't have that which meant that to support a guest
a special host-contiguous region of memory was needed to give the guest its
R
The following changes since commit 59255887e6cafeff747250d2613003a41d1d9dff:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180502' into
staging (2018-05-03 11:25:14 +0100)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.13-20180504
for y
There are several places in spapr_hcall.c where we need to update the LPCR
value on all CPUs. We do this with the set_spr() helper. That's not
really correct because this directly sets the SPR value, without going
through the ppc_store_lpcr() helper which may need to update state based
on the LPC
From: Cédric Le Goater
The Partition Table Control Register (PTCR) is a hypervisor privileged
SPR. It contains the host real address of the Partition Table and its
size.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
target/ppc/cpu.h| 2
On Fri, 4 May 2018 10:11:02 +1000
David Gibson wrote:
> On Thu, May 03, 2018 at 11:16:10PM +0200, Greg Kurz wrote:
> > Hi,
> >
> > It is expected to be able to migrate a guest started with
> >
> > -machine max-cpu-compat=power8
> >
> > from a POWER9 host to a POWER8 host. It works with re
On Fri, 4 May 2018 10:12:23 +1000
David Gibson wrote:
> On Thu, May 03, 2018 at 11:16:29PM +0200, Greg Kurz wrote:
> > The pseries-2.7 and older machine types require CPUPPCState::insns_flags
> > to be strictly equal between source and destination. This checking is
> > abusive and breaks migratio
"Michael S. Tsirkin" writes:
> On Fri, Apr 13, 2018 at 12:04:20PM +0200, Marc-André Lureau wrote:
>> Hi
>>
>> On Fri, Apr 13, 2018 at 9:21 AM, Markus Armbruster wrote:
>> > "Michael S. Tsirkin" writes:
>> >
>> >> This is helpful for automatic code analysis.
>> >
>> > Out of curiosity: how?
>>
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 120 +--
target/openrisc/insns.decode | 15 ++
2 files changed, 73 insertions(+), 62 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 548e0230
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 359 +++
target/openrisc/insns.decode | 21 +++
2 files changed, 149 insertions(+), 231 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index f02d04cbc
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 116 +--
target/openrisc/insns.decode | 12 +
2 files changed, 70 insertions(+), 58 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 2c15b2713
This reverts commit 9578f8cc3e8bd71de8e3f543dc7b95644d64824e.
The patch snuck in by accident without having been posted to
qemu-devel. It's entirely redundant: existing target print-% already
serves the purpose.
Cc: Michael S. Tsirkin
Signed-off-by: Markus Armbruster
---
Makefile | 3 ---
1 f
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 41 +
target/openrisc/insns.decode | 3 +++
2 files changed, 16 insertions(+), 28 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index f2f9a0c0d2..548
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 322 +++
target/openrisc/insns.decode | 76 +++---
2 files changed, 229 insertions(+), 169 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 01
On 05/03/2018 10:51 PM, Michael S. Tsirkin wrote:
Some places include kvm_i386.h, others target/i386/kvm_i386.h.
Let's be consistent.
Signed-off-by: Michael S. Tsirkin
---
hw/i386/kvm/apic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/kvm/apic.c b/hw/i386/kv
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 66e493220e..3866106bf6 100644
--- a/target/openrisc/translate.c
+++ b/target/openris
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 62 +++-
target/openrisc/insns.decode | 6 +
2 files changed, 32 insertions(+), 36 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 8ca01e1a33
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 279 +++
target/openrisc/insns.decode | 35 +-
2 files changed, 151 insertions(+), 163 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 794002
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 55 ++--
target/openrisc/insns.decode | 5
2 files changed, 27 insertions(+), 33 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 90520b0805.
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 149 +--
target/openrisc/insns.decode | 12
2 files changed, 83 insertions(+), 78 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 40b21a5db1
Begin with the 0x08 major opcode, the system instructions.
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 79 +--
target/openrisc/Makefile.objs | 9 +
target/openrisc/insns.decode | 28 +++
3 files changed, 76 insert
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 275 +--
target/openrisc/insns.decode | 24
2 files changed, 160 insertions(+), 139 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 95e4f17b
While the openrisc decode isn't particularly complicated,
the result, I think, is still cleaner.
r~
Richard Henderson (13):
target-openrisc: Write back result before FPE exception
target/openrisc: Start conversion to decodetree.py
target/openrisc: Convert branch insns
target/openrisc: C
On 05/03/2018 10:51 PM, Michael S. Tsirkin wrote:
Some places include tcg.h, others tcg/tcg.h.
Let's be consistent.
Signed-off-by: Michael S. Tsirkin
---
include/exec/translator.h | 2 +-
trace/mem.h | 2 +-
accel/stubs/tcg-stub.c| 2 +-
accel/tcg/cputlb.c| 2 +-
From: Richard Henderson
The architecture manual is unclear about this, but the or1ksim
does writeback before the exception. This requires splitting
the helpers in half, with the exception raised by the second.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target/openri
Stefan Hajnoczi writes:
[...]
> So to clarify, three separate steps:
>
> 1. Get rid of target-specific #ifdefs
... and compile just once instead of per target, speeding up the build
> 2a. Modular QEMU, single binary
> 2b. Heterogenous QEMU
>
> 2a and 2b are independent but both depend on 1.
1.
On Thu, May 03, 2018 at 04:37:29PM +0200, Cédric Le Goater wrote:
> On 05/03/2018 08:25 AM, David Gibson wrote:
> > On Thu, May 03, 2018 at 08:07:54AM +0200, Cédric Le Goater wrote:
> >> On 05/03/2018 07:45 AM, David Gibson wrote:
> >>> On Thu, Apr 26, 2018 at 11:48:06AM +0200, Cédric Le Goater wro
On Thu, May 03, 2018 at 05:13:31PM +0200, Greg Kurz wrote:
> On Thu, 3 May 2018 16:21:39 +1000
> David Gibson wrote:
>
> > This makes several minor cleanups to these functions:
> > * Follow usual convention of an early exit on error, rather than having
> > most of the body in an if
> > *
On Thu, May 03, 2018 at 06:34:16PM +0200, Greg Kurz wrote:
> On Thu, 3 May 2018 16:21:40 +1000
> David Gibson wrote:
>
> > rtas_start_cpu() calls spapr_cpu_update_tb_offset() and
> > spapr_cpu_set_endianness() to initialize certain things in the new cpu's
> > state. This is the only caller of t
On Thu, May 03, 2018 at 06:06:14PM +0200, Cédric Le Goater wrote:
> On 05/03/2018 07:35 AM, David Gibson wrote:
> > On Thu, Apr 26, 2018 at 11:27:21AM +0200, Cédric Le Goater wrote:
> >> On 04/26/2018 09:11 AM, David Gibson wrote:
> >>> On Thu, Apr 19, 2018 at 02:43:02PM +0200, Cédric Le Goater wro
On Thu, May 03, 2018 at 05:10:48PM +0200, Cédric Le Goater wrote:
> On 05/03/2018 07:39 AM, David Gibson wrote:
> > On Thu, Apr 26, 2018 at 07:15:29PM +0200, Cédric Le Goater wrote:
> >> On 04/26/2018 11:27 AM, Cédric Le Goater wrote:
> >>> On 04/26/2018 09:11 AM, David Gibson wrote:
> On Thu,
On Tue, Apr 17, 2018 at 04:08:01PM +0200, Paolo Bonzini wrote:
[...]
> +static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion
> *iommu_mr,
> + hwaddr *xlat,
> + hw
On Fri, May 4, 2018 at 3:50 AM, Michael S. Tsirkin wrote:
> When pulling in headers that are in the same directory as C file (as
> opposed to one in include/), we should use its relative path, without a
> directory. Directory based path works more or less by accident.
>
> Signed-off-by: Michael S
In some cases (e.g. spapr) we record guest timebase after qmp_stop()
via a runstate hook so we can restore it on qmp_cont(). If a migration
occurs in between those events we end up saving it again, this time
based on the current timebase the guest would be seeing had it been
running. This has the e
On Tue, Apr 17, 2018 at 04:08:00PM +0200, Paolo Bonzini wrote:
> Prepare for extracting the IOMMU part to a separate function. Mostly
> cosmetic; the only semantic change is that, if there is more than one
> cascaded IOMMU and the second one fails to translate, *plen_out is now
> adjusted accordin
On Fri, May 4, 2018 at 8:56 AM, Alistair Francis
wrote:
> On Wed, Apr 25, 2018 at 5:02 PM Michael Clark wrote:
>
> > * Add user-mode CSR defininitions.
> > * Reorder CSR definitions to match the specification.
> > * Change H mode interrupt comment to 'reserved'.
> > * Remove unused X_COP interru
On Thu, Mar 1, 2018 at 10:03 AM Philippe Mathieu-Daudé
wrote:
> On 02/28/2018 07:32 PM, Alistair Francis wrote:
> > Signed-off-by: Alistair Francis
> > ---
> >
> > hw/microblaze/xlnx-zynqmp-pmu.c | 77
+++--
> > 1 file changed, 75 insertions(+), 2 deletions(-
On Thu, May 03, 2018 at 06:50:09PM +0200, Cédric Le Goater wrote:
> On 05/03/2018 07:22 AM, David Gibson wrote:
> > On Thu, Apr 26, 2018 at 12:43:29PM +0200, Cédric Le Goater wrote:
> >> On 04/26/2018 06:20 AM, David Gibson wrote:
> >>> On Tue, Apr 24, 2018 at 11:46:04AM +0200, Cédric Le Goater wro
On Thu, May 03, 2018 at 08:20:33PM -0700, no-re...@patchew.org wrote:
[...]
> === OUTPUT BEGIN ===
> Checking PATCH 1/10: intel-iommu: send PSI always even if across PDEs...
> Checking PATCH 2/10: intel-iommu: remove IntelIOMMUNotifierNode...
> Checking PATCH 3/10: intel-iommu: add iommu lock...
On Thu, Mar 1, 2018 at 10:21 AM Philippe Mathieu-Daudé
wrote:
> On 02/28/2018 07:31 PM, Alistair Francis wrote:
> > Signed-off-by: Alistair Francis
> > ---
> > V2:
> > - Use UINT32_MAX and uint64_t in xlnx_iomod_pit_ctr_pr()
> > - Name frequency varaible frequency_hz
> > - Shorten R_MAX #defi
On Thu, Mar 1, 2018 at 9:02 AM Philippe Mathieu-Daudé
wrote:
> Hi Alistair,
> On 02/28/2018 07:32 PM, Alistair Francis wrote:
> > Signed-off-by: Alistair Francis
> > ---
> >
> > include/hw/gpio/xlnx-pmu-iomod-gp.h | 52 +
> > hw/gpio/xlnx-pmu-iomod-gp.c | 150
+
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180504030811.28111-1-pet...@redhat.com
Subject: [Qemu-devel] [PATCH v2 00/10] intel-iommu: nested vIOMMU, cleanups,
bug fixes
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=b
On Fri, May 04, 2018 at 05:44:02AM +0300, Michael S. Tsirkin wrote:
> On Fri, May 04, 2018 at 10:17:01AM +1000, David Gibson wrote:
> > On Thu, May 03, 2018 at 10:51:42PM +0300, Michael S. Tsirkin wrote:
> > > Some places include kvm_ppc.h, others target/ppc/kvm_ppc.h.
> > > Let's be consistent.
>
Now after previous changes, we will always pass that parameter as true
now. Remove it. After removing that variable, now we can greatly
simplify the page walking logic.
No functional change at all.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 70 +
During the recursive page walking of IOVA page tables, some stack
variables are constant variables and never changed during the whole page
walking procedure. Isolate them into a struct so that we don't need to
pass those contants down the stack every time and multiple times.
Signed-off-by: Peter
IOMMU replay was carried out before in many use cases, e.g., context
cache invalidations, domain flushes. We used this mechanism to sync the
shadow page table by firstly (1) unmap the whole address space, then
(2) walk the page table to remap what's in the table.
This is very dangerous.
The prob
For each VTDAddressSpace, now we maintain what IOVA ranges we have
mapped and what we have not. With that information, now we only send
MAP or UNMAP when necessary. Say, we don't send MAP notifies if we know
we have already mapped the range, meanwhile we don't send UNMAP notifies
if we know we ne
We pass in the VTDAddressSpace to replace the aw bits when doing page
walk. The VTDAddressSpace contains the aw bits information, meanwhile
we'll need to do something more in the follow up patches regarding to
the address spaces.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 20 ++
Add a per-iommu big lock to protect IOMMU status. Currently the only
thing to be protected is the IOTLB/context cache, since that can be
accessed even without BQL, e.g., in IO dataplane.
Note that we don't need to protect device page tables since that's fully
controlled by the guest kernel. Howe
Introduce a simplest interval tree implementation based on GTree.
Current implementation is mostly tailored to maintain and trace device
mapped IOVA ranges, but still it might be useful to other modules in the
future.
It is naive in that it even does not allow user to pass in private
structs along
That is not really necessary. Removing that node struct and put the
list entry directly into VTDAddressSpace. It simplfies the code a lot.
Signed-off-by: Peter Xu
---
include/hw/i386/intel_iommu.h | 9 ++--
hw/i386/intel_iommu.c | 41 ++-
2 files ch
For UNMAP-only IOMMU notifiers, we don't really need to walk the page
tables. Fasten that procedure by skipping the page table walk. That
should boost performance for UNMAP-only notifiers like vhost.
Signed-off-by: Peter Xu
---
include/hw/i386/intel_iommu.h | 2 ++
hw/i386/intel_iommu.c
During IOVA page table walking, there is a special case when the PSI
covers one whole PDE (Page Directory Entry, which contains 512 Page
Table Entries) or more. In the past, we skip that entry and we don't
notify the IOMMU notifiers. This is not correct. We should send UNMAP
notification to regi
v2:
- fix patchew code style warnings
- interval tree: postpone malloc when inserting; simplify node remove
a bit where proper [Jason]
- fix up comment and commit message for iommu lock patch [Kevin]
- protect context cache too using the iommu lock [Kevin, Jason]
- add vast comment in patch 8 to
On Fri, May 04, 2018 at 05:39:57AM +0300, Michael S. Tsirkin wrote:
> On Fri, May 04, 2018 at 10:15:56AM +1000, David Gibson wrote:
> > On Thu, May 03, 2018 at 10:51:12PM +0300, Michael S. Tsirkin wrote:
> > > This way they are easier to find using standard rules.
> > >
> > > Signed-off-by: Michae
On Fri, May 04, 2018 at 10:17:01AM +1000, David Gibson wrote:
> On Thu, May 03, 2018 at 10:51:42PM +0300, Michael S. Tsirkin wrote:
> > Some places include kvm_ppc.h, others target/ppc/kvm_ppc.h.
> > Let's be consistent.
> >
> > Signed-off-by: Michael S. Tsirkin
>
> One of your earlier patches i
On Fri, May 04, 2018 at 10:15:56AM +1000, David Gibson wrote:
> On Thu, May 03, 2018 at 10:51:12PM +0300, Michael S. Tsirkin wrote:
> > This way they are easier to find using standard rules.
> >
> > Signed-off-by: Michael S. Tsirkin
>
> I don't really understand what this is accomplishing.
Pls
On Thu, May 03, 2018 at 03:45:05PM -0600, Alex Williamson wrote:
> The NVIDIA BAR0 quirks virtualize the PCI config space mirrors found
> in device MMIO space. Normally PCI config space is considered a slow
> path and further optimization is unnecessary, however NVIDIA uses a
> register here to en
On Thu, May 03, 2018 at 03:45:13PM -0600, Alex Williamson wrote:
> With vfio ioeventfd support, we can program vfio-pci to perform a
> specified BAR write when an eventfd is triggered. This allows the
> KVM ioeventfd to be wired directly to vfio-pci, entirely avoiding
> userspace handling for thes
On Thu, May 03, 2018 at 10:29:42AM -0600, Alex Williamson wrote:
> On Thu, 3 May 2018 12:56:03 +0800
> Peter Xu wrote:
>
> > On Tue, May 01, 2018 at 10:43:46AM -0600, Alex Williamson wrote:
> >
> > [...]
> >
> > > -static void vfio_ioeventfd_exit(VFIOIOEventFD *ioeventfd)
> > > +static void vfi
On Sat, Apr 28, 2018 at 4:17 AM, Alistair Francis
wrote:
> On Thu, Apr 26, 2018 at 10:34 PM Michael Clark wrote:
>
>
>
> > On Fri, Apr 27, 2018 at 5:22 PM, Michael Clark wrote:
>
>
>
> >> On Fri, Apr 27, 2018 at 4:48 AM, Alistair Francis >
> wrote:
>
> >>> On Wed, Apr 25, 2018 at 5:03 PM Micha
On Thu, May 03, 2018 at 02:34:21PM +0200, Greg Kurz wrote:
> On Wed, 18 Apr 2018 13:33:44 +1000
> David Gibson wrote:
>
> > On Tue, Apr 17, 2018 at 02:39:09PM +0530, Bharata B Rao wrote:
> > > On Tue, Apr 17, 2018 at 11:14:27AM +1000, David Gibson wrote:
> > > > > static void spapr_machine_2_1
On Thu, May 03, 2018 at 09:24:38PM +0100, Mark Cave-Ayland wrote:
> This is the remaining set of patches from my previous uninorth patchset which
> moves the uninorth token register to its own separate device, and then moves
> the wiring of macio IRQs to the Mac New World machine (similar to as alr
On Thu, May 03, 2018 at 09:24:39PM +0100, Mark Cave-Ayland wrote:
> Commit 4e46dcdbd3 "PPC: Newworld: Add uninorth token register" added a TODO
> which was to convert the uninorth registers hack to a proper device. Move
> these registers to a new uninorth device, removing the old hacks from
> mac_n
On Thu, May 03, 2018 at 11:16:10PM +0200, Greg Kurz wrote:
> Hi,
>
> It is expected to be able to migrate a guest started with
>
> -machine max-cpu-compat=power8
>
> from a POWER9 host to a POWER8 host. It works with recent QEMU versions,
> but it is badly broken if the destination runs QEM
On Thu, May 03, 2018 at 10:51:42PM +0300, Michael S. Tsirkin wrote:
> Some places include kvm_ppc.h, others target/ppc/kvm_ppc.h.
> Let's be consistent.
>
> Signed-off-by: Michael S. Tsirkin
One of your earlier patches in this series moved to using a full
target/ppc/whatever.h for includers outs
On Thu, May 03, 2018 at 11:16:29PM +0200, Greg Kurz wrote:
> The pseries-2.7 and older machine types require CPUPPCState::insns_flags
> to be strictly equal between source and destination. This checking is
> abusive and breaks migration of KVM guests when the host CPU models
> are different, even i
On Thu, May 03, 2018 at 10:51:12PM +0300, Michael S. Tsirkin wrote:
> This way they are easier to find using standard rules.
>
> Signed-off-by: Michael S. Tsirkin
I don't really understand what this is accomplishing.
> ---
> include/hw/ppc/e500-ccsr.h | 1 +
> include/hw/ppc/mac.h | 1 +
Currently the device-tree create_device_tree function
returns the size of the allocated device tree buffer
however there is no way to get the actual amount of
buffer space used by the device-tree.
14ec3cbd7c1e31dca4d23f028100c8f43e156573 increases
the FDT_MAX_SIZE to 1 MiB. This creates an issue
f
On 04.05.2018 03:01, Michael S. Tsirkin wrote:
> On Fri, May 04, 2018 at 02:35:49AM +0200, Thomas Huth wrote:
>> On 03.05.2018 21:51, Michael S. Tsirkin wrote:
>>> Each target is currently built with a different set of include
>>> directories, this is what makes it possible to pull in a separate co
On 05/03/2018 06:56 PM, John Snow wrote:
> I'm working on a project to attempt to autogenerate all of this, but
> until then let's just do a bit of the usual kinds of tidying.
>
>
>
> For convenience, this branch is
On Fri, May 04, 2018 at 02:35:49AM +0200, Thomas Huth wrote:
> On 03.05.2018 21:51, Michael S. Tsirkin wrote:
> > Each target is currently built with a different set of include
> > directories, this is what makes it possible to pull in a separate copy
> > of cpu.h depending on the target.
> >
> >
On 03.05.2018 21:51, Michael S. Tsirkin wrote:
> Each target is currently built with a different set of include
> directories, this is what makes it possible to pull in a separate copy
> of cpu.h depending on the target.
>
> Replace with per-target ifdefs which are easier to understand.
>
> Signe
On 03.05.2018 21:50, Michael S. Tsirkin wrote:
> we just need a struct name, let's add a forward
> declaration instead of an include.
>
> Signed-off-by: Michael S. Tsirkin
> ---
> include/hw/s390x/sclp.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/s390x
On Thu, May 03, 2018 at 10:51:39PM +0300, Michael S. Tsirkin wrote:
> This way they are easier to find.
>
> Signed-off-by: Michael S. Tsirkin
Acked-by: David Gibson
> ---
> hw/ppc/spapr.c | 6 +++---
> hw/ppc/spapr_caps.c | 2 +-
> hw/ppc/spapr_hcall.c | 4 ++--
> 3 files changed, 6 in
On Thu, May 03, 2018 at 10:50:35PM +0300, Michael S. Tsirkin wrote:
> When pulling in headers that are in the same directory as C file (as
> opposed to one in include/), we should use its relative path, without a
> directory. Directory based path works more or less by accident.
>
> Signed-off-by:
> Commit 4e46dcdbd3 "PPC: Newworld: Add uninorth token register" added a TODO
> which was to convert the uninorth registers hack to a proper device. Move
> these registers to a new uninorth device, removing the old hacks from
> mac_newworld.c.
>
> Signed-off-by: Mark Cave-Ayland
> Reviewed-by: P
Hi,
This series failed build test on s390x host. Please find the details below.
Type: series
Message-id: 20180503222626.1303410-1-ebl...@redhat.com
Subject: [Qemu-devel] [PATCH] nbd/client: Relax handling of large
NBD_CMD_BLOCK_STATUS reply
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180503222626.1303410-1-ebl...@redhat.com
Subject: [Qemu-devel] [PATCH] nbd/client: Relax
The TEXI and string versions are actually identical, except for markup.
We can probably automate this... but make the ordering the same until
then.
Signed-off-by: John Snow
---
qemu-img-cmds.hx | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/qemu-img-cmds.hx b/qemu-img-
These are also different and out of order for whatever reason.
I'd like to automate this in the future, but for now let's put
on the band-aid.
In the case of resize, there were options missing from all
three docstrings; the new string is based on the code.
Signed-off-by: John Snow
---
qemu-img-
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