Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1521663109-32262-1-git-send-email-c...@braap.org
Subject: [Qemu-devel] [PATCH v1 00/14] fp-test + hostfloat
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git l
On 03/22/2018 01:57 PM, Emilio G. Cota wrote:
>> Is there any especially good reason you want to not put this code into the
>> normal softfloat function? Does it really many any measurable difference at
>> all to force this code to be inlined into a helper?
>
> You mean to do this? (... or see be
From: yuchenlin
VMDK has a hard limitation of extent size, which is due to the size of grain
table entry is 32 bits. It means it can only point to a grain located at
offset = 2^32. To avoid writing the user data beyond limitation and record a
useless offset
in grain table. We should return ERROR
On Thu, Mar 22, 2018 at 13:05:00 +0800, Richard Henderson wrote:
> On 03/22/2018 04:11 AM, Emilio G. Cota wrote:
> > +#define GEN_FPU_ADDSUB(add_name, sub_name, soft_t, host_t, \
> > + host_abs_func, min_normal) \
> > +static inline __att
On 21.03.2018 12:52, Marc-André Lureau wrote:
> Signed-off-by: Marc-André Lureau
> Acked-by: Cornelia Huck
> ---
> qapi/misc.json | 101 --
> qapi/target.json| 106
> include/sysemu/arch_init.h
"Peter Maydell" wrote on 03/15/2018 11:55:19
AM:
> From: "Peter Maydell"
> To: alar...@ddci.com
> Cc: "QEMU Developers"
> Date: 03/15/2018 11:55 AM
> Subject: Re: [Qemu-devel] -icount changes physical address assignments
in QEMU 2.10/2.11
>
> On 23 February 2018 at 00:39, wrote:
> > When p
Hi,
This series failed docker-build@min-glib build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180321115211.17937-1-marcandre.lur...@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/49
From: yuchenlin
VMDK has a hard limitation of extent size, which is due to the size of grain
table entry is 32 bits. It means it can only point to a grain located at
offset = 2^32. To prevent offset overflow and record a useless offset
in grain table. We should return un-support here.
Signed-off
On Wed, Mar 21, 2018 at 05:37:22PM +0100, Paolo Bonzini wrote:
> On 21/03/2018 17:31, Howard Spoelstra wrote:
> > On Wed, Mar 21, 2018 at 5:25 PM, Paolo Bonzini wrote:
> >> On 21/03/2018 17:23, Howard Spoelstra wrote:
> >>> warning: FTH: (10844): *** Fault tolerant heap shim applied to current
> >
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180321211056.3339-1-yuval.sh...@oracle.com
Subject: [Qemu-devel] [PATCH 0/3] hw/rdma: Fix 32-bit compilation
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(gi
On 03/22/2018 04:11 AM, Emilio G. Cota wrote:
> +#define GEN_FPU_ADDSUB(add_name, sub_name, soft_t, host_t, \
> + host_abs_func, min_normal) \
> +static inline __attribute__((always_inline)) soft_t \
> +fpu_ ## soft_t
On Thu, Mar 22, 2018 at 12:32:36AM +0100, Marc-André Lureau wrote:
> Hi
>
> On Wed, Mar 21, 2018 at 9:33 PM, Eric Blake wrote:
> > On 03/21/2018 03:09 PM, Dr. David Alan Gilbert wrote:
> >
>
> So the parsing job and the dispatching job is isolated now. It gives us
> a chance in fo
On Thu, Mar 22, 2018 at 01:29:23 +, Alex Bennée wrote:
> Emilio G. Cota writes:
>
> > Performance results for fp-bench run under aarch64-linux-user
> > on an Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz host:
> >
> > - before:
> > sqrt-single: 13.23 MFlops
> > sqrt-double: 13.24 MFlops
> >
> > -
On Thu, 03/22 10:40, yuchen...@synology.com wrote:
> From: yuchenlin
>
> VMDK has a hard limitation of extent size, which is due to the size of grain
> table entry is 32 bits. It means it can only point to a grain located at
> offset = 2^32. To prevent offset overflow and record a useless offset
On Wed, Mar 21, 2018 at 07:55:19AM -0500, Eric Blake wrote:
> On 03/21/2018 01:55 AM, Peter Xu wrote:
> > Add "id" fields to the commands, and check that the command returns are
> > in order.
> >
> > Signed-off-by: Peter Xu
> > ---
> > tests/qmp-test.c | 8 +++-
> > 1 file changed, 7 inser
The apt-get commands we run through ssh expect certain features of the
tty, and refuses to work if /dev/null is used. It is ugly, but easy to
satisfy.
Actually, there is no reason to hide the output. It just makes things
harder to diagnose. We can always redirect in the Makefile, so don't do
it co
Hello,
In 'bdrv_all_create_snapshot', each block will create snapshot in a for loop.
If a domain configured disk mixed with qcow2 and rbd.
In 'qcow2_snapshot_create', sn_info->id_str will be set. But in
'qemu_rbd_snap_create' the 'id_str' is checked.
On this condition, 'id_str' check will be fa
On Wed, Mar 21, 2018 at 07:52:06AM -0500, Eric Blake wrote:
> On 03/21/2018 01:55 AM, Peter Xu wrote:
> > It simply tests the new OOB capability, and make sure the QAPISchema can
> > parse it correctly.
>
> We also want negative tests that cover any new error messages in the qapi
> generator (such
On Wed, Mar 21, 2018 at 05:58:48PM -0400, John Snow wrote:
> ./check -v -raw
> Failures: 109 132 136 148 152 183
>
> 3fd2457d18edf5736f713dfe1ada9c87a9badab1 is the first bad commit
> commit 3fd2457d18edf5736f713dfe1ada9c87a9badab1
> Author: Peter Xu
> Date: Fri Mar 9 17:00:03 2018 +0800
>
>
Instead of using "1.0" as the system version of SMBIOS, we should use
mc->desc for mach-virt machine type. With this patch, "dmidecode -t 1"
(e.g., "-M virt-2.12,accel=kvm") will show:
Handle 0x0100, DMI type 1, 27 bytes
System Information
Manufacturer: QEMU
Product
On Wed, Mar 21, 2018 at 12:36:44PM +0100, Marc-André Lureau wrote:
> Fix leak spotted by ASAN:
>
> Direct leak of 16 byte(s) in 1 object(s) allocated from:
> #0 0x7fe1abb80a38 in __interceptor_calloc (/lib64/libasan.so.4+0xdea38)
> #1 0x7fe1aaf1bf75 in g_malloc0 ../glib/gmem.c:124
> #2
On 03/20/2018 11:24 AM, Michael S. Tsirkin wrote:
On Tue, Mar 20, 2018 at 11:18:23AM +0800, Wei Wang wrote:
On 03/20/2018 10:59 AM, Michael S. Tsirkin wrote:
On Tue, Mar 20, 2018 at 10:16:09AM +0800, Wei Wang wrote:
On 03/20/2018 06:55 AM, Michael S. Tsirkin wrote:
On Mon, Mar 19, 2018 at 05:
On Wed, Mar 21, 2018 at 12:11:21PM -0500, Eric Blake wrote:
> On 03/21/2018 07:37 AM, Max Reitz wrote:
> > On 2018-03-12 19:36, Eric Blake wrote:
> > > From: Peter Xu
> > >
> > > Start to use dedicate IO thread for QMP monitors that are not using
> > > MUXed chardev.
> > >
> > > Reviewed-by: Fam
On 2018年03月20日 18:44, Greg Kurz wrote:
If the backend could not transmit a packet right away for some reason,
the packet is queued for asynchronous sending. The corresponding vq
element is tracked in the async_tx.elem field of the VirtIONetQueue,
for later freeing when the transmission is compl
On Wed, 03/21 11:58, Paolo Bonzini wrote:
> diff --git a/hw/scsi/scsi-generic.c b/hw/scsi/scsi-generic.c
> index 7414fe2d67..b3de5df324 100644
> --- a/hw/scsi/scsi-generic.c
> +++ b/hw/scsi/scsi-generic.c
> @@ -500,9 +500,10 @@ static void scsi_generic_realize(SCSIDevice *s, Error
> **errp)
>
Le 23/01/2018 à 15:48, Laurent Vivier a écrit :
> From: Peter Maydell
>
> If multiple guest threads in user-mode emulation write to a
> page which QEMU has marked read-only because of cached TCG
> translations, the threads can race in page_unprotect:
>
> * threads A & B both try to do a write t
On Fri, Mar 09, 2018 at 14:29:22 +0100, Paolo Bonzini wrote:
> Actually enable the global memory barriers if supported by the OS.
> Because only recent versions of Linux include the support, they
> are disabled by default. Note that it also has to be disabled
> for QEMU to run under Wine.
>
> Bef
Emilio G. Cota writes:
> Performance results for fp-bench run under aarch64-linux-user
> on an Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz host:
>
> - before:
> sqrt-single: 13.23 MFlops
> sqrt-double: 13.24 MFlops
>
> - after:
> sqrt-single: 15.02 MFlops
> sqrt-double: 15.07 MFlops
>
> Note that s
On Fri, Mar 09, 2018 at 14:29:18 +0100, Paolo Bonzini wrote:
> I didn't have time to check whether it improves performance (not
> too likely, since QEMU tends to have pretty long RCU critical
> sections), but it cannot hurt either. :)
Sorry it took me more than a week to go through this, I was bus
Hi
On Wed, Mar 21, 2018 at 9:33 PM, Eric Blake wrote:
> On 03/21/2018 03:09 PM, Dr. David Alan Gilbert wrote:
>
So the parsing job and the dispatching job is isolated now. It gives us
a chance in following up patches to totally move the parser outside.
The isolation is d
Hi,
This series failed docker-quick@centos6 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180321115211.17937-1-marcandre.lur...@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/49]
On 03/21/2018 04:10 PM, Yuval Shaia wrote:
Hi all,
Following are three patches which fixes various compilation warnings and
errors detected when compiling rdma device in 32bit host.
All three patches are based on Eric Blake patch for rdma device.
Thanks!
Patch #1: Change host_virt to void *
Low
On 03/21/2018 02:42 PM, Dr. David Alan Gilbert wrote:
* Stefan Berger (stef...@linux.vnet.ibm.com) wrote:
Extend the docs related to TPM with specs related to VM save and
restore and a troubleshooting guide for TPM migration.
Signed-off-by: Stefan Berger
This seems ok, so:
Reviewed-by: Dr. D
On Wed, Mar 21, 2018 at 03:58:05PM -0500, Eric Blake wrote:
> On 03/21/2018 03:44 PM, Kevin Wolf wrote:
> >>>
> >>>You're right that file locking on a character device like /dev/null is
> >>>not going to work as expected, but is it a case where fcntl() actually
> >>>fails, or is it worse where the
./check -v -raw
Failures: 109 132 136 148 152 183
3fd2457d18edf5736f713dfe1ada9c87a9badab1 is the first bad commit
commit 3fd2457d18edf5736f713dfe1ada9c87a9badab1
Author: Peter Xu
Date: Fri Mar 9 17:00:03 2018 +0800
monitor: enable IO thread for (qmp & !mux) typed
Start to use dedicat
On 03/21/2018 01:14 PM, Dr. David Alan Gilbert wrote:
* Stefan Berger (stef...@linux.vnet.ibm.com) wrote:
+
+if (totlength > 0) {
+tsb->buffer = g_try_malloc(totlength);
+if (!tsb->buffer) {
+error_report("tpm-emulator: Out of memory allocating %u bytes",
+
On 03/21/2018 04:04 PM, Dr. David Alan Gilbert wrote:
* Stefan Berger (stef...@linux.vnet.ibm.com) wrote:
This series of patches implements support for migrating the state of the
external 'swtpm' TPM emulator as well as that of the TIS interface.
For testing of TPM 2 (migration) please use the
On Wed, Mar 21, 2018 at 21:41:19 +0100, Laurent Vivier wrote:
> Le 21/03/2018 à 21:11, Emilio G. Cota a écrit :
> > diff --git a/target/m68k/Makefile.objs b/target/m68k/Makefile.objs
> > index ac61948..2868b11 100644
> > --- a/target/m68k/Makefile.objs
> > +++ b/target/m68k/Makefile.objs
> > @@ -1,
On Wed, Mar 21, 2018 at 05:22:07PM +0200, Michael S. Tsirkin wrote:
> Our rule right now is to use <> for external headers only.
> RDMA code violates that, fix it up.
>
> Signed-off-by: Michael S. Tsirkin
Thanks.
Reviewed-by: Yuval Shaia
> ---
> hw/rdma/rdma_backend.h| 2 +-
> hw/rd
Hi all,
Following are three patches which fixes various compilation warnings and
errors detected when compiling rdma device in 32bit host.
All three patches are based on Eric Blake patch for rdma device.
Thanks!
Patch #1: Change host_virt to void *
Low level IB verbs library accept void * argumen
Use the correct printf formats, so that a 32-bit compile doesn't spit
out lots of warnings about %lx being incompatible with uint64_t.
Suggested-by: Eric Blake
Signed-off-by: Yuval Shaia
---
hw/rdma/rdma_backend.c| 21 +++--
hw/rdma/rdma_rm.c | 4 ++--
hw/rd
Macro should not cast the given variable to u64 instead it should use
the supplied format argument (fmt).
Reported-by: Eric Blake
Signed-off-by: Yuval Shaia
---
hw/rdma/rdma_backend.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/rdma/rdma_backend.c b/hw/rdma/rdma_b
To avoid compilation warnings on 32-bit machines:
rdma_backend.c: In function 'rdma_backend_create_mr':
rdma_backend.c:409:37: error: cast to pointer from integer of different
size [-Werror=int-to-pointer-cast]
mr->ibmr = ibv_reg_mr(pd->ibpd, (void *)addr, length, access);
Reported-by: Eri
mtval/stval must be set on all exceptions but zero is
a legal value if there is no exception specific info.
Placing the instruction bytes for illegal instruction
exceptions in mtval/stval is an optional feature and
is currently not supported by QEMU RISC-V.
Cc: Sagar Karandikar
Cc: Bastian Koppel
These fields are marked WARL in the specification so illegal
writes are silently dropped.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 26 +-
1 file changed, 13 insertions(+), 13 d
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1dcbdbe..cd337ab 100644
--- a/target/riscv/cpu.h
+
Pointless indirection. Other ports use EM_ constants directly.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 2 +-
hw
Some changes were delivered a few weeks ago that fixed CVE-2018-7550
before that CVE was created. Changeset:
2a8fcd119eb7 ("multiboot: bss_end_addr can be zero")
Shortly after that delivery, a different changeset claimed in its commit
message to fix that CVE, but it really fixed a different o
On 03/21/2018 03:44 PM, Kevin Wolf wrote:
You're right that file locking on a character device like /dev/null is
not going to work as expected, but is it a case where fcntl() actually
fails, or is it worse where the fcntl() claiming the locks "succeeds"
but doesn't do what we want? That is, wha
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 3a
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
Signed-off-by: Michael Clark
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 808eab7..c3a029a 100644
--- a/target/riscv/translate.
This empty commit documents multiboot.c as fixed against CVE-2018-7550.
The fix, dated Dec 21 2017, went in before the CVE was created, as:
2a8fcd119eb7 ("multiboot: bss_end_addr can be zero")
Fixes: CVE-2018-7550
Signed-off-by: Jack Schwartz
Reviewed-by: Mark Kanda
--
1.8.3.1
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
ind
- Model borrowed from target/sh4/cpu.c
- Rewrote riscv_cpu_list to use object_class_get_list
- Dropped 'struct RISCVCPUInfo' and used TypeInfo array
- Replaced riscv_cpu_register_types with DEFINE_TYPES
- Marked base class as abstract
Cc: Igor Mammedov
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Remove a potential buffer overflow (not seen in practice).
Perhaps cpu_physical_memory_write already has bound checks.
This change however makes space for the maximum device tree
size and adds an explicit bounds check and error message.
It doesn't trigger, but it may help in the future if the
devic
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/ri
After reading cpu_physical_memory_write and friends, it seems
that memory_region_is_ram is a more appropriate interface,
and matches the intent of the code that is calling it.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/ris
The sifive_u machine already marks its ROM readonly. This fixes
the remaining boards.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 9 +
hw/riscv/spike.c | 18 ++
hw/riscv/
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.
It seems the RISC-V WARL behaviour is preferred to having to
trap overhead versus simply reading back the value and checking
if the write took (saves hundreds of cycles and
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_clint.c | 9 ++
This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe
This is essentially dead-code elimination. Support for more
local interrupts will be added in a future revision, as they
will be defined in a future version of the Privileged ISA
specification.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbel
- Inline PTE_TABLE check for better readability
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Set READ flag for PTE X flag if mstatus.mxr is in effect
- Change access ch
create_fdt sets the fdt variable on RISCVVirtState and this is
used to access the fdt. This reverts a change introduced in
https://github.com/riscv/riscv-qemu/pull/109 which introduced
a redundant return value, overlooking the RISCVVirtState
structure member that made create_fdt inconsistent with t
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification
defines the canonical order for extensions in the ISA string. It is
silent on the position of the E extension however E is a substitute
for I so it must come early in the extension list order. A comment
is added to state E and I
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unne
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/riscv/spike.h | 4 ++--
include/hw/riscv/virt.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/
Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/virt.c | 4 ++--
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
The following changes since commit f1a63fcfcd92c88be8942b5ae71aef9749a4f135:
Update version for v2.12.0-rc0 release (2018-03-20 19:04:22 +)
are available in the git repository at:
https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-2.12-
This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Am 21.03.2018 um 14:48 hat Pino Toscano geschrieben:
> On Wednesday, 21 March 2018 14:45:38 CET Eric Blake wrote:
> > [adding qemu lists]
> >
> > On 03/21/2018 07:51 AM, Richard W.M. Jones wrote:
> > > On Wed, Mar 21, 2018 at 01:44:17PM +0100, Pino Toscano wrote:
> > >> Newer versions of qemu use
Le 21/03/2018 à 21:11, Emilio G. Cota a écrit :
> The appended paves the way for leveraging the host FPU for a subset
> of guest FP operations. For most guest workloads (e.g. FP flags
> aren't ever cleared, inexact occurs often and rounding is set to the
> default [to nearest]) this will yield siza
Am 21.03.2018 um 21:26 hat Eric Blake geschrieben:
> On 03/21/2018 03:01 PM, John Snow wrote:
> > Adjust each caller of raw_open_common to specify if they are expecting
> > host and character devices or not. Tighten expectations of file types upon
> > open in the common code and refuse types that a
On 03/21/2018 03:09 PM, Dr. David Alan Gilbert wrote:
So the parsing job and the dispatching job is isolated now. It gives us
a chance in following up patches to totally move the parser outside.
The isolation is done using one QEMUBH. Only one dispatcher QEMUBH is
used for all the monitors.
On Wed, Mar 21, 2018 at 08:07:54PM +, Moger, Babu wrote:
>
> > -Original Message-
> > From: Eduardo Habkost
> > Sent: Wednesday, March 21, 2018 1:15 PM
> > To: Moger, Babu
> > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > Lendacky, Thomas ; Singh, Brijesh
> > ; k
On 03/21/18 20:47, Corey Minyard wrote:
> Could someone create a wiki account for me so I can update the changlog?
I've created the account and am about to send the credentials to Corey
off-list. Just posting this notice to synchronize with other wiki users
reading this list.
Thanks
Laszlo
Performance improvement for SPEC06fp for the last few commits:
qemu-aarch64 SPEC06fp (test set) speedup over
QEMU f6d81cdec8
Host: Intel(R) Core(TM) i7-6700K CPU @
4.00GHz
error bars:
On 03/21/2018 04:25 PM, Kevin Wolf wrote:
> Am 21.03.2018 um 21:01 hat John Snow geschrieben:
>> Adjust each caller of raw_open_common to specify if they are expecting
>> host and character devices or not. Tighten expectations of file types upon
>> open in the common code and refuse types that ar
The appended paves the way for leveraging the host FPU for a subset
of guest FP operations. For most guest workloads (e.g. FP flags
aren't ever cleared, inexact occurs often and rounding is set to the
default [to nearest]) this will yield sizable performance speedups.
The approach followed here av
On 03/21/2018 03:01 PM, John Snow wrote:
Adjust each caller of raw_open_common to specify if they are expecting
host and character devices or not. Tighten expectations of file types upon
open in the common code and refuse types that are not expected.
This has two effects:
(1) Character and bloc
Am 21.03.2018 um 21:01 hat John Snow geschrieben:
> Adjust each caller of raw_open_common to specify if they are expecting
> host and character devices or not. Tighten expectations of file types upon
> open in the common code and refuse types that are not expected.
>
> This has two effects:
>
> (
Performance results for fp-bench run under aarch64-linux-user
on an Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz host:
- before:
sqrt-single: 13.23 MFlops
sqrt-double: 13.24 MFlops
- after:
sqrt-single: 15.02 MFlops
sqrt-double: 15.07 MFlops
Note that sqrt in soft-ft is relatively fast, which means
On Wed, Mar 21, 2018 at 07:57:29PM +0300, Roman Kagan wrote:
> On Wed, Mar 21, 2018 at 02:18:54PM +0100, Vitaly Kuznetsov wrote:
> > Roman Kagan writes:
> >
> > > On Tue, Mar 20, 2018 at 06:35:00PM +0100, Vitaly Kuznetsov wrote:
> > >> Requiring tsc_is_stable_and_known() is too restrictive: even
Performance results for fp-bench run under aarch64-linux-user
on an Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz host:
- before:
div-single: 29.77 MFlops
div-double: 29.85 MFlops
- after:
div-single: 85.90 MFlops
div-double: 86.10 MFlops
Signed-off-by: Emilio G. Cota
---
include/fpu/hostfloat.h |
Note that special-casing "a_is_zero || b_is_zero" pays off--see
the last patch in this series for performance numbers on that.
Performance results for fp-bench run under aarch64-linux-user
on an aarch64 host:
- before:
fma-single: 53.05 MFlops
fma-double: 51.89 MFlops
- after:
fma-single: 113.93
On Tue, Feb 20, 2018 at 21:01:37 +, Alex Bennée wrote:
> This is an attempt to save some of the cost of sqrt by using the
> inbuilt support of the host hardware. The idea is assuming we start
> with a valid input we can use the hardware. If any tininess issues
> occur this will trip and FPU exc
These are a few muladd-related operations that the original IBM syntax
does not specify; model files for these are in muladd.fptest.
Signed-off-by: Emilio G. Cota
---
tests/fp-test/fp-test.c | 24 +
tests/fp-test/muladd.fptest | 51
This paves the way for upcoming work.
Signed-off-by: Emilio G. Cota
---
include/fpu/softfloat.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 36626a5..7b9d31c 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloa
This will allow us to measure the performance impact of FP
emulation optimizations.
Signed-off-by: Emilio G. Cota
---
tests/fp-bench.c | 290 +
tests/.gitignore | 1 +
tests/Makefile.include | 3 +-
3 files changed, 293 insertions(+
Performance results included in the following commit's log.
Signed-off-by: Emilio G. Cota
---
include/fpu/hostfloat.h | 4
include/fpu/softfloat.h | 6 ++
fpu/hostfloat.c | 36
fpu/softfloat.c | 34 --
This series is a first stab at (1) having a test suite for our floating
point (FP) implementation, and (2) leveraging the host FPU to speed up
guest FP operations whenever possible.
- Patch 1 is a set of simple microbenchmarks to isolate the performance
of particular FP operations.
- Patch 2 ad
This will allow us to run correctness tests against our
FP implementation. The test can be run in two modes (called
"testers"): host and soft. With the former we check the results
and FP flags on the host machine against the model.
With the latter we check QEMU's fpu primitives against the
model. N
Before 8936006 ("fpu/softfloat: re-factor minmax", 2018-02-21),
we used to return +Zero for maxnummag(-Zero,+Zero); after that
commit, we return -Zero.
Fix it by making {min,max}nummag consistent with {min,max}num,
deferring to the latter when the absolute value of the operands
is the same.
With
Performance results (single and double precision) for
fp-bench run under aarch64-linux-user on an Intel(R)
Core(TM) i7-4790K CPU @ 4.00GHz host:
- before:
add-single: 86.74 MFlops
add-double: 86.46 MFlops
sub-single: 83.33 MFlops
sub-double: 84.57 MFlops
- after:
add-single: 188.26 MFlops
add-dou
This paves the way for upcoming work.
Signed-off-by: Emilio G. Cota
---
include/fpu/softfloat.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 7b9d31c..8fb44a8 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloa
Note that special-casing "a_is_zero || b_is_zero" pays off--see
the last patch in this series for performance numbers on that.
Performance results for fp-bench run under aarch64-linux-user
on an Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz host:
- before:
mul-single: 86.17 MFlops
mul-double: 87.74 MF
* Marc-André Lureau (marcandre.lur...@gmail.com) wrote:
> Hi
>
> On Fri, Mar 9, 2018 at 9:59 AM, Peter Xu wrote:
> > Originally QMP goes through these steps:
> >
> > JSON Parser --> QMP Dispatcher --> Respond
> > /|\(2)(3) |
> >(1) |
> -Original Message-
> From: Eduardo Habkost
> Sent: Wednesday, March 21, 2018 1:15 PM
> To: Moger, Babu
> Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> Lendacky, Thomas ; Singh, Brijesh
> ; k...@vger.kernel.org; k...@tripleback.net;
> mtosa...@redhat.com; Hook, Gary ;
On Wed, Mar 21, 2018 at 08:17:55PM +0300, Roman Kagan wrote:
> On Wed, Mar 21, 2018 at 05:17:38PM +0100, Vitaly Kuznetsov wrote:
> > (What I'm worried about with all our hv_* knobs is that more of them we
> > have easier it is to assemble some frankenstien which won't look like
> > any existing Hyp
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