On 07.02.2018 18:50, Luiz Capitulino wrote:
> The query-cpus command has an extremely serious side effect:
> it always interrupt all running vCPUs so that they can run
> ioctl calls. This can cause a huge performance degradation for
> some workloads. And most of the information retrieved by the
> i
On Wed, Feb 7, 2018 at 12:38 PM, Pavel Dovgalyuk wrote:
> > From: Ciro Santilli [mailto:ciro.santi...@gmail.com]
> > Can you provide a test branch somewhere so I can easily test it out?
>
> Here it is: https://github.com/ispras/qemu/tree/rr-180207
>
> Pavel Dovgalyuk
>
> Awesome! This worked with
The patch has been merged here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=0cb57cc701839e7358918
** Changed in: qemu
Status: New => Fix Committed
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On Wed, Jan 24, 2018 at 01:39:34PM +0800, Peter Xu wrote:
> This version should have addressed all comments in previous one, also
> fixed another race condition after I addressed all the comments (a new
> race condition introduced by addressing the comments...). For some
> more details of the race
This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The
differences to Pi 2 are:
- Firmware address
- Board ID
- Board revision
The CPU is different too, but that's going to be configured as part of
the machine default CPU when we introduce a new machine type.
The patch was written from
This patch adds a "raspi3" machine type, which can now be selected as
the machine to run on by users via the "-M" command line option to QEMU.
The machine type does *not* ignore memory transaction failures so we
likely need to add some dummy devices later when people run something
more complicated
This patch series adds support for Raspberry Pi 3 as a new machine model
"raspi3", which is an extension of the "raspi2" model with the following
differences:
- Default CPU type is "cortex-a53"
- Firmware is at address 0x8
- Board ID is 0xc44 and board revision is 0xa02082
The patches w
On 02/07/2018 08:02 AM, Michael S. Tsirkin wrote:
On Tue, Feb 06, 2018 at 07:08:16PM +0800, Wei Wang wrote:
This is the deivce part implementation to add a new feature,
VIRTIO_BALLOON_F_FREE_PAGE_HINT to the virtio-balloon device. The device
receives the guest free page hints from the driver and
Finally I could test it. Yeah man, awesome, that did the trick. It is working
like a charm.
You can close the ticket.
Thanks
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https://bugs.launchpad.net/bugs/1739378
Title:
migration
The following changes since commit 20e0d439a6ded635ec89f6135c08cd5541c68962:
Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20180204' into
staging (2018-02-06 14:21:41 +)
are available in the git repository at:
git://repo.or.cz/qemu/armbru.git tags/pull-misc-2018-02-07-v2
for
Markus Armbruster writes:
> This cleanup makes the number of objects depending on qapi/qmp/qdict.h
> drop from 4550 (out of 4743) to 368 in my "build everything" tree.
> For qapi/qmp/qobject.h, the number drops from 4552 to 390.
>
> While there, separate #include from file comment with a blank li
On 01/02/18 20:36, Alexey Kardashevskiy wrote:
> If we run QEMU with -netdev user,id=USER0,hostfwd=tcp::-:22, it starts
> a DHCP server and starts allocating client IPs from 10.0.2.15 so
> this is what the guest normally receives. Since QEMU automatically adds
> the DHCP starting address into t
On 02/02/18 13:45, Alexey Kardashevskiy wrote:
> On 29/01/18 16:03, Alexey Kardashevskiy wrote:
>> On 15/12/17 15:47, Alexey Kardashevskiy wrote:
>>> On 26/10/17 12:41, Alexey Kardashevskiy wrote:
The "-machine xxx,help" prints kernel-irqchip possible values as
"OnOffSplit", this adds sep
On 02/07/2018 07:57 AM, Michael S. Tsirkin wrote:
On Tue, Feb 06, 2018 at 07:08:18PM +0800, Wei Wang wrote:
Use the free page reporting feature from the balloon device to clear the
bits corresponding to guest free pages from the dirty bitmap, so that the
free memory are not sent.
Signed-off-by:
To make our efforts on QEMU testing easier to consume by contributors,
let's add a document. For example, Patchew reports build errors on
patches that should be relatively easy to reproduce with a few steps, and
it is much nicer if there is such a documentation that it can refer to.
This focuses o
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Message-Id: <20180116060901.17413-9-f...@redhat.com>
Signed-off-by: Fam Zheng
---
docs/qemu-block-drivers.texi | 37 +
qemu-doc.texi| 1 +
2 files changed, 38 insertions(+)
diff --git a/d
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Message-Id: <20180116060901.17413-7-f...@redhat.com>
Signed-off-by: Fam Zheng
---
qemu-img.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/qemu-img.c b/qemu-img.c
index 68b375f998..28d0e4e9f8 100644
--- a/qemu-i
This is a new protocol driver that exclusively opens a host NVMe
controller through VFIO. It achieves better latency than linux-aio by
completely bypassing host kernel vfs/block layer.
$rw-$bs-$iodepth linux-aio nvme://
randread-4k-1 10
Allow block driver to map and unmap a buffer for later I/O, as a performance
hint.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Message-Id: <20180116060901.17413-5-f...@redhat.com>
Signed-off-by: Fam Zheng
---
block/block-backend.c | 10 ++
block/io.c
This is a library to manage the host vfio interface, which could be used
to implement userspace device driver code in QEMU such as NVMe or net
controllers.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Message-Id: <20180116060901.17413-3-f...@redhat.com>
Signed-off-by: Fam Zheng
---
in
These functions will be wanted by block-obj-y but the actual definition
is in obj-y, so stub them to keep the linker happy.
Signed-off-by: Fam Zheng
Acked-by: Paolo Bonzini
Message-Id: <20180110091846.10699-2-f...@redhat.com>
Reviewed-by: Stefan Hajnoczi
---
stubs/Makefile.objs | 1 +
stubs/r
On Wed, 02/07 15:31, Paolo Bonzini wrote:
> On 01/02/2018 03:20, Fam Zheng wrote:
> > To make our efforts on QEMU testing easier to consume by contributors,
> > let's add a document. For example, Patchew reports build errors on
> > patches that should be relatively easy to reproduce with a few step
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Message-Id: <20180116060901.17413-8-f...@redhat.com>
Signed-off-by: Fam Zheng
---
block/nvme.c | 7 +-
hw/block/nvme.h | 698 +-
include/block/nvme.h | 700 ++
From: Paolo Bonzini
qemu_co_queue_next does not need to release and re-acquire the mutex,
because the queued coroutine does not run immediately. However, this
does not hold for qemu_co_enter_next. Now that qemu_co_queue_wait
can synchronize (via QemuLockable) with code that is not running in
co
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1518053328-34687-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total
Forward these two calls to the IOVA manager.
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Message-Id: <20180116060901.17413-6-f...@redhat.com>
Signed-off-by: Fam Zheng
---
block/nvme.c | 24
1 file changed, 24 insertions(+)
diff --git a/block/nvme.c b/block/n
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Message-Id: <20180116060901.17413-10-f...@redhat.com>
Signed-off-by: Fam Zheng
---
qapi/block-core.json | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/qapi/block-core.json b/qapi/block-core.json
index 8
From: Paolo Bonzini
QemuLockable is a polymorphic lock type that takes an object and
knows which function to use for locking and unlocking. The
implementation could use C11 _Generic, but since the support is
not very widespread I am instead using __builtin_choose_expr and
__builtin_types_compati
From: Paolo Bonzini
Using "fedora:latest" makes behavior different depending on when you
actually pulled the image from the docker repository. In my case,
the supposedly "latest" image was a Fedora 25 download from 8 months
ago, and the new "test-debug" test was failing.
Use "27" to improve rep
From: Paolo Bonzini
Now that CoQueues can use a QemuMutex for thread-safety, there is no
need for curl to roll its own coroutine queue. Coroutines can be
placed directly on the queue instead of using a list of CURLAIOCBs.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
Message-Id: <
From: Paolo Bonzini
There are cases in which a queued coroutine must be restarted from
non-coroutine context (with qemu_co_enter_next). In this cases,
qemu_co_enter_next also needs to be thread-safe, but it cannot use
a CoMutex and so cannot qemu_co_queue_wait. Use QemuLockable so
that the CoQu
From: Paolo Bonzini
In preparation for adding a similar test using QemuLockable, add a very
simple testcase that has two interleaved calls to lock and unlock.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
Message-Id: <20180203153935.8056-2-pbonz...@redhat.com>
Reviewed-by: Richard
The following changes since commit 7b213bb4755dc99e447c19c532768ef5105b9771:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2018-02-07 20:40:36 +)
are available in the Git repository at:
git://github.com/famz/qemu.git tags/staging-pull-request
for you to
On Wed, Feb 7, 2018 at 4:03 AM, Igor Mammedov wrote:
> On Tue, 6 Feb 2018 11:09:56 +1300
> Michael Clark wrote:
>
> > On Tue, Feb 6, 2018 at 4:04 AM, Igor Mammedov
> wrote:
> >
> > > On Mon, 5 Feb 2018 19:22:28 +1300
> > > Michael Clark wrote:
> > >
> > > > Add CPU state header, CPU definitio
We are now passing all but one of the set of tests cases in riscv-tests.
The one failing set of tests relates to support for "9.2 NaN Boxing of
Narrower Values" as per the RISC-V ISA Specification v2.2. The remaining
case is where we try to use a single-precision operation on an input that
doesn't
To paraphrase; the case we are failing on is a corner case, where a
register containing a double is used as input to a single precision op. It
won't happen in correct code.
On Thu, Feb 8, 2018 at 2:55 PM, Michael Clark wrote:
> We are now passing all but one of the set of tests cases in riscv-te
On Wed, 02/07 17:36, Paolo Bonzini wrote:
> The next patch will introduce a different unrealize implementation
> for scsi-block. Compared to the code before commit fb7b5c0df6
> ("scsi: devirtualize unrealize of SCSI devices", 2014-10-31), the
> common code for all SCSI devices is kept in scsi-bus.
Test finisher memory mapped device used to exit simulation.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_test.c | 99 ++
include/hw/riscv/sifive_test.h | 48
2 files changed, 147 insertions(+)
create mode 100644 hw/riscv/s
This provides a RISC-V Board compatible with the the SiFive U500 SDK.
The following machine is implemented:
- 'sifive_u500'; CLINT, PLIC, UART, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/sifive_u500.c | 338 +
include/hw/riscv/sifive_u5
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.
The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/seri
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 312
include/hw/riscv/sifive_clint.h | 56 ++
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 554 +
include/hw/riscv/sifive_plic.h | 91 ++
This adds RISC-V into the build system enabling the following targets:
- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user
This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
scri
Holds the state of a heterogenous array of RISC-V hardware threads.
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 95 +++
include/hw/riscv/riscv_hart.h | 45
2 files changed, 140 insertions(+)
create mode 100644 hw/
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
RISC-V code generator has complete coverage for the Base ISA v2.2,
Privileged ISA v1.9.1 and Privileged ISA v1.10:
- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privile
This provides a RISC-V Board compatible with the the SiFive E300 SDK.
The following machine is implemented:
- 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e300.c | 232 +
include/hw/riscv/
Implementation of linux user emulation for RISC-V.
Signed-off-by: Michael Clark
---
linux-user/elfload.c | 22 +++
linux-user/main.c | 97 +
linux-user/riscv/syscall_nr.h | 287 ++
linux-user/riscv/target_cpu.h
I've included this patch in the RISC-V patch series just submitted.
The change is enclosed within a simple conditional so there is no risk of
affecting any other ports.
There was one line whitespace fix to the pre-existing code however it fell
nicely within the diff hunk so I included the fix.
O
Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.
PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
The SiFive verification team have PMP test cases that will be run.
Nothing currently depends on PMP support. It would be prefera
The RISC-V disassembler has no dependencies outside of the 'disas'
directory so it can be applied independently. The majority of the
disassembler is machine-generated from instruction set metadata:
- https://github.com/michaeljclark/riscv-meta
Expected checkpatch errors for consistency and brevit
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:
- 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10
Signed-off-by: Mi
On Wed, 02/07 17:36, Paolo Bonzini wrote:
> scsi-block bypasses the dirty bitmaps and pre-write notifiers, so it
> cannot be the source of a block job. The gist of the fix is to add
> op-blockers to the BlockBackend, and remove them at "unrealize" time,
> but things are a little more complex becau
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
allows identical copies of BBL (Berkeley Boot Loader) and linux to run
on both Spike and QEMU. BBL provides HTIF console access via the
SBI (Supervisor Binary Interface) and the linux kernel SBI console.
The HTIF interface read
Helper routines for FPU instructions and NaN definitions.
Signed-off-by: Michael Clark
---
fpu/softfloat-specialize.h | 7 +-
target/riscv/fpu_helper.c | 375 +
2 files changed, 379 insertions(+), 3 deletions(-)
create mode 100644 target/riscv/fpu_
GDB Register read and write routines.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/gdbstub.c | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_prci.c | 95 ++
include/hw/riscv/sifive_prci.h | 43 +++
2 files changed, 138
QEMU currently implements IEEE 754-2008 minNum/maxNum. This patch adds
support for IEEE 754-201x minimumNumber/maximumNumber which is required
by the RISC-V port.
minNum(x, y) is defined as
- min(x, y) if neither is NaN
- if one of x and y is a number and one is qNaN, return the number
- if both a
Privileged control and status register helpers and page fault handling.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 464 ++
target/riscv/helper.h| 78 ++
target/riscv/op_helper.c | 644 ++
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Michael Clark
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 375
include/hw/riscv/virt
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Michael Clark
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
Add CPU state header, CPU definitions and initialization routines
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 385
target/riscv/cpu.h | 256 +
target/riscv/cpu_bits.h | 41
QEMU RISC-V Emulation Support (RV64GC, RV32GC)
This version of the RISC-V patch series "lucky number five" contains
cleanups to the FPU code, fixes several FPU related test failures in
riscv-tests and updates the syscalls for RISC-V linux-user emulation.
The git tree for this v5 patch series (squ
> On Wed, Jan 31, 2018 at 11:57:45PM +0800, Luwei Kang wrote:
> > From: Chao Peng
> >
> > Expose Intel Processor Trace feature to guest.
> >
> > To make Intel PT live migration safe and get same CPUID information
> > with same CPU model on diffrent host. CPUID[14] is constant in this
> > patch. In
On 08/02/18 01:12, Alex Williamson wrote:
> On Wed, 7 Feb 2018 15:48:26 +1100
> Alexey Kardashevskiy wrote:
>
>> On 07/02/18 15:25, Alex Williamson wrote:
>>> On Wed, 7 Feb 2018 15:09:22 +1100
>>> Alexey Kardashevskiy wrote:
On 07/02/18 11:08, Alex Williamson wrote:
> diff --git a/i
On 2/7/2018 8:06 PM, Igor Mammedov wrote:
On Wed, 7 Feb 2018 07:49:58 +
"Tan, Jianfeng" wrote:
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Tuesday, February 6, 2018 1:32 AM
To: Igor Mammedov
Cc: Tan, Jianfeng; qemu-devel@nongnu.org; Jason Wang; Maxim
On Wed, 02/07 17:29, Paolo Bonzini wrote:
> Even if an op blocker is present for BLOCK_OP_TYPE_MIRROR_SOURCE,
> it is checked a bit late and the result is that the target is
> created even if drive-mirror subsequently fails. Add an early
> check to avoid this.
>
> Signed-off-by: Paolo Bonzini
>
On 2/7/2018 7:36, Paolo Bonzini wrote:
Queued, thanks. Sorry for the delay!
That's okay, thanks!
Yu
Paolo
QEMU currently implements IEEE 754-2008 minNum/maxNum. This patch adds
support for IEEE 754-201x minimumNumber/maximumNumber which is required
by the RISC-V port.
minNum(x, y) is defined as
- min(x, y) if neither is NaN
- if one of x and y is a number and one is qNaN, return the number
- if both a
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180207225540.31698-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PULL 00/20] tcg: generic vector operaions
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
tota
On 7 February 2018 at 15:25, Paolo Bonzini wrote:
> The following changes since commit f24ee107a07f093bd7ed475dd48d7ba57ea3d8fe:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/ui-20180202-pull-request'
> into staging (2018-02-02 18:54:11 +)
>
> are available in the git repository at:
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 25 +-
tcg/aarch64/tcg-target.opc.h | 3 +
tcg/aarch64/tcg-target.inc.c | 588 +++
3 files changed, 569 insertions(+), 47 deletions(-)
create mode 100644 tcg/a
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 419 +
1 file changed, 346 insertions(+), 73 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 48088dbb29..5717e85def 10
The x86 vector instruction set is extremely irregular. With newer
editions, Intel has filled in some of the blanks. However, we don't
get many 64-bit operations until SSE4.2, introduced in 2009.
The subsequent edition was for AVX1, introduced in 2011, which added
three-operand addressing, and ad
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 93 +-
1 file changed, 59 insertions(+), 34 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 81 +++---
1 file changed, 33 insertions(+), 48 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 200 +
1 file changed, 128 insertions(+), 72 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 28 +---
1 file changed, 5 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 91f0ab7f12..0830c3f
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
Makefile.target |2 +-
accel/tcg/tcg-runtime.h | 29 +
tcg/tcg-gvec-desc.h | 49 ++
tcg/tcg-op-gvec.h| 198 +++
tcg/tcg-op.h |1 +
tcg/tcg-opc.h|
On 2018-02-07 23:46, Max Reitz wrote:
> On 2018-01-19 21:58, John Snow wrote:
>> We're attempting to slacken the mirror loop in three different places,
>> but we can combine these three attempts. Combine the early loop call to
>> block_job_pause_point with the two late-loop calls to block_job_sleep
Use dup to convert a non-constant scalar to a third vector.
Add addition, multiplication, and logical operations with an immediate.
Add addition, subtraction, multiplication, and logical operations with
a non-constant scalar. Allow for the front-end to build operations in
which the scalar operand
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 42 --
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 5a4e6
Trivial move and constant propagation. Some identity and constant
function folding, but nothing that requires knowledge of the size
of the vector element.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 150 +---
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 154 +
1 file changed, 129 insertions(+), 25 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
No vector ops as yet. SSE only has direct support for 8- and 16-bit
saturation; handling 32- and 64-bit saturation is much more expensive.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 20
tcg/tcg-op-gvec.h| 10 ++
accel/tcg/tcg
Some functions use intN_t arguments, some use uintN_t, some just
used "unsigned". To aid putting function pointers in tables, we
need consistency.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/tcg-op.h | 16
tcg/tcg-op.c | 42 +++
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 5 +
tcg/tcg-op-gvec.h| 2 ++
tcg/tcg-op.h | 1 +
tcg/tcg-opc.h| 1 +
tcg/tcg.h| 1 +
accel/tcg/tcg-runtime-gvec.c | 44 ++
Opcodes are added for scalar and vector shifts, but considering the
varied semantics of these do not expose them to the front ends. Do
go ahead and provide them in case they are needed for backend expansion.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d2bb59eded..8d41f783dc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/
0/qemu.git tags/pull-tcg-20180207
for you to fetch changes up to b63799b11c17e8f1068dbd05c18cbb9c9aa69c56:
tcg/aarch64: Add vector operations (2018-02-07 14:47:50 -0800)
tcg
Nothing uses or enables them yet.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
Makefile.target | 4 +-
tcg/tcg-op.h | 27 +
tcg/tcg-opc.h| 25 +
tcg/tcg.h| 56 +++
tcg/tcg-op-vec.c | 292 +
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 30 +
tcg/tcg-op-gvec.h| 4 ++
tcg/tcg-op.h | 3 +
tcg/tcg-opc.h| 2 +
accel/tcg/tcg-runtime-gvec.c | 36 +++
tcg/tcg-op-gvec.c
This will be required for storing vector constants.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/tcg-pool.inc.c | 115 +++--
1 file changed, 93 insertions(+), 22 deletions(-)
diff --git a/tcg/tcg-p
On 2018-01-19 21:58, John Snow wrote:
> Remove the last call in block/mirror, using relax instead.
> relax may do nothing if we are canceled, so allow iteration to return
> prematurely and allow mirror_run to handle the cancellation logic.
Ah, now you write it with two l? ;-)
>
> This is a funct
On 2018-01-19 21:58, John Snow wrote:
> There's not currently any external caller of it.
>
> Except in tests, but we'll fix that here too.
>
> Replace usages in test cases with block_job_relax, which functions
> similarly enough to be used as a drop-in replacement.
>
> Very technically block_job
On 2018-01-19 21:58, John Snow wrote:
> We're attempting to slacken the mirror loop in three different places,
> but we can combine these three attempts. Combine the early loop call to
> block_job_pause_point with the two late-loop calls to block_job_sleep_ns.
>
> When delay_ns is 0 and it has not
Hi Folks,
I'm currently going through riscv-tests failures in riscv-qemu and we have
an issue with fmin/fmax.
In particular, this test case is failing:
- https://github.com/riscv/riscv-tests/blob/master/isa/rv64uf/fmin.S#L35-L35
The RISC-V port is currently using the solftfloat floatXX_minnum/m
On Wed, Feb 7, 2018 at 10:37 AM, Dr. David Alan Gilbert
wrote:
> * Dan Williams (dan.j.willi...@intel.com) wrote:
>> On Wed, Feb 7, 2018 at 10:08 AM, Dr. David Alan Gilbert
>> wrote:
>> > * Dan Williams (dan.j.willi...@intel.com) wrote:
>> >> On Wed, Feb 7, 2018 at 5:24 AM, Dr. David Alan Gilbert
On 2018-01-19 21:58, John Snow wrote:
> We can count on the relax call to check cancellation for us, so
> condense these concurrent calls.
>
> Signed-off-by: John Snow
> ---
> block/mirror.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/block/mirror.c b/block/
On 2018-01-19 21:58, John Snow wrote:
> This is a respin of the same functionality as mirror_throttle,
> so trash this and replace it with the generic version.
>
> yield_and_check returned true if canceled, false otherwise.
> block_job_relax returns -ECANCELED if canceled, 0 otherwise.
>
> Signed
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