On Wed, 09/13 20:19, Max Reitz wrote:
> Add a new parameter -B to qemu-io's write command. When used, qemu-io
> will not wait for the result of the operation and instead execute it in
> the background.
Cannot aio_write be used for this purpose?
Fam
On Wed, 09/13 20:19, Max Reitz wrote:
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/151 | 111
> +
> tests/qemu-iotests/151.out | 5 ++
> tests/qemu-iotests/group | 1 +
> 3 files changed, 117 insertions(+)
> create mode 100755 tests
Am 18.09.2017 um 07:39 hat Fam Zheng geschrieben:
> On Mon, 09/18 07:18, Kevin Wolf wrote:
> > Am 05.09.2017 um 05:02 hat Fam Zheng geschrieben:
> > > On Fri, 09/01 13:28, Amador Pahim wrote:
> > > > The current message shows 'self._args', which contains only part of the
> > > > options used in the
Hi Philippe,
On Mon, Sep 18, 2017 at 5:27 AM, Philippe Mathieu-Daudé
wrote:
> Hi Sundeep,
>
> On 09/14/2017 01:36 AM, Philippe Mathieu-Daudé wrote:
>
>> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>>
> [...]
>
>> +static inline int msf2_divbits(uint32_t div)
>>>
>>
>> Please directly use ct
On Wed, 09/13 20:18, Max Reitz wrote:
> In order to talk to the source BDS (and maybe in the future to the
> target BDS as well) directly, we need to convert our existing AIO
> requests into coroutine I/O requests.
>
> Signed-off-by: Max Reitz
> ---
> block/mirror.c | 134
>
On Mon, 09/18 07:18, Kevin Wolf wrote:
> Am 05.09.2017 um 05:02 hat Fam Zheng geschrieben:
> > On Fri, 09/01 13:28, Amador Pahim wrote:
> > > The current message shows 'self._args', which contains only part of the
> > > options used in the Qemu command line.
> > >
> > > This patch makes the qemu f
Python requires parentheses around multiline expression. This fixes the
breakage of all Python-based qemu-iotests cases that was introduced in
commit dab91d9aa0.
Signed-off-by: Kevin Wolf
---
Eduardo, I think I'm going to include this patch in a block layer pull
request today, just to stop the C
Am 05.09.2017 um 05:02 hat Fam Zheng geschrieben:
> On Fri, 09/01 13:28, Amador Pahim wrote:
> > The current message shows 'self._args', which contains only part of the
> > options used in the Qemu command line.
> >
> > This patch makes the qemu full args list an instance variable and then
> > use
thanks Peter..
Shannon,
using your launch arguments seems to go as you write..
nice progress..
any info on if running QEMU on Linux will be better right now than
Windows?
as I thought virtio-gpu was for Linux but I'm very new to QEMU so
probably bad knowledge..
also don't know how mature ARM64 p
On Wed, Sep 13, 2017 at 02:09:02PM +0100, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > On Thu, Aug 24, 2017 at 08:27:20PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > Register a waker function in vhost-user code to b
At 09/15/2017 06:05 PM, Dou Liyang wrote:
Hi Daniel,
At 09/15/2017 04:40 PM, Daniel P. Berrange wrote:
On Fri, Sep 15, 2017 at 04:33:18PM +0800, Dou Liyang wrote:
In QEMU, if we enable NUMA and have nodes, QEMU will build ACPI SRAT
table
for transfering NUMA configuration to the guest. So, the
On Wed, 09/13 20:18, Max Reitz wrote:
> When converting mirror's I/O to coroutines, we are going to need a point
> where these coroutines are created. mirror_perform() is going to be
> that point.
>
> Signed-off-by: Max Reitz
> ---
> block/mirror.c | 53 ++---
On Wed, 09/13 20:18, Max Reitz wrote:
> When a block job decides to be represented as a BDS and track its
> associated child nodes itself instead of having the BlockJob object
> track them, it needs to implement the drained_begin/drained_end child
> operations. In order to do that, it has to be ab
On Wed, 09/13 20:18, Max Reitz wrote:
> Drainined a BDS child may lead to both the original BDS and/or its other
> children being deleted (e.g. if the original BDS represents a block
> job). We should prepare for this in both bdrv_drain_recurse() and
> bdrv_drained_begin() by monitoring whether th
On 09/17/2017 02:15 PM, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/mac_oldworld.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index fcac3
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v8 00/13] tests: Add VM based build tests (for
non-x86_64 and/or non-Linux)
Message-id: 20170918024402.3265-1-f...@redhat.com
Type: series
=== TEST SCRIPT BEGIN ===
#!/b
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4bd1797330..e9be7faff7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1890,6 +1890,7 @@ S: Maintained
F: .travis.yml
F: .shippable.yml
F: t
Signed-off-by: Fam Zheng
---
Makefile | 2 ++
configure | 2 +-
tests/vm/Makefile.include | 42 ++
3 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 tests/vm/Makefile.include
diff --git a/Makefile b/Mak
The image is prepared following instructions as in:
https://wiki.qemu.org/Hosts/BSD
Signed-off-by: Fam Zheng
---
tests/vm/openbsd | 43 +++
1 file changed, 43 insertions(+)
create mode 100755 tests/vm/openbsd
diff --git a/tests/vm/openbsd b/tests/vm/ope
This is the common code to implement a "VM test" to
1) Download and initialize a pre-defined VM that has necessary
dependencies to build QEMU and SSH access.
2) Archive $SRC_PATH to a .tar file.
3) Boot the VM, and pass the source tar file to the guest.
4) SSH into the VM, untar the s
Signed-off-by: Fam Zheng
---
tests/docker/Makefile.include | 15 ++-
tests/docker/run | 8 +---
2 files changed, 3 insertions(+), 20 deletions(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index aaab1a4208..7a027d5bd6 100644
--- a/tes
The image is prepared following instructions as in:
https://wiki.qemu.org/Hosts/BSD
Signed-off-by: Fam Zheng
Reviewed-by: Kamil Rytarowski
---
tests/vm/netbsd | 42 ++
1 file changed, 42 insertions(+)
create mode 100755 tests/vm/netbsd
diff --git a/tes
Signed-off-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Alex Bennée
---
scripts/qemu.py | 7 +++
1 file changed, 7 insertions(+)
diff --git a/scripts/qemu.py b/scripts/qemu.py
index 8c67595ec8..774e201e8b 100644
--- a/scripts/qemu.py
+++ b/scripts/qemu.py
@@ -215,6 +215,13 @@ cl
Signed-off-by: Fam Zheng
---
tests/vm/README | 85 +
1 file changed, 85 insertions(+)
create mode 100644 tests/vm/README
diff --git a/tests/vm/README b/tests/vm/README
new file mode 100644
index 00..fa30a79ea7
--- /dev/null
+++ b/t
This will be used by setup test user ssh.
Signed-off-by: Fam Zheng
---
tests/keys/id_rsa | 27 +++
tests/keys/id_rsa.pub | 1 +
2 files changed, 28 insertions(+)
create mode 100644 tests/keys/id_rsa
create mode 100644 tests/keys/id_rsa.pub
diff --git a/tests/keys/
Signed-off-by: Fam Zheng
---
.gitignore | 1 +
tests/.gitignore | 1 +
2 files changed, 2 insertions(+)
diff --git a/.gitignore b/.gitignore
index cf65316863..40acfcb9e2 100644
--- a/.gitignore
+++ b/.gitignore
@@ -52,6 +52,7 @@
/vscclient
/vhost-user-scsi
/fsdev/virtfs-proxy-helper
+*.
The image is prepared following instructions as in:
https://wiki.qemu.org/Hosts/BSD
Signed-off-by: Fam Zheng
---
tests/vm/freebsd | 42 ++
1 file changed, 42 insertions(+)
create mode 100755 tests/vm/freebsd
diff --git a/tests/vm/freebsd b/tests/vm/free
This adds a 32bit guest.
The official LTS cloud image is downloaded and initialized with
cloud-init.
Signed-off-by: Fam Zheng
---
tests/vm/ubuntu.i386 | 88
1 file changed, 88 insertions(+)
create mode 100755 tests/vm/ubuntu.i386
diff --git
Signed-off-by: Fam Zheng
---
scripts/archive-source.sh | 33 +
1 file changed, 33 insertions(+)
create mode 100755 scripts/archive-source.sh
diff --git a/scripts/archive-source.sh b/scripts/archive-source.sh
new file mode 100755
index 00..8b373e3090
--- /
v8: Fix typo in code "od" => "os".
QEMU to listen on 127.0.0.1 to be more secure.
Update README.
v7: Add Alex's rev-by to patch 2.
GPLv2 => GPLv2+ for all new files. [Peter]
Add more description in file header to archive-source.sh for the intended
usage. [Peter]
"output ta
On Sat, Sep 16, 2017 at 04:02:41PM +0200, BALATON Zoltan wrote:
> Resending those patches that were reviewed and did not need any
> changes or only rebasing to latest master so these could go in now.
> I'll get back to the other patches that need more changes later.
Applied to ppc-for-2.11, thanks
On Fri, Sep 15, 2017 at 03:15:51PM +0200, Greg Kurz wrote:
> It never got used since its introduction (commit 7c43bca004af).
>
> Signed-off-by: Greg Kurz
Applied to ppc-for-2.11, thanks.
> ---
> target/ppc/kvm.c |5 -
> target/ppc/kvm_ppc.h |6 --
> 2 files changed, 11 dele
On 09/16/2017 06:03 AM, John Snow wrote:
On 09/15/2017 05:35 PM, John Snow wrote:
On 08/04/2017 06:26 AM, Mao Zhongyi wrote:
Replace init with realize in IDEDeviceClass, which has errp
as a parameter. So all the implementations now use error_setg
instead of error_report for reporting erro
On 09/16/2017 05:35 AM, John Snow wrote:
On 08/04/2017 06:26 AM, Mao Zhongyi wrote:
Replace init with realize in IDEDeviceClass, which has errp
as a parameter. So all the implementations now use error_setg
instead of error_report for reporting error.
Cc: John Snow
Cc: Markus Armbruster
S
Hi Sundeep,
On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:
Hi Qemu-devel,
I am trying to add Smartfusion2 SoC.
SoC is from Microsemi and System on Module(SOM)
board is from Emcraft systems. Smartfusion2 has hardened
Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
At the moment onl
On 2017/9/16 1:33, Halil Pasic wrote:
>
>
> On 09/14/2017 02:58 AM, Longpeng (Mike) wrote:
>>
>>
>> On 2017/9/14 2:14, Halil Pasic wrote:
>>
>>>
>>>
>>> On 09/11/2017 03:10 AM, Longpeng(Mike) wrote:
*NOTE*
The code realization is based on the latest virtio crypto spec:
[PATCH v
On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:
Modelled System Timer in Microsemi's Smartfusion2 Soc.
Timer has two 32bit down counters and two interrupts.
Signed-off-by: Subbaraya Sundeep
Reviewed-by: Alistair Francis
Acked-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:
Modelled Microsemi's Smartfusion2 SPI controller.
Signed-off-by: Subbaraya Sundeep
Reviewed-by: Alistair Francis
Tested-by: Philippe Mathieu-Daudé
On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:
Emulated Emcraft's Smartfusion2 System On Module starter
kit.
Signed-off-by: Subbaraya Sundeep
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:
Smartfusion2 SoC has hardened Microcontroller subsystem
and flash based FPGA fabric. This patch adds support for
Microcontroller subsystem in the SoC.
Signed-off-by: Subbaraya Sundeep
Reviewed-by: Alistair Francis
---
default-configs/arm-softm
Hi Sundeep, Peter,
On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:
Added Sytem register block of Smartfusion2.
This block has PLL registers which are accessed by guest.
Signed-off-by: Subbaraya Sundeep
Reviewed-by: Alistair Francis
---
hw/misc/Makefile.objs | 1 +
hw/misc/msf2-s
Hi Sundeep,
On 09/14/2017 01:36 AM, Philippe Mathieu-Daudé wrote:
On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
[...]
+static inline int msf2_divbits(uint32_t div)
Please directly use ctz32() instead of msf2_divbits()
It seems you missed this review comment in your v9.
+{
+ int r
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v3 0/6] QOMify MIPS cpu
Message-id: 20170917232010.14183-1-f4...@amsat.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BA
and clean every implementation.
Suggested-by: Eduardo Habkost
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: 20170917232010.14183-7-f4...@amsat.org
qom/cpu.c | 7 ++-
target/alpha/cpu.c | 6 +-
target/arm/cpu.c | 4
target/cris/cpu.c | 4
targ
From: Igor Mammedov
now cpu_mips_init() reimplements subset of cpu_generic_init()
tasks, so just drop it and use cpu_generic_init() directly.
Signed-off-by: Igor Mammedov
Reviewed-by: Hervé Poussineau
Signed-off-by: Philippe Mathieu-Daudé
[PMD: use internal.h instead of cpu.h]
Tested-by: Jame
From: Igor Mammedov
Register separate QOM types for each mips cpu model,
so it would be possible to reuse generic CPU creation
routines.
Signed-off-by: Igor Mammedov
Signed-off-by: Philippe Mathieu-Daudé
[PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass,
mark MIPSCPU abstract, a
This changes the order between cpu_mips_realize_env() and
cpu_exec_initfn(), but cpu_exec_initfn() don't have anything that
depends on cpu_mips_realize_env() being called first.
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Igor Mammedov
Tested-by: James Hogan
Reviewed-by: Eduardo Habkost
-
This timer is a required part of the MIPS32/MIPS64 System Control coprocessor
(CP0). Moving it with the other architecture related files will allow an opaque
use of CPUMIPSState* in the next commit (introduce "internal.h").
also remove it from 'user' targets, remove an unnecessary include.
Signed
Hi,
This series is based on Igor's "complete cpu QOMification" [1] but only modify
the MIPS part. Igor posted an updated series [2].
Yongbok: this series is now ready to apply to your MIPS tree :)
Regards,
Phil.
[1]: http://lists.nongnu.org/archive/html/qemu-devel/2017-07/msg04414.html
[2]: ht
no logical change, only code movement (and fix a comment typo).
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Igor Mammedov
Tested-by: James Hogan
Acked-by: Eduardo Habkost
---
This patch triggers 3 positive falses from checkpatch:
ERROR: space prohibited after that '&' (ctx:WxW)
#664: FIL
so it can be used in mips_cpu_realizefn() in the next commit
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Igor Mammedov
Tested-by: James Hogan
Reviewed-by: Eduardo Habkost
---
target/mips/internal.h | 1 +
target/mips/translate.c | 19 ---
2 files changed, 13 insertions(
On 09/15/2017 09:20 PM, Eduardo Habkost wrote:
On Wed, Aug 30, 2017 at 07:52:25PM -0300, Philippe Mathieu-Daudé wrote:
while here, move it from translate_init.c to helper.c
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Igor Mammedov
Tested-by: James Hogan
---
target/mips/helper.c
Hi Eduardo,
On 09/15/2017 09:15 PM, Eduardo Habkost wrote:
On Wed, Aug 30, 2017 at 07:52:23PM -0300, Philippe Mathieu-Daudé wrote:
From: Igor Mammedov
Register separate QOM types for each mips cpu model,
so it would be possible to reuse generic CPU creation
routines.
Signed-off-by: Igor Mamm
"D:\Program Files\qemu\qemu-system-aarch64.exe" -device virtio-scsi-
pci,id=scsi -drive if=none,id=cd,file=\path\to\iso -device scsi-
cd,drive=cd,bootindex=0 -m 2048 -cpu cortex-a57 -smp 4 -machine virt
-device virtio-gpu-pci -bios "QEMU_EFI .fd" -device usb-ehci -device
usb-kbd -device usb-mouse -
From: Benjamin Herrenschmidt
We use 900Mhz, otherwise MacOS X 10.5 refuses to install.
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/mac_newworld.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index d466634..c581d96 100
From: Benjamin Herrenschmidt
Some interrupts get triggered before the OS has setup the
right interrupt type. If an edge interrupt is latched that
way, not delivered (still masked), then the interrupt is
changed to level and isn't asserted anymore, it will be
stuck "pending", causing an interrupt
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac_oldworld.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index fcac399..5d1171d 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -380,8 +380,10
Signed-off-by: Mark Cave-Ayland
---
hw/ide/macio.c | 154 +---
1 file changed, 56 insertions(+), 98 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index db5db39..428fbfc 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -255,131 +
From: Benjamin Herrenschmidt
Apple uses an IBM MPIC2A without timers, it has 64 sources.
Signed-off-by: Benjamin Herrenschmidt
---
hw/intc/openpic.c| 35 +++
hw/ppc/mac_newworld.c|2 +-
include/hw/ppc/openpic.h |1 +
3 files changed, 37 ins
From: Benjamin Herrenschmidt
This completely reworks the handling of the control register
according to my understanding of the HW and the spec.
It should (hopefully ... still testing) fix a number of issues
most notably cases of MacOS hanging.
Also update dbdma_unassigned_rw() and dbdma_unassig
Observation of the code shows indicates that several timer fields are
missing from the migration stream.
Signed-off-by: Mark Cave-Ayland
---
hw/intc/openpic.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 10d6e87..debf
From: Benjamin Herrenschmidt
The timing register exists on all variants of MacIO IDE, we just
store and return its value.
The interrupts register only exists on KeyLargo but it doesn't
hurt to have it. The lack of this register causes MacOS X to
hangs under some circumstances.
Both are 32-bit o
Here is the latest set of Mac-related PPC patches based upon Ben's earlier
work to improve MacOS compatibility, with various fixups and other odds and
ends from me.
Note this patch bumps the vmstate_openpic_timer version as it includes extra
fields, however I don't see this currently being an issu
;
> Merge remote-tracking branch
> 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-09-16
> 14:36:16 +0100)
>
> are available in the git repository at:
>
> git://github.com/rth7680/qemu.git tags/pull-tcg-20170917
>
> for you to fetch change
On 09/16/2017 11:22 AM, oscarbg wrote:
> Public bug reported:
>
> Hi,
> recently Windows ARM64 ISOs have been posted on the internet..
> just checked with latest QEMU 2.10 release from
> https://qemu.weilnetz.de/w64/qemu-w64-setup-20170830.exe
> "h:\qemu\qemu-system-aarch64.exe" -boot d -cdrom
There was a potential problem here with an ILP32 host
with 64 host registers.
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 50dfd7c77f..25662c36d4 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -186
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 321 +--
1 file changed, 168 insertions(+), 153 deletions(-)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 8ffc7a7205..879885b68b 100644
--- a/tcg/ppc/tcg-target.i
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 186 +++
1 file changed, 107 insertions(+), 79 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 14599a8685..98a12535a5 100644
--- a/tcg/arm/tcg-target.in
It's not even clear what the interface REG and VAL32 were supposed to mean.
All uses had REG = 0 and VAL32 was the bitset assigned to the destination.
Signed-off-by: Richard Henderson
---
tcg/tcg.h| 1 -
tcg/aarch64/tcg-target.inc.c | 33 +++---
tcg/a
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 282 +++
1 file changed, 151 insertions(+), 131 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 704fcddd9b..150530f30e 100644
--- a/tcg/aarch64/
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 1 -
tcg/mips/tcg-target.inc.c | 47 ---
tcg/tcg.c | 8
3 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/tcg
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.h| 1 -
tcg/aarch64/tcg-target.inc.c | 2 +-
tcg/arm/tcg-target.inc.c | 2 +-
tcg/i386/tcg-target.inc.c| 4 ++--
tcg/mips/tcg-target.inc.c| 2 +-
tcg/ppc/tcg-target.inc.c | 2 +-
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 4
tcg/tcg.c | 2 +-
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 5bf67678d5..006e988788 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -190,10 +190,6 @@ typedef enum
From: Philippe Mathieu-Daudé
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20170912211934.20919-1-f4...@amsat.org>
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.c | 54 -
accel/tcg/user-exec.c | 52
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 2 +
tcg/tcg.c | 227 +-
2 files changed, 226 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index ac941
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target.inc.c | 239 ++---
1 file changed, 137 insertions(+), 102 deletions(-)
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 1da4debbaf..bc673bd8c6 100644
--- a/tcg/sparc/tcg-ta
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Thomas Huth
Message-Id: <20170911213328.9701-5-f4...@amsat.org>
Signed-off-by: Richard Henderson
---
atomic_template.h => accel/tcg/atomic_template.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename atom
From: Philippe Mathieu-Daudé
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20170911213328.9701-4-f4...@amsat.org>
Signed-off-by: Richard Henderson
---
Makefile.target | 2 +-
{tcg => accel/tcg}/tcg-runtime.h | 0
{tcg => accel/tcg}/tcg-runtime
From: Thomas Huth
The header is only used by accel/tcg/cputlb.c so we can
move it to the accel/tcg/ folder, too.
Signed-off-by: Thomas Huth
[PMD: reword commit title to match series]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20170911213328.9701-2-f4...@amsat.org>
Signed-off-by: Richar
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.inc.c | 324 --
1 file changed, 170 insertions(+), 154 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 1c09ec7d5b..ce4030602f 100644
--- a/tcg/mips/tcg-targe
From: Philippe Mathieu-Daudé
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20170911213328.9701-3-f4...@amsat.org>
Signed-off-by: Richard Henderson
---
Makefile.target| 4 ++--
user-exec-stub.c => accel/tcg/user-exec-stub.c | 0
ging (2017-09-16 14:36:16 +0100)
are available in the git repository at:
git://github.com/rth7680/qemu.git tags/pull-tcg-20170917
for you to fetch changes up to 89b2e37e6506d92b00ac478e7953be6ddd7a86a9:
tcg/mips: Fully convert tcg_target_op_def (2017-09-17 06:5
From: Philippe Mathieu-Daudé
This fixes building for ppc64 on ppc32 (changed in 5964fca8a12c):
tcg/ppc/tcg-target.inc.c: In function 'tb_target_set_jmp_target':
include/qemu/compiler.h:86:30: error: static assertion failed: \
"not expecting: sizeof(*(uint64_t *)jmp_addr) > ATOMIC_REG_SIZE"
On 17.09.2017 16:22, Alex Bennée wrote:
>
> Dmitry Osipenko writes:
>
>> On 24.02.2017 14:21, Alex Bennée wrote:
>>> Previously flushes on other vCPUs would only get serviced when they
>>> exited their TranslationBlocks. While this isn't overly problematic it
>>> violates the semantics of TLB fl
Dmitry Osipenko writes:
> On 24.02.2017 14:21, Alex Bennée wrote:
>> Previously flushes on other vCPUs would only get serviced when they
>> exited their TranslationBlocks. While this isn't overly problematic it
>> violates the semantics of TLB flush from the point of view of source
>> vCPU.
>>
>
On 16/09/17 17:46, Peter Maydell wrote:
> This patchset converts a handful of old devices from the old_mmio
> fields in MemoryRegionOps. We don't have very many devices still
> using old_mmio, so it would be nice to get rid of the remainder
> and drop the field entirely at some point.
That remind
On 24.02.2017 14:21, Alex Bennée wrote:
> Previously flushes on other vCPUs would only get serviced when they
> exited their TranslationBlocks. While this isn't overly problematic it
> violates the semantics of TLB flush from the point of view of source
> vCPU.
>
> To solve this we call the cputlb
It's expected behaviour that you don't have any video output, because by
default the "virt" board has no graphics device. Most people use a
serial console here. It should also be possible to set it up with a
virtio gpu graphics device, but I don't know whether Windows supports
that.
--
You receiv
On Wed, Sep 13, 2017 at 02:56:51PM +0200, Greg Kurz wrote:
> On Wed, 13 Sep 2017 22:23:29 +1000
> David Gibson wrote:
>
> [...snip...]
> > > > > Also, if all PHBs are instanciated with index != -1, we're limited to
> > > > > 31.
> > > > > Maybe this could be the default value for the machine pro
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