On 18/08/2017 05:38, Fam Zheng wrote:
> On Thu, 08/17 16:23, Paolo Bonzini wrote:
>>> +if (scsi_sense_matches(r, SENSE_CODE(NO_MEDIUM))) {
>>> +error = ENOMEDIUM;
>>> +} else if (scsi_sense_matches(r, SENSE_CODE(TARGET_FAILURE))) {
>>> +error = ENOMEM;
>>> +
On 08/18/2017 02:57 AM, Laszlo Ersek wrote:
> On 08/18/17 02:16, Laszlo Ersek wrote:
>> On 08/17/17 22:57, Laszlo Ersek wrote:
>>> On 08/04/17 12:49, Paolo Bonzini wrote:
On 04/08/2017 10:36, Hannes Reinecke wrote:
> The LUN0 emulation is just that, an emulation for a non-existing
> LU
Hello QEMU PPC people,
This is v3, it is only a single patch now.
My core objective with this patch is to provide a way for QEMU to configure the
newly writeable KVM capability 'KVM_CAP_PPC_SMT', because without it Power 9
hosts can only run VMs with a single thread per core. (With this capabili
KVM now allows writing to KVM_CAP_PPC_SMT which has previously been
read only. Doing so causes KVM to act, for that VM, as if the host's
SMT mode was the given value. This is particularly important on Power
9 systems because their default value is 1, but they are able to
support values up to 8.
Th
Hi!
We have received a report that qemu cannot handle hundreds of virtio
devices and crashes. I tried qemu with 150 virtio-block devices, 1 CPU and
and 2GB RAM (the exact command line is at the end) and found that it took
more than 5.5GB resident and 9GB virtual memory. Bit weird, I tried
valgrind
Philippe Mathieu-Daudé writes:
> On 08/17/2017 02:55 PM, Alistair Francis wrote:
On 15/08/2017 09:30, Markus Armbruster wrote:
> The stupid fix is to repeat libraries until the link succeeds:
>
> test-util-obj-y = libqemuutil.a libqemustub.a libqemuutil.a
>
> [...]
>
On Fri, Aug 18, 2017 at 12:35:36PM +1000, David Gibson wrote:
> On Tue, Aug 15, 2017 at 02:42:21PM +1000, Sam Bobroff wrote:
> > KVM now allows writing to KVM_CAP_PPC_SMT which has previously been
> > read only. Doing so causes KVM to act, for that VM, as if the host's
> > SMT mode was the given va
> -Original Message-
> From: Auger Eric [mailto:eric.au...@redhat.com]
> Sent: Thursday, August 17, 2017 9:03 PM
> To: Bharat Bhushan ;
> eric.auger@gmail.com; peter.mayd...@linaro.org;
> alex.william...@redhat.com; m...@redhat.com; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: w
> On Aug 15, 2017, at 6:27 PM, Paolo Bonzini wrote:
>
> On 15/08/2017 20:46, Programmingkid wrote:
>>
>>> On Aug 14, 2017, at 2:51 AM, Paolo Bonzini wrote:
>>>
>>> On 13/08/2017 21:13, Programmingkid wrote:
Lately I found out that Windows NT 4.0 seems to work well with the
486 and p
On Thu, Aug 17, 2017 at 06:31:28PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 08/17/2017 04:52 AM, David Gibson wrote:
> > On Tue, Aug 15, 2017 at 05:28:46PM -0300, Daniel Henrique Barboza wrote:
> > > This patch is a follow up on the discussions that started with
> > > Laurent's patch series
On 08/17/2017 02:22 AM, David Hildenbrand wrote:
> Let's do it just like the other architectures. Introduce kvm-stub.c
> for stubs and kvm_s390x.h for the declarations.
>
> Add a fake declaration of struct kvm_s390_irq so we don't need other
> ugly CONFIG_KVM checks.
>
> Change license to GPL2+ a
On Thu, Aug 17, 2017 at 11:40:48AM +0200, Paolo Bonzini wrote:
> On 17/08/2017 07:56, Peter Xu wrote:
> > In vtd_switch_address_space() we did the memory region switch, however
> > it's possible that the caller of it has not taken the BQL at all. Make
> > sure we have it.
> >
> > CC: Paolo Bonzini
On 08/17/2017 02:22 AM, David Hildenbrand wrote:
> Only used in that file.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/cpu.h | 11 ---
> target/s390x/misc_helper.c | 11 +++
> 2 files changed, 11 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson
On 08/17/2017 02:22 AM, David Hildenbrand wrote:
> Only used in that file. Also drop the comment, not really needed.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/cpu.h | 7 ---
> target/s390x/diag.c | 7 +++
> 2 files changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: R
On 08/17/2017 02:22 AM, David Hildenbrand wrote:
> Only used in that file.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/cpu.h| 11 ---
> target/s390x/mem_helper.c | 11 +++
> 2 files changed, 11 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson
On 08/17/2017 02:22 AM, David Hildenbrand wrote:
> Only used in that file.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/cpu.h | 14 --
> target/s390x/excp_helper.c | 14 ++
> 2 files changed, 14 insertions(+), 14 deletions(-)
Reviewed-by: Richard Hen
On 08/17/2017 02:22 AM, David Hildenbrand wrote:
> +const char *cc_name(int cc_op)
While we're changing things up a tich, enum cc_op?
> +{
> +static const char *cc_names[] = {
static const char * const cc_names[]
Otherwise,
Reviewed-by: Richard Henderson
r~
On Thu, 08/17 16:23, Paolo Bonzini wrote:
> > +if (scsi_sense_matches(r, SENSE_CODE(NO_MEDIUM))) {
> > +error = ENOMEDIUM;
> > +} else if (scsi_sense_matches(r, SENSE_CODE(TARGET_FAILURE))) {
> > +error = ENOMEM;
> > +} else if (scsi_sense_matches(r,
ThrottleGroup is converted to an object. This will allow the future
throttle block filter drive easy creation and configuration of throttle
groups in QMP and cli.
A new QAPI struct, ThrottleLimits, is introduced to provide a shared
struct for all throttle configuration needs in QMP.
ThrottleGroup
This commit eliminates the 1:1 relationship between BlockBackend and
throttle group state. Users will be able to create multiple throttle
nodes, each with its own throttle group state, in the future. The
throttle group state cannot be per-BlockBackend anymore, it must be
per-throttle node. This i
timer_cb() needs to know about the current Aio context of the throttle
request that is woken up. In order to make ThrottleGroupMember backend
agnostic, this information is stored in an aio_context field instead of
accessing it from BlockBackend.
Reviewed-by: Alberto Garcia
Reviewed-by: Stefan Haj
block/throttle.c uses existing I/O throttle infrastructure inside a
block filter driver. I/O operations are intercepted in the filter's
read/write coroutines, and referred to block/throttle-groups.c
The driver can be used with the syntax
-drive driver=throttle,file.filename=foo.qcow2, \
li
Move the CoMutex and CoQueue inits inside throttle_group_register_tgm()
which is called whenever a ThrottleGroupMember is initialized. There's
no need for them to be separate.
Reviewed-by: Alberto Garcia
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Manos Pitsidianakis
---
block/block-backend.c
This series adds a throttle block driver filter. Currently throttling is done
at the BlockBackend level. Using block driver interfaces we can move the
throttling to any point in the BDS graph using a throttle node which uses the
existing throttling code. This allows for potentially more complex
con
Signed-off-by: Manos Pitsidianakis
---
tests/qemu-iotests/184 | 310 +
tests/qemu-iotests/184.out | 422 +
tests/qemu-iotests/group | 1 +
3 files changed, 733 insertions(+)
create mode 100755 tests/qemu-iotests/
On Tue, Aug 15, 2017 at 02:42:21PM +1000, Sam Bobroff wrote:
> KVM now allows writing to KVM_CAP_PPC_SMT which has previously been
> read only. Doing so causes KVM to act, for that VM, as if the host's
> SMT mode was the given value. This is particularly important on Power
> 9 systems because their
On Thu, Aug 17, 2017 at 11:26:56AM +0800, Wei Wang wrote:
> Add a new vq to report hints of guest free pages to the host.
>
> Signed-off-by: Wei Wang
> Signed-off-by: Liang Li
> ---
> drivers/virtio/virtio_balloon.c | 167
> +++-
> include/uapi/linux/virtio_
On Thu, Aug 17, 2017 at 11:26:54AM +0800, Wei Wang wrote:
> Add a new feature, VIRTIO_BALLOON_F_SG, which enables the transfer
> of balloon (i.e. inflated/deflated) pages using scatter-gather lists
> to the host.
>
> The implementation of the previous virtio-balloon is not very
> efficient, becaus
On Thu, Aug 17, 2017 at 11:26:56AM +0800, Wei Wang wrote:
> Add a new vq to report hints of guest free pages to the host.
Please add some text here explaining the report_free_page_signal
thing.
I also really think we need some kind of ID in the
buffer to do a handshake. whenever id changes you
a
Hi,
On 08/17/2017 10:01 PM, Darius Goad wrote:
Hello. I'm Melissa, a trans woman who is the main developer of the nVidia
emulation code for 86Box. I'm interested in porting this code over to QEMU
as QEMU has higher compatibility with newer operating systems, as well as
expanding the developer ba
On Sun, Aug 13, 2017 at 07:04:38PM +0200, BALATON Zoltan wrote:
You know I'm going to say it, right: needs a commit message.
What's a "plb-pcix", and what's an example of a 440 SoCs which has it.
This is basically a new device, so I'm pretty willing to merge for
2.11 with minimal review once reb
On 08/17/2017 10:02 PM, Thomas Huth wrote:
On 17.08.2017 10:41, Cornelia Huck wrote:
On Thu, 17 Aug 2017 08:25:09 +0200
Thomas Huth wrote:
With some small modifications, we can also use the the netfilter,
the fiter-mirror and the filter-redirector tests on s390x.
s/fiter/filter/
OK ... co
On Sun, Aug 13, 2017 at 07:04:38PM +0200, BALATON Zoltan wrote:
> Enough to please U-Boot and make it able to detect SDRAM SPD EEPROMs
>
> Signed-off-by: François Revol
> Signed-off-by: BALATON Zoltan
I don't have the knowledge to review this deeply (or, rather, I don't
have the time to refresh
On Thu, Aug 17, 2017 at 08:33:10PM +0200, Thomas Huth wrote:
> QEMU currently crashes when trying to use a 'pc-dimm' on the pseries
> machine without specifying its 'memdev' property. Let's add a sanity
> check to the pre_plug handler to fix this issue.
>
> Signed-off-by: Thomas Huth
Thanks for
On Thu, Aug 17, 2017 at 05:23:46PM +0100, Anthony PERARD wrote:
> This means that the function will be call and the property
> acpi-pcihp-bsel will be set even if ACPI build is disable.
>
> To do PCI passthrough with Xen, the property acpi-pcihp-bsel needs to be
> set, but this was done only when
Hello. I'm Melissa, a trans woman who is the main developer of the nVidia
emulation code for 86Box. I'm interested in porting this code over to QEMU
as QEMU has higher compatibility with newer operating systems, as well as
expanding the developer base for nVidia graphics card emulation.
The 86Box
On 08/18/17 02:16, Laszlo Ersek wrote:
> On 08/17/17 22:57, Laszlo Ersek wrote:
>> On 08/04/17 12:49, Paolo Bonzini wrote:
>>> On 04/08/2017 10:36, Hannes Reinecke wrote:
The LUN0 emulation is just that, an emulation for a non-existing
LUN0. So we should be returning LUN_NOT_SUPPORTED for
On 08/17/17 22:57, Laszlo Ersek wrote:
> On 08/04/17 12:49, Paolo Bonzini wrote:
>> On 04/08/2017 10:36, Hannes Reinecke wrote:
>>> The LUN0 emulation is just that, an emulation for a non-existing
>>> LUN0. So we should be returning LUN_NOT_SUPPORTED for any request
>>> coming from any other LUN.
>
On 08/17/2017 08:01 PM, Richard Henderson wrote:
Nothing uses or enables them yet.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
tcg/tcg.h | 5 +
tcg/tcg.c | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index d
On 08/17/2017 08:01 PM, Richard Henderson wrote:
Add with value 0 so that structure zero initialization can
indicate that the field is not present.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
tcg/tcg-opc.h | 2 ++
tcg/tcg.c | 3 +++
2 files changed, 5 i
On 08/17/2017 08:01 PM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
tcg/tcg.h | 2 +
tcg/tcg.c | 310 ++
2 files changed, 312 insertions(+)
diff --git a/tcg/tcg.h b/tcg/t
To enable hotplugging of a newly created pcie-pci-bridge,
we need to tell firmware (e.g. SeaBIOS) to reserve
additional buses or IO/MEM/PREF space for pcie-root-port.
Additional bus reservation allows us to hotplug pcie-pci-bridge into this root
port.
The number of buses and IO/MEM/PREF space to r
Signed-off-by: Aleksandr Bezzubikov
Reviewed-by: Laszlo Ersek
Reviewed-by: Marcel Apfelbaum
---
docs/pcie.txt| 49 ++--
docs/pcie_pci_bridge.txt | 114 +++
2 files changed, 140 insertions(+), 23 deletions(-)
create mode 1
On PCI init PCI bridges may need some extra info about bus number,
IO, memory and prefetchable memory to reserve. QEMU can provide this
with a special vendor-specific PCI capability.
Signed-off-by: Aleksandr Bezzubikov
Reviewed-by: Marcel Apfelbaum
---
hw/pci/pci_bridge.c | 46 +
This series introduces a new device - Generic PCI Express to PCI bridge,
and also makes all necessary changes to enable hotplug of the bridge itself
and any device into the bridge.
Changes v6->v7:
Change IO/MEM/PREF reservation properties type to SIZE.
Changes v5->v6:
1. Fix indentation in the ca
Introduce a new PCIExpress-to-PCI Bridge device,
which is a hot-pluggable PCI Express device and
supports devices hot-plug with SHPC.
This device is intended to replace the DMI-to-PCI Bridge.
Signed-off-by: Aleksandr Bezzubikov
Reviewed-by: Marcel Apfelbaum
---
hw/pci-bridge/Makefile.objs
On PCI init PCI bridge devices may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits. QEMU can provide this
with special vendor-specific PCI capability.
This capability is intended to be used only
for Red Hat PCI bridges, i.e. QEMU cooperation.
Signed-off
Refactor pci_find_capability function to get bdf instead of
a whole pci_device* as the only necessary field for this function
is still bdf.
Signed-off-by: Aleksandr Bezzubikov
Reviewed-by: Marcel Apfelbaum
---
src/fw/pciinit.c| 4 ++--
src/hw/pci.c| 25 +
sr
Now PCI bridges get a bus range number on a system init,
basing on currently plugged devices. That's why when one wants to hotplug
another bridge,
it needs his child bus, which the parent is unable to provide (speaking about
virtual device).
The suggested workaround is to have vendor-specific cap
In case of Red Hat Generic PCIE Root Port reserve additional buses
and/or IO/MEM/PREF space, which values are provided in a vendor-specific
capability.
Signed-off-by: Aleksandr Bezzubikov
Reviewed-by: Marcel Apfelbaum
---
src/fw/pciinit.c | 106 +
On Tue, Aug 15, 2017 at 4:41 PM Markus Armbruster wrote:
> Marc-André Lureau writes:
>
> > The type_seen member can be of a different type than the 'qtype' being
> > checked, since a string create several conflicts. Lookup the real
> > conflicting type in the conflict set, that one must be prese
Now PCI bridges get a bus range number on a system init,
basing on currently plugged devices. That's why when one wants to hotplug
another bridge,
it needs his child bus, which the parent is unable to provide (speaking about
virtual device).
The suggested workaround is to have vendor-specific cap
Refactor pci_find_capability function to get bdf instead of
a whole pci_device* as the only necessary field for this function
is still bdf.
Signed-off-by: Aleksandr Bezzubikov
Reviewed-by: Marcel Apfelbaum
---
src/fw/pciinit.c| 4 ++--
src/hw/pci.c| 25 +
sr
In case of Red Hat Generic PCIE Root Port reserve additional buses
and/or IO/MEM/PREF space, which values are provided in a vendor-specific
capability.
Signed-off-by: Aleksandr Bezzubikov
Reviewed-by: Marcel Apfelbaum
---
src/fw/pciinit.c | 106 +
On PCI init PCI bridge devices may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits. QEMU can provide this
with special vendor-specific PCI capability.
This capability is intended to be used only
for Red Hat PCI bridges, i.e. QEMU cooperation.
Signed-off
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 46 +-
tcg/tcg-opc.h | 12 +-
tcg/i386/tcg-target.inc.c | 382 ++
3 files changed, 399 insertions(+), 41 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-t
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.h | 4 +
tcg/tcg.h | 6 +-
tcg/tcg-op-gvec.c | 230 +++---
tcg/tcg.c | 8 +-
4 files changed, 197 insertions(+), 51 deletions(-)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-
Add with value 0 so that structure zero initialization can
indicate that the field is not present.
Signed-off-by: Richard Henderson
---
tcg/tcg-opc.h | 2 ++
tcg/tcg.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 9162125fac..b1445a4c24 100644
--
When Alex and I started talking about this topic, this is the direction
I was thinking. The primary difference from Alex's version is that the
interface on the target/cpu/ side uses offsets and not a faux temp. The
secondary difference is that, for smaller vector sizes at least, I will
expand to
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 2 +
tcg/tcg.c | 310 ++
2 files changed, 312 insertions(+)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index b9e15da13b..b443143b21 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -962,6 +962,8 @@ do
Signed-off-by: Richard Henderson
---
Makefile.target| 5 +-
tcg/tcg-op-gvec.h | 88 ++
tcg/tcg-runtime.h | 16 ++
tcg/tcg-op-gvec.c | 443 +
tcg/tcg-runtime-gvec.c | 199 ++
5 files changed, 749
Nothing uses or implements them yet.
Signed-off-by: Richard Henderson
---
tcg/tcg-opc.h | 89 +++
tcg/tcg.h | 24
2 files changed, 113 insertions(+)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 956fb1e9f3..9162125f
Nothing uses or enables them yet.
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 5 +
tcg/tcg.c | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index dd97095af5..1277caed3d 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -256,6 +256,11 @@ typedef struc
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 137 -
1 file changed, 87 insertions(+), 50 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..025354f983 100644
--- a/target/arm/transla
x86 is not the only architecture supported by multiboot.
For example GRUB supports MIPS architecture as well.
Signed-off-by: Anatol Pomozov
---
hw/i386/multiboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c
index 19113c0fce..a492
Multiboot may load section headers and all sections (even those that are
not part of any segment) to target memory.
Tested with an ELF application that uses data from strings table
section.
Signed-off-by: Anatol Pomozov
---
hw/core/loader.c | 8 ++--
hw/i386/multiboot.c | 83 +++
Using C structs makes the code more readable and prevents type conversion
errors.
Borrow multiboot1 header from GRUB project.
Signed-off-by: Anatol Pomozov
---
hw/i386/multiboot.c| 124 +-
hw/i386/multiboot_header.h | 254 +
On 08/17/2017 04:52 AM, David Gibson wrote:
On Tue, Aug 15, 2017 at 05:28:46PM -0300, Daniel Henrique Barboza wrote:
This patch is a follow up on the discussions that started with
Laurent's patch series "spapr: disable hotplugging without OS" [1]
and discussions made at patch "spapr: reset DRC
On 07.08.2017 19:50, Paolo Bonzini wrote:
>Not much to say, unfortunately. It's pretty much the same capabilities
>as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It
>also lacks FlexPriority compared to the Conroe I had checked.
>
>It's not great that even the revert patch do
On 17.08.2017 22:58, Gerhard Wiesinger wrote:
>
> On 07.08.2017 19:50, Paolo Bonzini wrote:
>
> >Not much to say, unfortunately. It's pretty much the same capabilities
> >as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It
> >also lacks FlexPriority compared to the Conroe I had
On 08/04/17 12:49, Paolo Bonzini wrote:
> On 04/08/2017 10:36, Hannes Reinecke wrote:
>> The LUN0 emulation is just that, an emulation for a non-existing
>> LUN0. So we should be returning LUN_NOT_SUPPORTED for any request
>> coming from any other LUN.
>> And we should be aborting unhandled command
On Thu Aug 17, 2017 at 05:26:53PM +0200, Auger Eric wrote:
> Hi Linu, Jean,
>
> On 17/08/2017 15:39, Jean-Philippe Brucker wrote:
> > Hi Linu,
> >
> > On 17/08/17 12:26, Linu Cherian wrote:
> >> Hi Eric,
> >>
> >> On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote:
> >>> This series implem
Hi
On Tue, Aug 8, 2017 at 8:04 AM, Kevin Wolf wrote:
> Am 04.08.2017 um 06:53 hat Anatol Pomozov geschrieben:
>> Hi Kevin
>>
>> Thanks for the information.
>>
>> So I sounds like we do want multiboot to load all sections regardless
>> of its segments info. To achieve it we need to read sections h
On 08/17/2017 11:04 AM, Alex Bennée wrote:
> +int32_t *rd = (int32_t *) d;
> +int16_t *rn = (int16_t *) n;
> +int16_t rm = (int16_t) m;
> +int i;
> +
> +#pragma GCC ivdep
> +for (i = 0; i < opr_elt; ++i) {
> +rd[i] = rn[i + doff_elt] * rm;
> +}
You need to run t
On 08/17/2017 11:04 AM, Alex Bennée wrote:
> -static const char *regnames[] = {
> +static const char *x_regnames[] = {
> "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
> "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
> "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
On 08/17/2017 11:04 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> target/arm/cpu.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 08/17/2017 11:03 AM, Alex Bennée wrote:
> As we operate directly on the vectors in memory we pass around the
> address for TCG_TYPE_VECTOR. Currently only helpers ever see these
> values but if we were to generate simd backend instructions they would
> load directly from the backing store.
>
>
On 08/17/2017 11:03 AM, Alex Bennée wrote:
> Currently it only makes sense for globals - i.e. registers directly
> mapped to CPUEnv.
> ---
> tcg/README | 1 +
> tcg/tcg.h | 20
> 2 files changed, 21 insertions(+)
I'm not keen on this. I know it makes for nicer intermediate
On 08/17/2017 11:03 AM, Alex Bennée wrote:
> Although the other types are aliases lets make it clear what TCG types
> are available.
>
> Signed-off-by: Alex Bennée
> ---
> tcg/README | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 08/17/2017 02:55 PM, Alistair Francis wrote:
On 15/08/2017 09:30, Markus Armbruster wrote:
The stupid fix is to repeat libraries until the link succeeds:
test-util-obj-y = libqemuutil.a libqemustub.a libqemuutil.a
[...]
Sticking '-Wp,-(' and '-Wp,-)' into the command line I get from
This workaround should help you avoid problems with Windows NT 4.0.
Create the disk image for the hard drive that is 4GB or less in size:
qemu-img create -f qcow2 .qcow2 4G
Run QEMU booting from the CD-ROM. I assume you used the Windows NT 4.0
workstation CD.
qemu-system-i386 -cpu pentium -vga
On 08/17/2017 02:02 PM, Markus Armbruster wrote:
Paolo Bonzini writes:
On 15/08/2017 09:30, Markus Armbruster wrote:
The stupid fix is to repeat libraries until the link succeeds:
test-util-obj-y = libqemuutil.a libqemustub.a libqemuutil.a
You may have seen this with -lX11 if you're old
If you forget to add -cpu 486 or -cpu pentium your disk image will be
corrupted and the display will display random characters.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1706296
Title:
Booting
The EP108 is the same as the ZCU102, mark it as deprecated as we don't
need two machines.
Signed-off-by: Alistair Francis
---
hw/arm/xlnx-zcu102.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 8a53221d0a..54207ba095 100644
If the user sets the secure property to true we want to enalbe both EL2
and EL3.
Signed-off-by: Alistair Francis
---
hw/arm/xlnx-zynqmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 9eceadbdc8..d6ca5dcd4e 100644
--- a/hw/
In preperation for future work let's manually create the Xilnx machines.
This will allow us to set properties for the machines in the future.
Signed-off-by: Alistair Francis
---
hw/arm/xlnx-zcu102.c | 75 +++-
1 file changed, 68 insertions(+), 7 d
The EL2 and EL3 work is working well now and interanlly we now have
tests that expect to start in EL3 and transition through EL2 to EL1. To
make this easy to run let's expose the secure property to the machine
and then use that to enable EL2.
This series also does some machine/name tidying up and
On 08/17/2017 12:54 AM, Markus Armbruster wrote:
> John Snow writes:
>
>> On 08/14/2017 05:57 PM, Eduardo Habkost wrote:
>>> Example output when using "-machine q35":
>>>
>>> {
>>> "available": true,
>>> "count": 1,
>>> "device-types": [
>>> "ide-device"
>>> ],
>>> "
Hi Paolo,
On 08/17/2017 11:45 AM, Paolo Bonzini wrote:
On 15/08/2017 19:00, Brijesh Singh wrote:
The following features bits have been added/removed compare to Opteron_G5
Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
fsgsbase, bmi1, avx2, smep, bmi2, rdseed, a
QEMU currently crashes when trying to use a 'pc-dimm' on the pseries
machine without specifying its 'memdev' property. Let's add a sanity
check to the pre_plug handler to fix this issue.
Signed-off-by: Thomas Huth
---
hw/ppc/spapr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20170817180404.29334-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n
Dne 17.8.2017 v 07:24 Markus Armbruster napsal(a):
> Lukáš Doktor writes:
>
>> Dne 16.8.2017 v 18:58 Markus Armbruster napsal(a):
>>> Lukáš Doktor writes:
>>>
Dne 15.8.2017 v 14:31 Markus Armbruster napsal(a):
> Lukáš Doktor writes:
>
>> No actual code changes, just several pyl
These are the integer registers as will become clear when we start
declaring the vector ones.
Signed-off-by: Alex Bennée
---
target/arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..80
These instructions show up in the ffmpeg profile from the
ff_simple_idct_put_neon function.
WARNING: this is experimental and essentially shortcuts to the
vectorised helper for the one instruction that shows up a lot in the
ffmpeg trace. Otherwise it falls through to the normal code
generation. We
This is used to pass constant information to the helper. This includes
immediate data and element counts/offsets.
Signed-off-by: Alex Bennée
---
target/arm/advsimd_helper_flags.h | 50 +++
target/arm/helper-a64.c | 1 +
target/arm/translate-a64.c
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b39d64aa0b..cdd47cb868 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -457,8 +457,8 @@ typedef struct CPUARMState {
As we operate directly on the vectors in memory we pass around the
address for TCG_TYPE_VECTOR. Currently only helpers ever see these
values but if we were to generate simd backend instructions they would
load directly from the backing store.
We also need to ensure when copying from one temp regis
Hi,
With upcoming work on SVE I've been looking at the way we implement
vector registers in QEMU's TCG. The current orthodoxy is to decompose
the vector into a series of TCG registers, often calling a helper
function the calculation of each element. The result of the helper is
then is then stored
Register the vector registers with TCG.
Signed-off-by: Alex Bennée
---
target/arm/translate-a64.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 805af51900..b5f48605a7 100644
--- a/target/ar
---
include/exec/helper-head.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index 1cfc43b9ff..3fb4c3fc39 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -23,6 +23,7 @@
#define GET_TCGV_i32 GET_TCGV_I32
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